From: patrice.chotard@st.com (Patrice Chotard)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec
Date: Tue, 28 Jun 2016 13:55:36 +0200 [thread overview]
Message-ID: <577265B8.5030009@st.com> (raw)
In-Reply-To: <20160628094914.GI1041@n2100.armlinux.org.uk>
Hi Russell
On 06/28/2016 11:49 AM, Russell King - ARM Linux wrote:
> On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard at st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch implements the write_sec callback that handle PL310
>> secure registers writes.
>> This callback is just a stub for now, to avoid system crash.
>> Later, it could handle SMC calls so that TZ handles the needed writes.
> Is there much point having the L2 cache DT node enabled if you have
> no support for the writes, which are required for the hardware to be
> enabled?
>
It's similar to what has been done for ux500 machine, in non secure
mode, we
can't write in L2 cache secure registers.
Patrice
WARNING: multiple messages have this Message-ID (diff)
From: Patrice Chotard <patrice.chotard@st.com>
To: Russell King - ARM Linux <linux@armlinux.org.uk>
Cc: <linux-arm-kernel@lists.infradead.org>, <kernel@stlinux.com>,
<linux-kernel@vger.kernel.org>, <peter.griffin@linaro.org>,
<lee.jones@linaro.org>
Subject: Re: [PATCH] ARM: sti: Implement dummy L2 cache's write_sec
Date: Tue, 28 Jun 2016 13:55:36 +0200 [thread overview]
Message-ID: <577265B8.5030009@st.com> (raw)
In-Reply-To: <20160628094914.GI1041@n2100.armlinux.org.uk>
Hi Russell
On 06/28/2016 11:49 AM, Russell King - ARM Linux wrote:
> On Tue, Jun 28, 2016 at 11:40:37AM +0200, patrice.chotard@st.com wrote:
>> From: Patrice Chotard <patrice.chotard@st.com>
>>
>> This patch implements the write_sec callback that handle PL310
>> secure registers writes.
>> This callback is just a stub for now, to avoid system crash.
>> Later, it could handle SMC calls so that TZ handles the needed writes.
> Is there much point having the L2 cache DT node enabled if you have
> no support for the writes, which are required for the hardware to be
> enabled?
>
It's similar to what has been done for ux500 machine, in non secure
mode, we
can't write in L2 cache secure registers.
Patrice
next prev parent reply other threads:[~2016-06-28 11:55 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-28 9:40 [PATCH] ARM: sti: Implement dummy L2 cache's write_sec patrice.chotard at st.com
2016-06-28 9:40 ` patrice.chotard
2016-06-28 9:49 ` Russell King - ARM Linux
2016-06-28 9:49 ` Russell King - ARM Linux
2016-06-28 11:55 ` Patrice Chotard [this message]
2016-06-28 11:55 ` Patrice Chotard
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