* [PATCH 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-07-01 7:36 ` Caesar Wang 0 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: Marc Zyngier, Heiko Stuebner Cc: dianders-F7+t8E8rja9g9hUCZPvPmw, Will Deacon, briannorris-hpIqsD4AKlfQT0dZR+AlfA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, cf-TNX95d0MmH7DzftRWevZcw, huangtao-TNX95d0MmH7DzftRWevZcw, jay.xu-TNX95d0MmH7DzftRWevZcw, Caesar Wang, devicetree-u79uwXL29TY76Z2rM5mHXA, David Wu, Masahiro Yamada, Brian Norris, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Mark Rutland, Rob Herring, Catalin Marinas, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Hello Heiko, Marc & ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. As my do some tests with ChromeOs for my rk3399 board. TEST=$perf list |grep Hardware cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] .. Also, localhost / # perf stat sleep 1 watch the Hardware event. e.g.: 2375647 instructions # 0.79 insns per cycle 18482 branch-misses # 0.00% of all branches -- And perf top/stat to watch the hardware event. That work for me on now. -Caesar Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 124 +++++++++++++++++++------------ 1 file changed, 75 insertions(+), 49 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-07-01 7:36 ` Caesar Wang 0 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: Marc Zyngier, Heiko Stuebner Cc: dianders, Will Deacon, briannorris, linux-rockchip, cf, huangtao, jay.xu, Caesar Wang, devicetree, David Wu, Masahiro Yamada, Brian Norris, linux-kernel, Mark Rutland, Rob Herring, Catalin Marinas, linux-arm-kernel Hello Heiko, Marc & ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. As my do some tests with ChromeOs for my rk3399 board. TEST=$perf list |grep Hardware cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] .. Also, localhost / # perf stat sleep 1 watch the Hardware event. e.g.: 2375647 instructions # 0.79 insns per cycle 18482 branch-misses # 0.00% of all branches -- And perf top/stat to watch the hardware event. That work for me on now. -Caesar Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 124 +++++++++++++++++++------------ 1 file changed, 75 insertions(+), 49 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs @ 2016-07-01 7:36 ` Caesar Wang 0 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: linux-arm-kernel Hello Heiko, Marc & ARM guys When Jay first submitted the rk3399.dtsi upstream <https://patchwork.kernel.org/patch/8885821/> he had the PMU node in there, but then took it out because the upstream binding wasn't done yet. It looks as if the upstream stuff has landed, since in linux/master I see: 287e9357abcc DT/arm,gic-v3: Documment PPI partition support e3825ba1af3a irqchip/gic-v3: Add support for partitioned PPIs 9e2c986cb460 irqchip: Add per-cpu interrupt partitioning library 222df54fd8b7 genirq: Allow the affinity of a percpu interrupt to be set/retrieved 651e8b54abde irqdomain: Allow domain matching on irq_fwspec This series patches add to support the rk3399 SoCs PMU. As my do some tests with ChromeOs for my rk3399 board. TEST=$perf list |grep Hardware cpu-cycles OR cycles [Hardware event] instructions [Hardware event] cache-references [Hardware event] branch-instructions OR branches [Hardware event] branch-misses [Hardware event] .. Also, localhost / # perf stat sleep 1 watch the Hardware event. e.g.: 2375647 instructions # 0.79 insns per cycle 18482 branch-misses # 0.00% of all branches -- And perf top/stat to watch the hardware event. That work for me on now. -Caesar Caesar Wang (2): arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs arm64: dts: rockchip: support the pmu node for rk3399 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 124 +++++++++++++++++++------------ 1 file changed, 75 insertions(+), 49 deletions(-) -- 1.9.1 ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs 2016-07-01 7:36 ` Caesar Wang @ 2016-07-01 7:36 ` Caesar Wang -1 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: Marc Zyngier, Heiko Stuebner Cc: dianders, Will Deacon, briannorris, linux-rockchip, cf, huangtao, jay.xu, Caesar Wang, linux-arm-kernel, Rob Herring, Mark Rutland, Catalin Marinas, Brian Norris, David Wu, devicetree, linux-kernel Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 98 ++++++++++++++++---------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a6dd623..8f0a069 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -159,10 +159,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; xin24m: xin24m { @@ -181,8 +181,8 @@ dmac_bus: dma-controller@ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -191,8 +191,8 @@ dmac_peri: dma-controller@ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; @@ -203,7 +203,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -216,7 +216,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -228,7 +228,7 @@ sdhci: sdhci@fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; @@ -244,7 +244,7 @@ usb_host0_ehci: usb@fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -253,7 +253,7 @@ usb_host0_ohci: usb@fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -262,7 +262,7 @@ usb_host1_ehci: usb@fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -271,7 +271,7 @@ usb_host1_ohci: usb@fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -279,7 +279,7 @@ gic: interrupt-controller@fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -290,7 +290,7 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; its: interrupt-controller@fee20000 { compatible = "arm,gic-v3-its"; msi-controller; @@ -305,7 +305,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -320,7 +320,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -335,7 +335,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -350,7 +350,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -365,7 +365,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -380,7 +380,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -393,7 +393,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -406,7 +406,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -419,7 +419,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -432,7 +432,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -445,7 +445,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -458,7 +458,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -471,7 +471,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -484,7 +484,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -497,7 +497,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -577,7 +577,7 @@ tsadc: tsadc@ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <750000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; @@ -611,7 +611,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -624,7 +624,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -639,7 +639,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -654,7 +654,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -669,7 +669,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -778,13 +778,13 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; }; rktimer: rktimer@ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -792,7 +792,7 @@ spdif: spdif@ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -806,7 +806,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -819,7 +819,7 @@ i2s1: i2s@ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -832,7 +832,7 @@ i2s2: i2s@ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -852,7 +852,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -865,7 +865,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -878,7 +878,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -891,7 +891,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -904,7 +904,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on rk3399 SoCs @ 2016-07-01 7:36 ` Caesar Wang 0 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: linux-arm-kernel Add the interrupts cells value for 4, and the 4th cell is zero. Due to the doc[0] said:" the system requires describing PPI affinity, then the value must be at least 4" The 4th cell is a phandle to a node describing a set of CPUs this interrupt is affine to. The interrupt must be a PPI, and the node pointed must be a subnode of the "ppi-partitions" subnode. For interrupt types other than PPI or PPIs that are not partitionned, this cell must be zero. See the "ppi-partitions" node description below. [0]: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel at lists.infradead.org --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 98 ++++++++++++++++---------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a6dd623..8f0a069 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -159,10 +159,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, - <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; xin24m: xin24m { @@ -181,8 +181,8 @@ dmac_bus: dma-controller at ff6d0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6d0000 0x0 0x4000>; - interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC0_PERILP>; clock-names = "apb_pclk"; @@ -191,8 +191,8 @@ dmac_peri: dma-controller at ff6e0000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xff6e0000 0x0 0x4000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <1>; clocks = <&cru ACLK_DMAC1_PERILP>; clock-names = "apb_pclk"; @@ -203,7 +203,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe310000 0x0 0x4000>; - interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; @@ -216,7 +216,7 @@ compatible = "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe320000 0x0 0x4000>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; clock-freq-min-max = <400000 150000000>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; @@ -228,7 +228,7 @@ sdhci: sdhci at fe330000 { compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; arasan,soc-ctl-syscon = <&grf>; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; @@ -244,7 +244,7 @@ usb_host0_ehci: usb at fe380000 { compatible = "generic-ehci"; reg = <0x0 0xfe380000 0x0 0x20000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -253,7 +253,7 @@ usb_host0_ohci: usb at fe3a0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3a0000 0x0 0x20000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; clock-names = "hclk_host0", "hclk_host0_arb"; status = "disabled"; @@ -262,7 +262,7 @@ usb_host1_ehci: usb at fe3c0000 { compatible = "generic-ehci"; reg = <0x0 0xfe3c0000 0x0 0x20000>; - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -271,7 +271,7 @@ usb_host1_ohci: usb at fe3e0000 { compatible = "generic-ohci"; reg = <0x0 0xfe3e0000 0x0 0x20000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; clock-names = "hclk_host1", "hclk_host1_arb"; status = "disabled"; @@ -279,7 +279,7 @@ gic: interrupt-controller at fee00000 { compatible = "arm,gic-v3"; - #interrupt-cells = <3>; + #interrupt-cells = <4>; #address-cells = <2>; #size-cells = <2>; ranges; @@ -290,7 +290,7 @@ <0x0 0xfff00000 0 0x10000>, /* GICC */ <0x0 0xfff10000 0 0x10000>, /* GICH */ <0x0 0xfff20000 0 0x10000>; /* GICV */ - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; its: interrupt-controller at fee20000 { compatible = "arm,gic-v3-its"; msi-controller; @@ -305,7 +305,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c1_xfer>; #address-cells = <1>; @@ -320,7 +320,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c2_xfer>; #address-cells = <1>; @@ -335,7 +335,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c3_xfer>; #address-cells = <1>; @@ -350,7 +350,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c5_xfer>; #address-cells = <1>; @@ -365,7 +365,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c6_xfer>; #address-cells = <1>; @@ -380,7 +380,7 @@ assigned-clock-rates = <200000000>; clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c7_xfer>; #address-cells = <1>; @@ -393,7 +393,7 @@ reg = <0x0 0xff180000 0x0 0x100>; clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -406,7 +406,7 @@ reg = <0x0 0xff190000 0x0 0x100>; clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -419,7 +419,7 @@ reg = <0x0 0xff1a0000 0x0 0x100>; clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -432,7 +432,7 @@ reg = <0x0 0xff1b0000 0x0 0x100>; clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -445,7 +445,7 @@ reg = <0x0 0xff1c0000 0x0 0x1000>; clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; #address-cells = <1>; @@ -458,7 +458,7 @@ reg = <0x0 0xff1d0000 0x0 0x1000>; clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; #address-cells = <1>; @@ -471,7 +471,7 @@ reg = <0x0 0xff1e0000 0x0 0x1000>; clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; #address-cells = <1>; @@ -484,7 +484,7 @@ reg = <0x0 0xff1f0000 0x0 0x1000>; clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; #address-cells = <1>; @@ -497,7 +497,7 @@ reg = <0x0 0xff200000 0x0 0x1000>; clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; #address-cells = <1>; @@ -577,7 +577,7 @@ tsadc: tsadc at ff260000 { compatible = "rockchip,rk3399-tsadc"; reg = <0x0 0xff260000 0x0 0x100>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; assigned-clocks = <&cru SCLK_TSADC>; assigned-clock-rates = <750000>; clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; @@ -611,7 +611,7 @@ reg = <0x0 0xff350000 0x0 0x1000>; clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; clock-names = "spiclk", "apb_pclk"; - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; #address-cells = <1>; @@ -624,7 +624,7 @@ reg = <0x0 0xff370000 0x0 0x100>; clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; clock-names = "baudclk", "apb_pclk"; - interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; reg-shift = <2>; reg-io-width = <4>; pinctrl-names = "default"; @@ -639,7 +639,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c0_xfer>; #address-cells = <1>; @@ -654,7 +654,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c4_xfer>; #address-cells = <1>; @@ -669,7 +669,7 @@ assigned-clock-rates = <200000000>; clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; clock-names = "i2c", "pclk"; - interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; pinctrl-names = "default"; pinctrl-0 = <&i2c8_xfer>; #address-cells = <1>; @@ -778,13 +778,13 @@ compatible = "snps,dw-wdt"; reg = <0x0 0xff840000 0x0 0x100>; clocks = <&cru PCLK_WDT>; - interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; }; rktimer: rktimer at ff850000 { compatible = "rockchip,rk3399-timer"; reg = <0x0 0xff850000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; clock-names = "pclk", "timer"; }; @@ -792,7 +792,7 @@ spdif: spdif at ff870000 { compatible = "rockchip,rk3399-spdif"; reg = <0x0 0xff870000 0x0 0x1000>; - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 7>; dma-names = "tx"; clock-names = "mclk", "hclk"; @@ -806,7 +806,7 @@ compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff880000 0x0 0x1000>; rockchip,grf = <&grf>; - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 0>, <&dmac_bus 1>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -819,7 +819,7 @@ i2s1: i2s at ff890000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff890000 0x0 0x1000>; - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 2>, <&dmac_bus 3>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -832,7 +832,7 @@ i2s2: i2s at ff8a0000 { compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; reg = <0x0 0xff8a0000 0x0 0x1000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; dmas = <&dmac_bus 4>, <&dmac_bus 5>; dma-names = "tx", "rx"; clock-names = "i2s_clk", "i2s_hclk"; @@ -852,7 +852,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff720000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO0_PMU>; - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -865,7 +865,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff730000 0x0 0x100>; clocks = <&pmucru PCLK_GPIO1_PMU>; - interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -878,7 +878,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff780000 0x0 0x100>; clocks = <&cru PCLK_GPIO2>; - interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -891,7 +891,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff788000 0x0 0x100>; clocks = <&cru PCLK_GPIO3>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; @@ -904,7 +904,7 @@ compatible = "rockchip,gpio-bank"; reg = <0x0 0xff790000 0x0 0x100>; clocks = <&cru PCLK_GPIO4>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; gpio-controller; #gpio-cells = <0x2>; -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-07-01 7:36 ` Caesar Wang @ 2016-07-01 7:36 ` Caesar Wang -1 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: Marc Zyngier, Heiko Stuebner Cc: dianders, Will Deacon, briannorris, linux-rockchip, cf, huangtao, jay.xu, Caesar Wang, linux-arm-kernel, Rob Herring, Mark Rutland, Catalin Marinas, Brian Norris, Masahiro Yamada, David Wu, devicetree, linux-kernel As the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel@lists.infradead.org --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8f0a069..b260f62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -165,6 +165,22 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + interrupt-affinity = <&cpu_l0>, + <&cpu_l1>, + <&cpu_l2>, + <&cpu_l3>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + interrupt-affinity = <&cpu_b0>, + <&cpu_b1>; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -296,6 +312,16 @@ msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; i2c1: i2c@ff110000 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-07-01 7:36 ` Caesar Wang 0 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-01 7:36 UTC (permalink / raw) To: linux-arm-kernel As the Marc posted the patches [0] to support Partitioning per-cpu interrupts. Let's add this patch to match it on rk3399 SoCs. [0]: https://lkml.org/lkml/2016/4/11/182 Signed-off-by: Caesar Wang <wxt@rock-chips.com> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> CC: linux-arm-kernel at lists.infradead.org --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8f0a069..b260f62 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -165,6 +165,22 @@ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + interrupt-affinity = <&cpu_l0>, + <&cpu_l1>, + <&cpu_l2>, + <&cpu_l3>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + interrupt-affinity = <&cpu_b0>, + <&cpu_b1>; + }; + xin24m: xin24m { compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -296,6 +312,16 @@ msi-controller; reg = <0x0 0xfee20000 0x0 0x20000>; }; + + ppi-partitions { + part0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + part1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; }; i2c1: i2c at ff110000 { -- 1.9.1 ^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-07-01 7:36 ` Caesar Wang @ 2016-07-01 10:26 ` Mark Rutland -1 siblings, 0 replies; 13+ messages in thread From: Mark Rutland @ 2016-07-01 10:26 UTC (permalink / raw) To: Caesar Wang, marc.zyngier Cc: Heiko Stuebner, dianders, Will Deacon, briannorris, linux-rockchip, cf, huangtao, jay.xu, linux-arm-kernel, Rob Herring, Catalin Marinas, Brian Norris, Masahiro Yamada, David Wu, devicetree, linux-kernel On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: > As the Marc posted the patches [0] to support Partitioning per-cpu > interrupts. Let's add this patch to match it on rk3399 SoCs. > > [0]: > https://lkml.org/lkml/2016/4/11/182 The core IRQ support is merged, but it's worth noting that the perf code doesn't use it yet. So we still need a patch adding support to the perf code before we can change the dts. I think Marc had a prototype of that somewhere. Marc? > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel@lists.infradead.org > > --- > > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 8f0a069..b260f62 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -165,6 +165,22 @@ > <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; > }; > > + pmu_a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; > + interrupt-affinity = <&cpu_l0>, > + <&cpu_l1>, > + <&cpu_l2>, > + <&cpu_l3>; > + }; I'm not keen on having to redundantly describe the affinity in interrupt-affinity and the partition's affinity property. Those will almost certainly be out-of-sync in some DTs, and it'll be very painful to deal with. I think that for partitioned PPIs the PMU driver should use the affinity from the PPI, and not have an interrupt-affinity property. Hopefully that's relatively simple to handle. Thanks, Mark. > + > + pmu_a72 { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; > + interrupt-affinity = <&cpu_b0>, > + <&cpu_b1>; > + }; > + > xin24m: xin24m { > compatible = "fixed-clock"; > clock-frequency = <24000000>; > @@ -296,6 +312,16 @@ > msi-controller; > reg = <0x0 0xfee20000 0x0 0x20000>; > }; > + > + ppi-partitions { > + part0: interrupt-partition-0 { > + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; > + }; > + > + part1: interrupt-partition-1 { > + affinity = <&cpu_b0 &cpu_b1>; > + }; > + }; > }; > > i2c1: i2c@ff110000 { > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-07-01 10:26 ` Mark Rutland 0 siblings, 0 replies; 13+ messages in thread From: Mark Rutland @ 2016-07-01 10:26 UTC (permalink / raw) To: linux-arm-kernel On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: > As the Marc posted the patches [0] to support Partitioning per-cpu > interrupts. Let's add this patch to match it on rk3399 SoCs. > > [0]: > https://lkml.org/lkml/2016/4/11/182 The core IRQ support is merged, but it's worth noting that the perf code doesn't use it yet. So we still need a patch adding support to the perf code before we can change the dts. I think Marc had a prototype of that somewhere. Marc? > Signed-off-by: Caesar Wang <wxt@rock-chips.com> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Will Deacon <will.deacon@arm.com> > Cc: Marc Zyngier <marc.zyngier@arm.com> > CC: linux-arm-kernel at lists.infradead.org > > --- > > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > index 8f0a069..b260f62 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi > @@ -165,6 +165,22 @@ > <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; > }; > > + pmu_a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; > + interrupt-affinity = <&cpu_l0>, > + <&cpu_l1>, > + <&cpu_l2>, > + <&cpu_l3>; > + }; I'm not keen on having to redundantly describe the affinity in interrupt-affinity and the partition's affinity property. Those will almost certainly be out-of-sync in some DTs, and it'll be very painful to deal with. I think that for partitioned PPIs the PMU driver should use the affinity from the PPI, and not have an interrupt-affinity property. Hopefully that's relatively simple to handle. Thanks, Mark. > + > + pmu_a72 { > + compatible = "arm,cortex-a72-pmu"; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; > + interrupt-affinity = <&cpu_b0>, > + <&cpu_b1>; > + }; > + > xin24m: xin24m { > compatible = "fixed-clock"; > clock-frequency = <24000000>; > @@ -296,6 +312,16 @@ > msi-controller; > reg = <0x0 0xfee20000 0x0 0x20000>; > }; > + > + ppi-partitions { > + part0: interrupt-partition-0 { > + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; > + }; > + > + part1: interrupt-partition-1 { > + affinity = <&cpu_b0 &cpu_b1>; > + }; > + }; > }; > > i2c1: i2c at ff110000 { > -- > 1.9.1 > ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-07-01 10:26 ` Mark Rutland (?) @ 2016-07-01 12:50 ` Marc Zyngier -1 siblings, 0 replies; 13+ messages in thread From: Marc Zyngier @ 2016-07-01 12:50 UTC (permalink / raw) To: Mark Rutland, Caesar Wang Cc: Heiko Stuebner, dianders-F7+t8E8rja9g9hUCZPvPmw, Will Deacon, briannorris-hpIqsD4AKlfQT0dZR+AlfA, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, cf-TNX95d0MmH7DzftRWevZcw, huangtao-TNX95d0MmH7DzftRWevZcw, jay.xu-TNX95d0MmH7DzftRWevZcw, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring, Catalin Marinas, Brian Norris, Masahiro Yamada, David Wu, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA On 01/07/16 11:26, Mark Rutland wrote: > On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: >> As the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 > > The core IRQ support is merged, but it's worth noting that the perf code > doesn't use it yet. So we still need a patch adding support to the perf > code before we can change the dts. > > I think Marc had a prototype of that somewhere. > > Marc? I posted something in the original discussion, but need to respin it. Stay tuned. Thanks, M. -- Jazz is not dead. It just smells funny... -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-07-01 12:50 ` Marc Zyngier 0 siblings, 0 replies; 13+ messages in thread From: Marc Zyngier @ 2016-07-01 12:50 UTC (permalink / raw) To: Mark Rutland, Caesar Wang Cc: Heiko Stuebner, dianders, Will Deacon, briannorris, linux-rockchip, cf, huangtao, jay.xu, linux-arm-kernel, Rob Herring, Catalin Marinas, Brian Norris, Masahiro Yamada, David Wu, devicetree, linux-kernel On 01/07/16 11:26, Mark Rutland wrote: > On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: >> As the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 > > The core IRQ support is merged, but it's worth noting that the perf code > doesn't use it yet. So we still need a patch adding support to the perf > code before we can change the dts. > > I think Marc had a prototype of that somewhere. > > Marc? I posted something in the original discussion, but need to respin it. Stay tuned. Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 @ 2016-07-01 12:50 ` Marc Zyngier 0 siblings, 0 replies; 13+ messages in thread From: Marc Zyngier @ 2016-07-01 12:50 UTC (permalink / raw) To: linux-arm-kernel On 01/07/16 11:26, Mark Rutland wrote: > On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: >> As the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 > > The core IRQ support is merged, but it's worth noting that the perf code > doesn't use it yet. So we still need a patch adding support to the perf > code before we can change the dts. > > I think Marc had a prototype of that somewhere. > > Marc? I posted something in the original discussion, but need to respin it. Stay tuned. Thanks, M. -- Jazz is not dead. It just smells funny... ^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 2016-07-01 10:26 ` Mark Rutland (?) (?) @ 2016-07-06 2:55 ` Caesar Wang -1 siblings, 0 replies; 13+ messages in thread From: Caesar Wang @ 2016-07-06 2:55 UTC (permalink / raw) To: Mark Rutland, marc.zyngier Cc: Caesar Wang, huangtao, devicetree, Heiko Stuebner, Masahiro Yamada, Catalin Marinas, Brian Norris, Will Deacon, dianders, linux-kernel, linux-rockchip, Rob Herring, David Wu, cf, briannorris, jay.xu, linux-arm-kernel [-- Attachment #1: Type: text/plain, Size: 3287 bytes --] Hi Mark, On 2016?07?01? 18:26, Mark Rutland wrote: > On Fri, Jul 01, 2016 at 03:36:10PM +0800, Caesar Wang wrote: >> As the Marc posted the patches [0] to support Partitioning per-cpu >> interrupts. Let's add this patch to match it on rk3399 SoCs. >> >> [0]: >> https://lkml.org/lkml/2016/4/11/182 > The core IRQ support is merged, but it's worth noting that the perf code > doesn't use it yet. So we still need a patch adding support to the perf > code before we can change the dts. > > I think Marc had a prototype of that somewhere. > > Marc? > >> Signed-off-by: Caesar Wang <wxt@rock-chips.com> >> Cc: Heiko Stuebner <heiko@sntech.de> >> Cc: Will Deacon <will.deacon@arm.com> >> Cc: Marc Zyngier <marc.zyngier@arm.com> >> CC: linux-arm-kernel@lists.infradead.org >> >> --- >> >> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 26 ++++++++++++++++++++++++++ >> 1 file changed, 26 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> index 8f0a069..b260f62 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi >> @@ -165,6 +165,22 @@ >> <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; >> }; >> >> + pmu_a53 { >> + compatible = "arm,cortex-a53-pmu"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; >> + interrupt-affinity = <&cpu_l0>, >> + <&cpu_l1>, >> + <&cpu_l2>, >> + <&cpu_l3>; >> + }; > I'm not keen on having to redundantly describe the affinity in > interrupt-affinity and the partition's affinity property. Those will > almost certainly be out-of-sync in some DTs, and it'll be very painful > to deal with. > > I think that for partitioned PPIs the PMU driver should use the affinity > from the PPI, and not have an interrupt-affinity property. Hopefully > that's relatively simple to handle. So you are keen have the simple to handle the pmu. e.g.: + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; + }; Right? --- BTW: Do I need continue to send it for upstream or you guys will change it for all platform? Thanks - Caesar > > Thanks, > Mark. > >> + >> + pmu_a72 { >> + compatible = "arm,cortex-a72-pmu"; >> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>; >> + interrupt-affinity = <&cpu_b0>, >> + <&cpu_b1>; >> + }; >> + >> xin24m: xin24m { >> compatible = "fixed-clock"; >> clock-frequency = <24000000>; >> @@ -296,6 +312,16 @@ >> msi-controller; >> reg = <0x0 0xfee20000 0x0 0x20000>; >> }; >> + >> + ppi-partitions { >> + part0: interrupt-partition-0 { >> + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; >> + }; >> + >> + part1: interrupt-partition-1 { >> + affinity = <&cpu_b0 &cpu_b1>; >> + }; >> + }; >> }; >> >> i2c1: i2c@ff110000 { >> -- >> 1.9.1 >> > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip -- caesar wang | software engineer | wxt@rock-chip.com [-- Attachment #2: Type: text/html, Size: 5504 bytes --] ^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2016-07-06 2:55 UTC | newest] Thread overview: 13+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-07-01 7:36 [PATCH 0/2] arm64: dts: rockchip: Support PMU for rk3399 SoCs Caesar Wang 2016-07-01 7:36 ` Caesar Wang 2016-07-01 7:36 ` Caesar Wang 2016-07-01 7:36 ` [PATCH 1/2] arm64: dts: rockchip: change all interrupts cells for 4 on " Caesar Wang 2016-07-01 7:36 ` Caesar Wang 2016-07-01 7:36 ` [PATCH 2/2] arm64: dts: rockchip: support the pmu node for rk3399 Caesar Wang 2016-07-01 7:36 ` Caesar Wang 2016-07-01 10:26 ` Mark Rutland 2016-07-01 10:26 ` Mark Rutland 2016-07-01 12:50 ` Marc Zyngier 2016-07-01 12:50 ` Marc Zyngier 2016-07-01 12:50 ` Marc Zyngier 2016-07-06 2:55 ` Caesar Wang
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