From: Marc Zyngier <marc.zyngier@arm.com>
To: Andre Przywara <andre.przywara@arm.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
Eric Auger <eric.auger@redhat.com>
Cc: linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org
Subject: Re: [PATCH v9 07/17] irqchip: refactor and add GICv3 definitions
Date: Wed, 13 Jul 2016 13:28:12 +0100 [thread overview]
Message-ID: <578633DC.4070806@arm.com> (raw)
In-Reply-To: <20160713015909.28793-8-andre.przywara@arm.com>
On 13/07/16 02:58, Andre Przywara wrote:
> arm-gic-v3.h contains bit and register definitions for the GICv3 and ITS,
> at least for the bits the we currently care about.
> The ITS emulation needs more definitions, so add them and refactor
> the memory attribute #defines to be more universally usable.
> To avoid changing all users, we still provide some of the old definitons
> defined with the help of the new macros.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 174 ++++++++++++++++++++++++-------------
> 1 file changed, 114 insertions(+), 60 deletions(-)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index bfbd707..ed61647 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -112,34 +112,58 @@
> #define GICR_WAKER_ProcessorSleep (1U << 1)
> #define GICR_WAKER_ChildrenAsleep (1U << 2)
>
> -#define GICR_PROPBASER_NonShareable (0U << 10)
> -#define GICR_PROPBASER_InnerShareable (1U << 10)
> -#define GICR_PROPBASER_OuterShareable (2U << 10)
> -#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
> -#define GICR_PROPBASER_nCnB (0U << 7)
> -#define GICR_PROPBASER_nC (1U << 7)
> -#define GICR_PROPBASER_RaWt (2U << 7)
> -#define GICR_PROPBASER_RaWb (3U << 7)
> -#define GICR_PROPBASER_WaWt (4U << 7)
> -#define GICR_PROPBASER_WaWb (5U << 7)
> -#define GICR_PROPBASER_RaWaWt (6U << 7)
> -#define GICR_PROPBASER_RaWaWb (7U << 7)
> -#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
> -#define GICR_PROPBASER_IDBITS_MASK (0x1f)
> -
> -#define GICR_PENDBASER_NonShareable (0U << 10)
> -#define GICR_PENDBASER_InnerShareable (1U << 10)
> -#define GICR_PENDBASER_OuterShareable (2U << 10)
> -#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
> -#define GICR_PENDBASER_nCnB (0U << 7)
> -#define GICR_PENDBASER_nC (1U << 7)
> -#define GICR_PENDBASER_RaWt (2U << 7)
> -#define GICR_PENDBASER_RaWb (3U << 7)
> -#define GICR_PENDBASER_WaWt (4U << 7)
> -#define GICR_PENDBASER_WaWb (5U << 7)
> -#define GICR_PENDBASER_RaWaWt (6U << 7)
> -#define GICR_PENDBASER_RaWaWb (7U << 7)
> -#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
> +#define GIC_BASER_CACHE_nCnB 0ULL
> +#define GIC_BASER_CACHE_SameAsInner 0ULL
> +#define GIC_BASER_CACHE_nC 1ULL
> +#define GIC_BASER_CACHE_RaWt 2ULL
> +#define GIC_BASER_CACHE_RaWb 3ULL
> +#define GIC_BASER_CACHE_WaWt 4ULL
> +#define GIC_BASER_CACHE_WaWb 5ULL
> +#define GIC_BASER_CACHE_RaWaWt 6ULL
> +#define GIC_BASER_CACHE_RaWaWb 7ULL
> +#define GIC_BASER_CACHE_MASK 7ULL
> +#define GIC_BASER_NonShareable 0ULL
> +#define GIC_BASER_InnerShareable 1ULL
> +#define GIC_BASER_OuterShareable 2ULL
> +#define GIC_BASER_SHAREABILITY_MASK 3ULL
> +
> +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
> + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
> +
> +#define GIC_BASER_SHAREABILITY(reg, type) \
> + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
> +
> +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
> +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
> +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
> +#define GICR_PROPBASER_SHAREABILITY_MASK \
> + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
> +#define GICR_PROPBASER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
> +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
Inner Cacheability : GICR_PROPBASER_CACHEABILITY_MASK
Outer Cacheability : GICR_PROPBASER_OUTER_CACHEABILITY_MASK
Why don't we have a symmetric naming (GICR_PROPBASER_INNER_CACHEABILITY_MASK)?
I'm all for having some backward compatibility, but given
that you're adding a lot of those, you should make sure that
the new stuff is not ambiguous.
This applies throughout the file.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v9 07/17] irqchip: refactor and add GICv3 definitions
Date: Wed, 13 Jul 2016 13:28:12 +0100 [thread overview]
Message-ID: <578633DC.4070806@arm.com> (raw)
In-Reply-To: <20160713015909.28793-8-andre.przywara@arm.com>
On 13/07/16 02:58, Andre Przywara wrote:
> arm-gic-v3.h contains bit and register definitions for the GICv3 and ITS,
> at least for the bits the we currently care about.
> The ITS emulation needs more definitions, so add them and refactor
> the memory attribute #defines to be more universally usable.
> To avoid changing all users, we still provide some of the old definitons
> defined with the help of the new macros.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 174 ++++++++++++++++++++++++-------------
> 1 file changed, 114 insertions(+), 60 deletions(-)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index bfbd707..ed61647 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -112,34 +112,58 @@
> #define GICR_WAKER_ProcessorSleep (1U << 1)
> #define GICR_WAKER_ChildrenAsleep (1U << 2)
>
> -#define GICR_PROPBASER_NonShareable (0U << 10)
> -#define GICR_PROPBASER_InnerShareable (1U << 10)
> -#define GICR_PROPBASER_OuterShareable (2U << 10)
> -#define GICR_PROPBASER_SHAREABILITY_MASK (3UL << 10)
> -#define GICR_PROPBASER_nCnB (0U << 7)
> -#define GICR_PROPBASER_nC (1U << 7)
> -#define GICR_PROPBASER_RaWt (2U << 7)
> -#define GICR_PROPBASER_RaWb (3U << 7)
> -#define GICR_PROPBASER_WaWt (4U << 7)
> -#define GICR_PROPBASER_WaWb (5U << 7)
> -#define GICR_PROPBASER_RaWaWt (6U << 7)
> -#define GICR_PROPBASER_RaWaWb (7U << 7)
> -#define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
> -#define GICR_PROPBASER_IDBITS_MASK (0x1f)
> -
> -#define GICR_PENDBASER_NonShareable (0U << 10)
> -#define GICR_PENDBASER_InnerShareable (1U << 10)
> -#define GICR_PENDBASER_OuterShareable (2U << 10)
> -#define GICR_PENDBASER_SHAREABILITY_MASK (3UL << 10)
> -#define GICR_PENDBASER_nCnB (0U << 7)
> -#define GICR_PENDBASER_nC (1U << 7)
> -#define GICR_PENDBASER_RaWt (2U << 7)
> -#define GICR_PENDBASER_RaWb (3U << 7)
> -#define GICR_PENDBASER_WaWt (4U << 7)
> -#define GICR_PENDBASER_WaWb (5U << 7)
> -#define GICR_PENDBASER_RaWaWt (6U << 7)
> -#define GICR_PENDBASER_RaWaWb (7U << 7)
> -#define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
> +#define GIC_BASER_CACHE_nCnB 0ULL
> +#define GIC_BASER_CACHE_SameAsInner 0ULL
> +#define GIC_BASER_CACHE_nC 1ULL
> +#define GIC_BASER_CACHE_RaWt 2ULL
> +#define GIC_BASER_CACHE_RaWb 3ULL
> +#define GIC_BASER_CACHE_WaWt 4ULL
> +#define GIC_BASER_CACHE_WaWb 5ULL
> +#define GIC_BASER_CACHE_RaWaWt 6ULL
> +#define GIC_BASER_CACHE_RaWaWb 7ULL
> +#define GIC_BASER_CACHE_MASK 7ULL
> +#define GIC_BASER_NonShareable 0ULL
> +#define GIC_BASER_InnerShareable 1ULL
> +#define GIC_BASER_OuterShareable 2ULL
> +#define GIC_BASER_SHAREABILITY_MASK 3ULL
> +
> +#define GIC_BASER_CACHEABILITY(reg, inner_outer, type) \
> + (GIC_BASER_CACHE_##type << reg##_##inner_outer##_CACHEABILITY_SHIFT)
> +
> +#define GIC_BASER_SHAREABILITY(reg, type) \
> + (GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
> +
> +#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
> +#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
> +#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
> +#define GICR_PROPBASER_SHAREABILITY_MASK \
> + GIC_BASER_SHAREABILITY(GICR_PROPBASER, SHAREABILITY_MASK)
> +#define GICR_PROPBASER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GICR_PROPBASER, INNER, MASK)
> +#define GICR_PROPBASER_OUTER_CACHEABILITY_MASK \
> + GIC_BASER_CACHEABILITY(GICR_PROPBASER, OUTER, MASK)
Inner Cacheability : GICR_PROPBASER_CACHEABILITY_MASK
Outer Cacheability : GICR_PROPBASER_OUTER_CACHEABILITY_MASK
Why don't we have a symmetric naming (GICR_PROPBASER_INNER_CACHEABILITY_MASK)?
I'm all for having some backward compatibility, but given
that you're adding a lot of those, you should make sure that
the new stuff is not ambiguous.
This applies throughout the file.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-07-13 12:22 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-13 1:58 [PATCH v9 00/17] KVM: arm64: GICv3 ITS emulation Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 1:58 ` [PATCH v9 01/17] KVM: arm/arm64: move redistributor kvm_io_devices Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 1:58 ` [PATCH v9 02/17] KVM: arm/arm64: check return value for kvm_register_vgic_device Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 1:58 ` [PATCH v9 03/17] KVM: extend struct kvm_msi to hold a 32-bit device ID Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 10:28 ` Paolo Bonzini
2016-07-13 10:28 ` Paolo Bonzini
2016-07-13 1:58 ` [PATCH v9 04/17] KVM: arm/arm64: extend arch CAP checks to allow per-VM capabilities Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 1:58 ` [PATCH v9 05/17] KVM: kvm_io_bus: add kvm_io_bus_get_dev() call Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 10:29 ` Paolo Bonzini
2016-07-13 10:29 ` Paolo Bonzini
2016-07-13 1:58 ` [PATCH v9 06/17] KVM: arm/arm64: VGIC: add refcounting for IRQs Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 12:15 ` Marc Zyngier
2016-07-13 12:15 ` Marc Zyngier
2016-07-13 13:50 ` Andre Przywara
2016-07-13 13:50 ` Andre Przywara
2016-07-13 1:58 ` [PATCH v9 07/17] irqchip: refactor and add GICv3 definitions Andre Przywara
2016-07-13 1:58 ` Andre Przywara
2016-07-13 12:28 ` Marc Zyngier [this message]
2016-07-13 12:28 ` Marc Zyngier
2016-07-13 1:59 ` [PATCH v9 08/17] KVM: arm64: handle ITS related GICv3 redistributor registers Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 09/17] KVM: arm64: introduce ITS emulation file with MMIO framework Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 10/17] KVM: arm64: introduce new KVM ITS device Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-14 8:36 ` Marc Zyngier
2016-07-14 8:36 ` Marc Zyngier
2016-07-14 11:11 ` Andre Przywara
2016-07-14 11:11 ` Andre Przywara
2016-07-14 12:57 ` Marc Zyngier
2016-07-14 12:57 ` Marc Zyngier
2016-07-15 9:33 ` Andre Przywara
2016-07-15 9:33 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 11/17] KVM: arm64: implement basic ITS register handlers Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-14 9:13 ` Marc Zyngier
2016-07-14 9:13 ` Marc Zyngier
2016-07-13 1:59 ` [PATCH v9 12/17] KVM: arm64: connect LPIs to the VGIC emulation Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 13/17] KVM: arm64: read initial LPI pending table Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-14 9:34 ` Marc Zyngier
2016-07-14 9:34 ` Marc Zyngier
2016-07-14 10:16 ` Andre Przywara
2016-07-14 10:16 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 14/17] KVM: arm64: allow updates of LPI configuration table Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-14 9:46 ` Marc Zyngier
2016-07-14 9:46 ` Marc Zyngier
2016-07-14 10:00 ` Andre Przywara
2016-07-14 10:00 ` Andre Przywara
2016-07-14 10:10 ` Marc Zyngier
2016-07-14 10:10 ` Marc Zyngier
2016-07-13 1:59 ` [PATCH v9 15/17] KVM: arm64: implement ITS command queue command handlers Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-14 10:38 ` Marc Zyngier
2016-07-14 10:38 ` Marc Zyngier
2016-07-14 15:35 ` Andre Przywara
2016-07-14 15:35 ` Andre Przywara
2016-07-14 16:33 ` Marc Zyngier
2016-07-14 16:33 ` Marc Zyngier
2016-07-15 8:19 ` Marc Zyngier
2016-07-15 8:19 ` Marc Zyngier
2016-07-13 1:59 ` [PATCH v9 16/17] KVM: arm64: implement MSI injection in ITS emulation Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-13 1:59 ` [PATCH v9 17/17] KVM: arm64: enable ITS emulation as a virtual MSI controller Andre Przywara
2016-07-13 1:59 ` Andre Przywara
2016-07-13 7:57 ` [PATCH v9 00/17] KVM: arm64: GICv3 ITS emulation Diana Madalina Craciun
2016-07-13 7:57 ` Diana Madalina Craciun
2016-07-13 8:15 ` Andre Przywara
2016-07-13 8:15 ` Andre Przywara
2016-07-14 10:52 ` Marc Zyngier
2016-07-14 10:52 ` Marc Zyngier
2016-07-14 11:01 ` Paolo Bonzini
2016-07-14 11:01 ` Paolo Bonzini
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