* Re: [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 [not found] ` <1468861197-7620-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2016-07-22 0:10 ` Eric Huang [not found] ` <57916469.6020901-5C7GfCeVMHo@public.gmane.org> 2016-07-27 12:55 ` Deucher, Alexander 1 sibling, 1 reply; 4+ messages in thread From: Eric Huang @ 2016-07-22 0:10 UTC (permalink / raw) To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Looks good to me. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Regards, Eric On 07/18/2016 12:59 PM, Rex Zhu wrote: > Change-Id: I68aa5431146b21990a998a777e00139f0478407f > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 30e8099..962aa5e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -604,6 +604,18 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev, > return 0; > } > > +static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool enable) > +{ > + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); > + > + if (enable) > + tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; > + else > + tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; > + > + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); > +} > + > static int vce_v3_0_set_clockgating_state(void *handle, > enum amd_clockgating_state state) > { > @@ -611,6 +623,9 @@ static int vce_v3_0_set_clockgating_state(void *handle, > bool enable = (state == AMD_CG_STATE_GATE) ? true : false; > int i; > > + if (adev->asic_type == CHIP_POLARIS10) > + vce_v3_set_bypass_mode(adev, enable); > + > if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) > return 0; > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <57916469.6020901-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 [not found] ` <57916469.6020901-5C7GfCeVMHo@public.gmane.org> @ 2016-07-25 2:09 ` Alexandre Demers 0 siblings, 0 replies; 4+ messages in thread From: Alexandre Demers @ 2016-07-25 2:09 UTC (permalink / raw) To: Eric Huang, Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Please, keep a similar syntax to other functions and to the file name. "vce_v3_set_bypass_mode" should be "vce_v3_0_set_bypass_mode". Alexandre Demers On 2016-07-21 20:10, Eric Huang wrote: > Looks good to me. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> > > Regards, > Eric > > On 07/18/2016 12:59 PM, Rex Zhu wrote: >> Change-Id: I68aa5431146b21990a998a777e00139f0478407f >> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 +++++++++++++++ >> 1 file changed, 15 insertions(+) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> index 30e8099..962aa5e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> @@ -604,6 +604,18 @@ static int vce_v3_0_process_interrupt(struct >> amdgpu_device *adev, >> return 0; >> } >> +static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, >> bool enable) >> +{ >> + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); >> + >> + if (enable) >> + tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; >> + else >> + tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; >> + >> + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); >> +} >> + >> static int vce_v3_0_set_clockgating_state(void *handle, >> enum amd_clockgating_state state) >> { >> @@ -611,6 +623,9 @@ static int vce_v3_0_set_clockgating_state(void >> *handle, >> bool enable = (state == AMD_CG_STATE_GATE) ? true : false; >> int i; >> + if (adev->asic_type == CHIP_POLARIS10) >> + vce_v3_set_bypass_mode(adev, enable); >> + >> if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) >> return 0; > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 [not found] ` <1468861197-7620-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> 2016-07-22 0:10 ` [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 Eric Huang @ 2016-07-27 12:55 ` Deucher, Alexander 1 sibling, 0 replies; 4+ messages in thread From: Deucher, Alexander @ 2016-07-27 12:55 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; +Cc: Zhu, Rex > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Monday, July 18, 2016 1:00 PM > To: amd-gfx@lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 > > Change-Id: I68aa5431146b21990a998a777e00139f0478407f > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 30e8099..962aa5e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -604,6 +604,18 @@ static int vce_v3_0_process_interrupt(struct > amdgpu_device *adev, > return 0; > } > > +static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool > enable) For consistency, please change the function name to: vce_v3_0_set_bypass_mode() With that fixed: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > +{ > + u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL); > + > + if (enable) > + tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; > + else > + tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK; > + > + WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp); > +} > + > static int vce_v3_0_set_clockgating_state(void *handle, > enum amd_clockgating_state state) > { > @@ -611,6 +623,9 @@ static int vce_v3_0_set_clockgating_state(void > *handle, > bool enable = (state == AMD_CG_STATE_GATE) ? true : false; > int i; > > + if (adev->asic_type == CHIP_POLARIS10) > + vce_v3_set_bypass_mode(adev, enable); > + > if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG)) > return 0; > > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
[parent not found: <1468861197-7620-2-git-send-email-Rex.Zhu@amd.com>]
[parent not found: <1468861197-7620-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH 2/3] drm/amd/powerplay: fix issue can't enable vce dpm. [not found] ` <1468861197-7620-2-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org> @ 2016-07-22 0:17 ` Eric Huang 0 siblings, 0 replies; 4+ messages in thread From: Eric Huang @ 2016-07-22 0:17 UTC (permalink / raw) To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Looks good to me. Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com> Regards, Eric On 07/18/2016 12:59 PM, Rex Zhu wrote: > Change-Id: I4e09b1c1685657c68a1b4a73928bcaf0ac025d7d > Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> > --- > .../powerplay/hwmgr/polaris10_clockpowergating.c | 14 +++++++-- > .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 34 +++++++--------------- > .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 2 +- > 3 files changed, 22 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c > index aeec25c..3d324d8 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c > @@ -131,11 +131,19 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) > > data->vce_power_gated = bgate; > > - if (bgate) > + if (bgate) { > + cgs_set_clockgating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_CG_STATE_GATE); > + polaris10_update_vce_dpm(hwmgr, true); > polaris10_phm_powerdown_vce(hwmgr); > - else > + } else { > polaris10_phm_powerup_vce(hwmgr); > - > + polaris10_update_vce_dpm(hwmgr, false); > + cgs_set_clockgating_state(hwmgr->device, > + AMD_IP_BLOCK_TYPE_VCE, > + AMD_CG_STATE_UNGATE); > + } > return 0; > } > > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c > index 5370c0f..ab3151a 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c > @@ -4422,25 +4422,20 @@ int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) > return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate); > } > > -static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) > +int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate) > { > - const struct phm_set_power_state_input *states = > - (const struct phm_set_power_state_input *)input; > struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); > - const struct polaris10_power_state *polaris10_nps = > - cast_const_phw_polaris10_power_state(states->pnew_state); > - const struct polaris10_power_state *polaris10_cps = > - cast_const_phw_polaris10_power_state(states->pcurrent_state); > - > uint32_t mm_boot_level_offset, mm_boot_level_value; > struct phm_ppt_v1_information *table_info = > (struct phm_ppt_v1_information *)(hwmgr->pptable); > > - if (polaris10_nps->vce_clks.evclk > 0 && > - (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) { > - > - data->smc_state_table.VceBootLevel = > + if (!bgate) { > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, > + PHM_PlatformCaps_StablePState)) > + data->smc_state_table.VceBootLevel = > (uint8_t) (table_info->mm_dep_table->count - 1); > + else > + data->smc_state_table.VceBootLevel = 0; > > mm_boot_level_offset = data->dpm_table_start + > offsetof(SMU74_Discrete_DpmTable, VceBootLevel); > @@ -4453,18 +4448,14 @@ static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) > cgs_write_ind_register(hwmgr->device, > CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value); > > - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { > + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) > smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, > PPSMC_MSG_VCEDPM_SetEnabledMask, > (uint32_t)1 << data->smc_state_table.VceBootLevel); > - > - polaris10_enable_disable_vce_dpm(hwmgr, true); > - } else if (polaris10_nps->vce_clks.evclk == 0 && > - polaris10_cps != NULL && > - polaris10_cps->vce_clks.evclk > 0) > - polaris10_enable_disable_vce_dpm(hwmgr, false); > } > > + polaris10_enable_disable_vce_dpm(hwmgr, !bgate); > + > return 0; > } > > @@ -4651,11 +4642,6 @@ static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i > "Failed to generate DPM level enabled mask!", > result = tmp_result); > > - tmp_result = polaris10_update_vce_dpm(hwmgr, input); > - PP_ASSERT_WITH_CODE((0 == tmp_result), > - "Failed to update VCE DPM!", > - result = tmp_result); > - > tmp_result = polaris10_update_sclk_threshold(hwmgr); > PP_ASSERT_WITH_CODE((0 == tmp_result), > "Failed to update SCLK threshold!", > diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h > index 402f5c0..dabbb5d 100644 > --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h > +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h > @@ -353,6 +353,6 @@ int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); > int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); > int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); > int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); > - > +int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate); > #endif > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-07-22 0:10 ` [PATCH 1/3] drm/amdgpu: add bypass mode for vce3.0 Eric Huang
[not found] ` <57916469.6020901-5C7GfCeVMHo@public.gmane.org>
2016-07-25 2:09 ` Alexandre Demers
2016-07-27 12:55 ` Deucher, Alexander
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2016-07-22 0:17 ` [PATCH 2/3] drm/amd/powerplay: fix issue can't enable vce dpm Eric Huang
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