All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marc Zyngier <marc.zyngier@arm.com>
To: Vijay Kilari <vijay.kilari@gmail.com>
Cc: Vijaya Kumar K <Vijaya.Kumar@cavium.com>,
	kvmarm@lists.cs.columbia.edu,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v4 1/5] arm/arm64: vgic-new: Implement support for userspace access
Date: Mon, 12 Sep 2016 09:51:43 +0100	[thread overview]
Message-ID: <57D66C9F.8070003@arm.com> (raw)
In-Reply-To: <CALicx6sHYqwGdW_zwE9d8BWO2BucQM6gEoLZAtJ6XG0AjAuGGw@mail.gmail.com>

On 12/09/16 09:46, Vijay Kilari wrote:
> On Mon, Sep 12, 2016 at 1:55 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 10/09/16 13:22, vijay.kilari@gmail.com wrote:
>>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>>
>>> +
>>> +void vgic_uaccess_write_pending(struct kvm_vcpu *vcpu,
>>> +                             gpa_t addr, unsigned int len,
>>> +                             unsigned long val)
>>> +{
>>> +     u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>>> +     int i;
>>> +
>>> +     for (i = 0; i < len * 8; i++) {
>>> +             struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>>> +
>>> +             spin_lock(&irq->irq_lock);
>>> +             if (test_bit(i, &val)) {
>>> +                     irq->pending = true;
>>> +                     irq->soft_pending = true;
>>> +                     vgic_queue_irq_unlock(vcpu->kvm, irq);
>>> +             } else {
>>> +                     irq->soft_pending = false;
>>> +                     if (irq->config == VGIC_CONFIG_EDGE ||
>>> +                         (irq->config == VGIC_CONFIG_LEVEL &&
>>> +                         !irq->line_level))
>>> +                             irq->pending = false;
>>> +                     spin_unlock(&irq->irq_lock);
>>> +             }
>>> +
>>> +             vgic_put_irq(vcpu->kvm, irq);
>>> +     }
>>> +}
>>> +
>>
>> These two functions only seems to be called from the GICv3 code. What is
>> the rational for making them globally accessible? Or should they also be
>> wired into the GICv2 code?
> 
> Yes, probably this might be required for V2. But I don't have GICv2 platform
> to implement and verify it. Also not aware if someone is looking at
> migration with GICv2
> platform with this new vgic code.

Migration is already supported, and we can always verify it once you've
made the change.

> 
> Can be kept here for later to wire into GICv2 code.

I don't think so. You are implementing this code, so please wire it into
the potential users.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 1/5] arm/arm64: vgic-new: Implement support for userspace access
Date: Mon, 12 Sep 2016 09:51:43 +0100	[thread overview]
Message-ID: <57D66C9F.8070003@arm.com> (raw)
In-Reply-To: <CALicx6sHYqwGdW_zwE9d8BWO2BucQM6gEoLZAtJ6XG0AjAuGGw@mail.gmail.com>

On 12/09/16 09:46, Vijay Kilari wrote:
> On Mon, Sep 12, 2016 at 1:55 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 10/09/16 13:22, vijay.kilari at gmail.com wrote:
>>> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>>>
>>> +
>>> +void vgic_uaccess_write_pending(struct kvm_vcpu *vcpu,
>>> +                             gpa_t addr, unsigned int len,
>>> +                             unsigned long val)
>>> +{
>>> +     u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
>>> +     int i;
>>> +
>>> +     for (i = 0; i < len * 8; i++) {
>>> +             struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
>>> +
>>> +             spin_lock(&irq->irq_lock);
>>> +             if (test_bit(i, &val)) {
>>> +                     irq->pending = true;
>>> +                     irq->soft_pending = true;
>>> +                     vgic_queue_irq_unlock(vcpu->kvm, irq);
>>> +             } else {
>>> +                     irq->soft_pending = false;
>>> +                     if (irq->config == VGIC_CONFIG_EDGE ||
>>> +                         (irq->config == VGIC_CONFIG_LEVEL &&
>>> +                         !irq->line_level))
>>> +                             irq->pending = false;
>>> +                     spin_unlock(&irq->irq_lock);
>>> +             }
>>> +
>>> +             vgic_put_irq(vcpu->kvm, irq);
>>> +     }
>>> +}
>>> +
>>
>> These two functions only seems to be called from the GICv3 code. What is
>> the rational for making them globally accessible? Or should they also be
>> wired into the GICv2 code?
> 
> Yes, probably this might be required for V2. But I don't have GICv2 platform
> to implement and verify it. Also not aware if someone is looking at
> migration with GICv2
> platform with this new vgic code.

Migration is already supported, and we can always verify it once you've
made the change.

> 
> Can be kept here for later to wire into GICv2 code.

I don't think so. You are implementing this code, so please wire it into
the potential users.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

  reply	other threads:[~2016-09-12  8:43 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-10 12:22 [PATCH v4 0/5] arm/arm64: vgic-new: Implement API for vGICv3 live migration vijay.kilari
2016-09-10 12:22 ` vijay.kilari at gmail.com
2016-09-10 12:22 ` [PATCH v4 1/5] arm/arm64: vgic-new: Implement support for userspace access vijay.kilari
2016-09-10 12:22   ` vijay.kilari at gmail.com
2016-09-12  8:25   ` Marc Zyngier
2016-09-12  8:25     ` Marc Zyngier
2016-09-12  8:46     ` Vijay Kilari
2016-09-12  8:46       ` Vijay Kilari
2016-09-12  8:51       ` Marc Zyngier [this message]
2016-09-12  8:51         ` Marc Zyngier
2016-09-10 12:22 ` [PATCH v4 2/5] arm/arm64: vgic-new: Add distributor and redistributor access vijay.kilari
2016-09-10 12:22   ` vijay.kilari at gmail.com
2016-09-12  8:42   ` Marc Zyngier
2016-09-12  8:42     ` Marc Zyngier
2016-09-10 12:22 ` [PATCH v4 3/5] arm/arm64: vgic-new: Introduce find_reg_by_id() vijay.kilari
2016-09-10 12:22   ` vijay.kilari at gmail.com
2016-09-10 12:22 ` [PATCH v4 4/5] arm/arm64: vgic-new: Implement VGICv3 CPU interface access vijay.kilari
2016-09-10 12:22   ` vijay.kilari at gmail.com
2016-09-11  7:56   ` Marc Zyngier
2016-09-11  7:56     ` Marc Zyngier
2016-09-12  9:00     ` Vijay Kilari
2016-09-12  9:00       ` Vijay Kilari
2016-09-12  9:12       ` Marc Zyngier
2016-09-12  9:12         ` Marc Zyngier
2016-09-10 12:22 ` [PATCH 5/5] arm/arm64: vgic-new: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl vijay.kilari
2016-09-10 12:22   ` vijay.kilari at gmail.com
2016-09-12  8:49   ` Marc Zyngier
2016-09-12  8:49     ` Marc Zyngier
2016-09-12 13:15 ` [PATCH v4 0/5] arm/arm64: vgic-new: Implement API for vGICv3 live migration Marc Zyngier
2016-09-12 13:15   ` Marc Zyngier
2016-09-12 16:44   ` Vijay Kilari
2016-09-12 16:44     ` Vijay Kilari

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=57D66C9F.8070003@arm.com \
    --to=marc.zyngier@arm.com \
    --cc=Vijaya.Kumar@cavium.com \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=vijay.kilari@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.