[PATCH 1/3] drm/amdgpu: refine function name for consistency

[PATCH 1/3] drm/amdgpu: refine function name for consistency

[root]

From: Rex Zhu <Rex.Zhu@amd.com>

Change-Id: I4e5589050bec48a7a6d8bc707bcafbeabf3f5ce1
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 615b8b1..df66abe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -685,7 +685,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
 	return 0;
 }
 
-static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool enable)
+static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
 {
 	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
 
@@ -705,7 +705,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
 	int i;
 
 	if (adev->asic_type == CHIP_POLARIS10)
-		vce_v3_set_bypass_mode(adev, enable);
+		vce_v3_0_set_bypass_mode(adev, enable);
 
 	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
 		return 0;
-- 
1.9.1

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[PATCH 2/3] drm/amd/powerplay: add bypass mode for vce 2.0.

[root]

From: Rex Zhu <Rex.Zhu@amd.com>

fix issue after vce encode, the eclk stay high.

Change-Id: I329d0cbc6342b2d6a7e3968bc211ddc533bf33b5
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index 5fa55b5..ee8a0cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -30,10 +30,10 @@
 #include "amdgpu.h"
 #include "amdgpu_vce.h"
 #include "cikd.h"
-
 #include "vce/vce_2_0_d.h"
 #include "vce/vce_2_0_sh_mask.h"
-
+#include "smu/smu_7_0_1_d.h"
+#include "smu/smu_7_0_1_sh_mask.h"
 #include "oss/oss_2_0_d.h"
 #include "oss/oss_2_0_sh_mask.h"
 
@@ -548,11 +548,28 @@ static int vce_v2_0_process_interrupt(struct amdgpu_device *adev,
 	return 0;
 }
 
+static void vce_v2_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
+{
+	u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
+
+	if (enable)
+		tmp |= GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
+	else
+		tmp &= ~GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK;
+
+	WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
+}
+
+
 static int vce_v2_0_set_clockgating_state(void *handle,
 					  enum amd_clockgating_state state)
 {
 	bool gate = false;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
+
+
+	vce_v2_0_set_bypass_mode(adev, enable);
 
 	if (state == AMD_CG_STATE_GATE)
 		gate = true;
-- 
1.9.1

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[PATCH 3/3] drm/amdgpu: add vce bypass mode for tonga.

[root]

From: Rex Zhu <Rex.Zhu@amd.com>

fix issue that encode test failed on the second time when
vce dpm enabled on tonga.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>

Change-Id: I9c77b631b977ab5cc14dc553b6e6beb502e4bd0e
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index df66abe..168b0db 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -704,7 +704,8 @@ static int vce_v3_0_set_clockgating_state(void *handle,
 	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
 	int i;
 
-	if (adev->asic_type == CHIP_POLARIS10)
+	if ((adev->asic_type == CHIP_POLARIS10) ||
+	    (adev->asic_type == CHIP_TONGA))
 		vce_v3_0_set_bypass_mode(adev, enable);
 
 	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
-- 
1.9.1

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Re: [PATCH 3/3] drm/amdgpu: add vce bypass mode for tonga.

[Andy Furniss]

This regresses vce perf badly on tonga

https://bugs.freedesktop.org/show_bug.cgi?id=97494

Maybe I need a better test case or faster cpu or something,
but vce powerplay encode issues disappeared for me with the latest
firmware.

root wrote:
> From: Rex Zhu <Rex.Zhu@amd.com>
>
> fix issue that encode test failed on the second time when
> vce dpm enabled on tonga.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Change-Id: I9c77b631b977ab5cc14dc553b6e6beb502e4bd0e
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> index df66abe..168b0db 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
> @@ -704,7 +704,8 @@ static int vce_v3_0_set_clockgating_state(void *handle,
>   	bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>   	int i;
>
> -	if (adev->asic_type == CHIP_POLARIS10)
> +	if ((adev->asic_type == CHIP_POLARIS10) ||
> +	    (adev->asic_type == CHIP_TONGA))
>   		vce_v3_0_set_bypass_mode(adev, enable);
>
>   	if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>

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Re: [PATCH 3/3] drm/amdgpu: add vce bypass mode for tonga.

[Andy Furniss]

Andy Furniss wrote:
> This regresses vce perf badly on tonga
>
> https://bugs.freedesktop.org/show_bug.cgi?id=97494
>
> Maybe I need a better test case or faster cpu or something,
> but vce powerplay encode issues disappeared for me with the latest
> firmware.

I did eventually find an issue - but I don't know if it's what the
comment below referred to.

vaapi cbr since the mesa commit that enabled dual instance
can sometimes produce different md5sums, though the vid is visually
OK. Maybe gstreamer timing based as it can be reduced by changing
cpufreq from on_demand to perf or adding ! queue !. Higher bitrates
seem to not have the issue, cqp doesn't seem affected.

>
> root wrote:
>> From: Rex Zhu <Rex.Zhu@amd.com>
>>
>> fix issue that encode test failed on the second time when
>> vce dpm enabled on tonga.
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>>
>> Change-Id: I9c77b631b977ab5cc14dc553b6e6beb502e4bd0e
>> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> index df66abe..168b0db 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
>> @@ -704,7 +704,8 @@ static int vce_v3_0_set_clockgating_state(void
>> *handle,
>>       bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
>>       int i;
>>
>> -    if (adev->asic_type == CHIP_POLARIS10)
>> +    if ((adev->asic_type == CHIP_POLARIS10) ||
>> +        (adev->asic_type == CHIP_TONGA))
>>           vce_v3_0_set_bypass_mode(adev, enable);
>>
>>       if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
>>
>

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