From: Marc Zyngier <marc.zyngier@arm.com>
To: vijay.kilari@gmail.com, christoffer.dall@linaro.org,
peter.maydell@linaro.org
Cc: kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org,
Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Subject: Re: [PATCH v5 4/6] arm/arm64: vgic-new: Introduce VENG0 and VENG1 fields to vmcr struct
Date: Fri, 16 Sep 2016 14:54:48 +0100 [thread overview]
Message-ID: <57DBF9A8.5040604@arm.com> (raw)
In-Reply-To: <1474028453-29132-5-git-send-email-vijay.kilari@gmail.com>
On 16/09/16 13:20, vijay.kilari@gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>
> ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
> and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
> variables to struct vmcr to support read and write of these fields.
>
> ICH_VMCR_CTLR_MASK is changed to mask only ICC_CTLR_EL1 fields.
This comment doesn't match the patch.
> Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 15 +++++++++++----
> virt/kvm/arm/vgic/vgic-mmio-v2.c | 16 ----------------
> virt/kvm/arm/vgic/vgic-mmio.c | 16 ++++++++++++++++
> virt/kvm/arm/vgic/vgic-v3.c | 10 ++++++++--
> virt/kvm/arm/vgic/vgic.h | 5 +++++
> 5 files changed, 40 insertions(+), 22 deletions(-)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 99ac022..88d83d3 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -352,8 +352,9 @@
> /*
> * CPU interface registers
> */
> -#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
> -#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
> +#define ICC_CTLR_EL1_EOImode_SHIFT (1)
> +#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
> +#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
> #define ICC_SRE_EL1_SRE (1U << 0)
>
> /*
> @@ -382,14 +383,20 @@
> #define ICH_HCR_EN (1 << 0)
> #define ICH_HCR_UIE (1 << 1)
>
> -#define ICH_VMCR_CTLR_SHIFT 0
> -#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
> +#define ICH_VMCR_CBPR_SHIFT 4
> +#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
> +#define ICH_VMCR_EOIM_SHIFT 9
> +#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
> #define ICH_VMCR_BPR1_SHIFT 18
> #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
> #define ICH_VMCR_BPR0_SHIFT 21
> #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
> #define ICH_VMCR_PMR_SHIFT 24
> #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
> +#define ICH_VMCR_ENG0_SHIFT 0
> +#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
> +#define ICH_VMCR_ENG1_SHIFT 1
> +#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>
> #define ICC_IAR1_EL1_SPURIOUS 0x3ff
I've asked you to make this a separate patch, which you've ignored.
Please make this change a separate patch, independent of any KVM change.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 4/6] arm/arm64: vgic-new: Introduce VENG0 and VENG1 fields to vmcr struct
Date: Fri, 16 Sep 2016 14:54:48 +0100 [thread overview]
Message-ID: <57DBF9A8.5040604@arm.com> (raw)
In-Reply-To: <1474028453-29132-5-git-send-email-vijay.kilari@gmail.com>
On 16/09/16 13:20, vijay.kilari at gmail.com wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>
> ICC_VMCR_EL2 supports virtual access to ICC_IGRPEN1_EL1.Enable
> and ICC_IGRPEN0_EL1.Enable fields. Add grpen0 and grpen1 member
> variables to struct vmcr to support read and write of these fields.
>
> ICH_VMCR_CTLR_MASK is changed to mask only ICC_CTLR_EL1 fields.
This comment doesn't match the patch.
> Also refactor vgic_set_vmcr and vgic_get_vmcr() code.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> ---
> include/linux/irqchip/arm-gic-v3.h | 15 +++++++++++----
> virt/kvm/arm/vgic/vgic-mmio-v2.c | 16 ----------------
> virt/kvm/arm/vgic/vgic-mmio.c | 16 ++++++++++++++++
> virt/kvm/arm/vgic/vgic-v3.c | 10 ++++++++--
> virt/kvm/arm/vgic/vgic.h | 5 +++++
> 5 files changed, 40 insertions(+), 22 deletions(-)
>
> diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
> index 99ac022..88d83d3 100644
> --- a/include/linux/irqchip/arm-gic-v3.h
> +++ b/include/linux/irqchip/arm-gic-v3.h
> @@ -352,8 +352,9 @@
> /*
> * CPU interface registers
> */
> -#define ICC_CTLR_EL1_EOImode_drop_dir (0U << 1)
> -#define ICC_CTLR_EL1_EOImode_drop (1U << 1)
> +#define ICC_CTLR_EL1_EOImode_SHIFT (1)
> +#define ICC_CTLR_EL1_EOImode_drop_dir (0U << ICC_CTLR_EL1_EOImode_SHIFT)
> +#define ICC_CTLR_EL1_EOImode_drop (1U << ICC_CTLR_EL1_EOImode_SHIFT)
> #define ICC_SRE_EL1_SRE (1U << 0)
>
> /*
> @@ -382,14 +383,20 @@
> #define ICH_HCR_EN (1 << 0)
> #define ICH_HCR_UIE (1 << 1)
>
> -#define ICH_VMCR_CTLR_SHIFT 0
> -#define ICH_VMCR_CTLR_MASK (0x21f << ICH_VMCR_CTLR_SHIFT)
> +#define ICH_VMCR_CBPR_SHIFT 4
> +#define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT)
> +#define ICH_VMCR_EOIM_SHIFT 9
> +#define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT)
> #define ICH_VMCR_BPR1_SHIFT 18
> #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
> #define ICH_VMCR_BPR0_SHIFT 21
> #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
> #define ICH_VMCR_PMR_SHIFT 24
> #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
> +#define ICH_VMCR_ENG0_SHIFT 0
> +#define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT)
> +#define ICH_VMCR_ENG1_SHIFT 1
> +#define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT)
>
> #define ICC_IAR1_EL1_SPURIOUS 0x3ff
I've asked you to make this a separate patch, which you've ignored.
Please make this change a separate patch, independent of any KVM change.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2016-09-16 13:46 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-16 12:20 [PATCH v5 0/6] arm/arm64: vgic-new: Implement API for vGICv3 live migration vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 12:20 ` [PATCH v5 1/6] arm/arm64: vgic-new: Implement support for userspace access vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 16:31 ` Marc Zyngier
2016-09-16 16:31 ` Marc Zyngier
2016-09-16 12:20 ` [PATCH v5 2/6] arm/arm64: vgic-new: Add distributor and redistributor access vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 12:20 ` [PATCH v5 3/6] arm/arm64: vgic-new: Introduce find_reg_by_id() vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 12:20 ` [PATCH v5 4/6] arm/arm64: vgic-new: Introduce VENG0 and VENG1 fields to vmcr struct vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 13:54 ` Marc Zyngier [this message]
2016-09-16 13:54 ` Marc Zyngier
2016-09-16 12:20 ` [PATCH 5/6] arm/arm64: vgic-new: Implement VGICv3 CPU interface access vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
2016-09-16 14:36 ` Marc Zyngier
2016-09-16 14:36 ` Marc Zyngier
2016-09-16 16:57 ` Vijay Kilari
2016-09-16 16:57 ` Vijay Kilari
2016-09-16 17:07 ` Marc Zyngier
2016-09-16 17:07 ` Marc Zyngier
2016-09-17 6:28 ` Vijay Kilari
2016-09-17 6:28 ` Vijay Kilari
2016-09-17 11:37 ` Marc Zyngier
2016-09-17 11:37 ` Marc Zyngier
2016-09-19 7:36 ` Vijay Kilari
2016-09-19 7:36 ` Vijay Kilari
2016-09-19 10:11 ` Peter Maydell
2016-09-19 10:11 ` Peter Maydell
2016-09-18 6:30 ` Vijay Kilari
2016-09-18 6:30 ` Vijay Kilari
2016-09-18 9:27 ` Marc Zyngier
2016-09-18 9:27 ` Marc Zyngier
2016-09-16 12:20 ` [PATCH v5 6/6] arm/arm64: vgic-new: Implement KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO ioctl vijay.kilari
2016-09-16 12:20 ` vijay.kilari at gmail.com
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