* [PATCH 1/8] drm/amdgpu: pad gfx and compute rings to 256 dw
@ 2016-10-05 14:13 Christian König
[not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 22+ messages in thread
From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
From: Christian König <christian.koenig@amd.com>
The same as on windows to avoid further problems with CE/DE
command submission overlaps.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 40abb6b..e3be5bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2896,7 +2896,7 @@ static int gfx_v6_0_sw_init(void *handle)
ring->ring_obj = NULL;
sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024,
- 0x80000000, 0xf,
+ 0x80000000, 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX);
if (r)
@@ -2920,7 +2920,7 @@ static int gfx_v6_0_sw_init(void *handle)
sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
r = amdgpu_ring_init(adev, ring, 1024,
- 0x80000000, 0xf,
+ 0x80000000, 0xff,
&adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2bdcdd0..3ef7cc0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4640,7 +4640,7 @@ static int gfx_v7_0_sw_init(void *handle)
ring->ring_obj = NULL;
sprintf(ring->name, "gfx");
r = amdgpu_ring_init(adev, ring, 1024,
- PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+ PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX);
if (r)
@@ -4667,7 +4667,7 @@ static int gfx_v7_0_sw_init(void *handle)
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
- PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+ PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE);
if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e3db40d..8efd7db 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2062,7 +2062,7 @@ static int gfx_v8_0_sw_init(void *handle)
}
r = amdgpu_ring_init(adev, ring, 1024,
- PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+ PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP,
AMDGPU_RING_TYPE_GFX);
if (r)
@@ -2089,7 +2089,7 @@ static int gfx_v8_0_sw_init(void *handle)
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
/* type-2 packets are deprecated on MEC, use type-3 instead */
r = amdgpu_ring_init(adev, ring, 1024,
- PACKET3(PACKET3_NOP, 0x3FFF), 0xf,
+ PACKET3(PACKET3_NOP, 0x3FFF), 0xff,
&adev->gfx.eop_irq, irq_type,
AMDGPU_RING_TYPE_COMPUTE);
if (r)
--
2.5.0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread[parent not found: <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* [PATCH 2/8] drm/amdgpu: "revert fix exclusive mode game texture blank(v2)" [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-05 14:13 ` Christian König 2016-10-05 14:13 ` [PATCH 3/8] drm/amdgpu: remove ring type check for conditional execution Christian König ` (5 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> This reverts commit e3bb40fcd1a3e889cf2c8972f1925083dd9f96dc and commit 52d7a0c509a48f228d1ec04eaadb2056c201e06e. Shouldn't be necessary any more with the increased padding and we really don't want engine specific code here. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 3e39039..38261a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -129,7 +129,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, unsigned i; int r = 0; - unsigned extra_nop = 0; if (num_ibs == 0) return -EINVAL; @@ -156,11 +155,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, alloc_size = amdgpu_ring_get_dma_frame_size(ring) + num_ibs * amdgpu_ring_get_emit_ib_size(ring); - if (job && !job->vm_needs_flush && ring->type == AMDGPU_RING_TYPE_GFX) { - extra_nop = 128; - alloc_size += extra_nop; - } - r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -171,8 +165,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, patch_offset = amdgpu_ring_init_cond_exec(ring); if (vm) { - amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast than DE */ - r = amdgpu_vm_flush(ring, job); if (r) { amdgpu_ring_undo(ring); -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 3/8] drm/amdgpu: remove ring type check for conditional execution [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2016-10-05 14:13 ` [PATCH 2/8] drm/amdgpu: "revert fix exclusive mode game texture blank(v2)" Christian König @ 2016-10-05 14:13 ` Christian König 2016-10-05 14:13 ` [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush Christian König ` (4 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> If a ring doesn't support that it shouldn't implement the function. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 38261a0..f43368b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -161,7 +161,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return r; } - if (ring->type == AMDGPU_RING_TYPE_GFX && ring->funcs->init_cond_exec) + if (ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring); if (vm) { -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2016-10-05 14:13 ` [PATCH 2/8] drm/amdgpu: "revert fix exclusive mode game texture blank(v2)" Christian König 2016-10-05 14:13 ` [PATCH 3/8] drm/amdgpu: remove ring type check for conditional execution Christian König @ 2016-10-05 14:13 ` Christian König [not found] ` <1475676809-3061-4-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2016-10-05 14:13 ` [PATCH 5/8] drm/amdgpu: remove explicit NULL init for parse_cs Christian König ` (3 subsequent siblings) 6 siblings, 1 reply; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> With the padding raised to 256 DW that shouldn't be needed any more. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 8efd7db..90bb451 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6253,10 +6253,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, { int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); - /* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE finish CEIB */ - if (usepfp) - amdgpu_ring_insert_nop(ring, 128); - amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | WRITE_DATA_DST_SEL(0)) | -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
[parent not found: <1475676809-3061-4-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush [not found] ` <1475676809-3061-4-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-05 15:20 ` Deucher, Alexander 0 siblings, 0 replies; 22+ messages in thread From: Deucher, Alexander @ 2016-10-05 15:20 UTC (permalink / raw) To: 'Christian König', amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Christian König > Sent: Wednesday, October 05, 2016 10:13 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush > > From: Christian König <christian.koenig@amd.com> > > With the padding raised to 256 DW that shouldn't be needed any more. > > Signed-off-by: Christian König <christian.koenig@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 8efd7db..90bb451 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -6253,10 +6253,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct > amdgpu_ring *ring, > { > int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); > > - /* GFX8 emits 128 dw nop to prevent DE do vm_flush before CE > finish CEIB */ > - if (usepfp) > - amdgpu_ring_insert_nop(ring, 128); > - Make sure to adjust the dma frame size as well in this patch. With that fixed, Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Alex > amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | > WRITE_DATA_DST_SEL(0)) | > -- > 2.5.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 5/8] drm/amdgpu: remove explicit NULL init for parse_cs [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> ` (2 preceding siblings ...) 2016-10-05 14:13 ` [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush Christian König @ 2016-10-05 14:13 ` Christian König 2016-10-05 14:13 ` [PATCH 6/8] drm/amdgpu: move IB and frame size directly into the engine description Christian König ` (2 subsequent siblings) 6 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 1 - drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 1 - drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 1 - drivers/gpu/drm/amd/amdgpu/si_dma.c | 1 - drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 1 - 9 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index e6d7bf9..662f493 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1225,7 +1225,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, - .parse_cs = NULL, .emit_ib = cik_sdma_ring_emit_ib, .emit_fence = cik_sdma_ring_emit_fence, .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index e3be5bd..4e35e16 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3258,7 +3258,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, - .parse_cs = NULL, .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, @@ -3277,7 +3276,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_compute, - .parse_cs = NULL, .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 3ef7cc0..d4db26d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -5141,7 +5141,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, - .parse_cs = NULL, .emit_ib = gfx_v7_0_ring_emit_ib_gfx, .emit_fence = gfx_v7_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, @@ -5162,7 +5161,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, - .parse_cs = NULL, .emit_ib = gfx_v7_0_ring_emit_ib_compute, .emit_fence = gfx_v7_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 90bb451..5aca9de 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6572,7 +6572,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, - .parse_cs = NULL, .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, @@ -6594,7 +6593,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, - .parse_cs = NULL, .emit_ib = gfx_v8_0_ring_emit_ib_compute, .emit_fence = gfx_v8_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 1f3dcab..2e3fd35 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -1229,7 +1229,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, - .parse_cs = NULL, .emit_ib = sdma_v2_4_ring_emit_ib, .emit_fence = sdma_v2_4_ring_emit_fence, .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 62e2f4c..d7d5f5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1574,7 +1574,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, - .parse_cs = NULL, .emit_ib = sdma_v3_0_ring_emit_ib, .emit_fence = sdma_v3_0_ring_emit_fence, .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index de35819..9f11e37 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -783,7 +783,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, - .parse_cs = NULL, .emit_ib = si_dma_ring_emit_ib, .emit_fence = si_dma_ring_emit_fence, .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index e0fd9f2..fec5a15 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1070,7 +1070,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, - .parse_cs = NULL, .emit_ib = uvd_v6_0_ring_emit_ib, .emit_fence = uvd_v6_0_ring_emit_fence, .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 3f6db4e..af91421 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -871,7 +871,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, - .parse_cs = NULL, .emit_ib = vce_v3_0_ring_emit_ib, .emit_vm_flush = vce_v3_0_emit_vm_flush, .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 6/8] drm/amdgpu: move IB and frame size directly into the engine description [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> ` (3 preceding siblings ...) 2016-10-05 14:13 ` [PATCH 5/8] drm/amdgpu: remove explicit NULL init for parse_cs Christian König @ 2016-10-05 14:13 ` Christian König 2016-10-05 14:13 ` [PATCH 7/8] drm/amdgpu: move the ring type into the funcs structure Christian König 2016-10-05 14:13 ` [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well Christian König 6 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 12 ------- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 25 ++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 46 +++++++++---------------- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 56 ++++++++++-------------------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 58 ++++++++++---------------------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 25 ++++---------- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 25 ++++---------- drivers/gpu/drm/amd/amdgpu/si_dma.c | 25 ++++---------- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 21 +++--------- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 21 +++--------- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 42 +++++++---------------- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 34 +++++-------------- 16 files changed, 117 insertions(+), 288 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 69ef6d0..4cfd55c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1960,8 +1960,6 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring) #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) -#define amdgpu_ring_get_emit_ib_size(r) (r)->funcs->get_emit_ib_size((r)) -#define amdgpu_ring_get_dma_frame_size(r) (r)->funcs->get_dma_frame_size((r)) #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index f43368b..acf48de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -152,8 +152,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, return -EINVAL; } - alloc_size = amdgpu_ring_get_dma_frame_size(ring) + - num_ibs * amdgpu_ring_get_emit_ib_size(ring); + alloc_size = ring->funcs->emit_frame_size + num_ibs * + ring->funcs->emit_ib_size; r = amdgpu_ring_alloc(ring, alloc_size); if (r) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 2f93588..767843c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -98,6 +98,9 @@ struct amdgpu_ring_funcs { void (*set_wptr)(struct amdgpu_ring *ring); /* validating and patching of IBs */ int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); + /* constants to calculate how many DW are needed for an emit */ + unsigned emit_frame_size; + unsigned emit_ib_size; /* command emit functions */ void (*emit_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib, @@ -127,8 +130,6 @@ struct amdgpu_ring_funcs { void (*end_use)(struct amdgpu_ring *ring); void (*emit_switch_buffer) (struct amdgpu_ring *ring); void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); - unsigned (*get_emit_ib_size) (struct amdgpu_ring *ring); - unsigned (*get_dma_frame_size) (struct amdgpu_ring *ring); }; struct amdgpu_ring { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 9a534e2..2fb469a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -824,18 +824,6 @@ void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, amdgpu_ring_write(ring, VCE_CMD_END); } -unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 4; /* amdgpu_vce_ring_emit_ib */ -} - -unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6; /* amdgpu_vce_ring_emit_fence x1 no user fence */ -} - /** * amdgpu_vce_ring_test_ring - test if VCE ring is working * diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 662f493..bac3c14 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -847,22 +847,6 @@ static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ } -static unsigned cik_sdma_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 4; /* cik_sdma_ring_emit_ib */ -} - -static unsigned cik_sdma_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* cik_sdma_ring_emit_hdp_flush */ - 3 + /* cik_sdma_ring_emit_hdp_invalidate */ - 6 + /* cik_sdma_ring_emit_pipeline_sync */ - 12 + /* cik_sdma_ring_emit_vm_flush */ - 9 + 9 + 9; /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ -} - static void cik_enable_sdma_mgcg(struct amdgpu_device *adev, bool enable) { @@ -1225,6 +1209,13 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, + .emit_frame_size = + 6 + /* cik_sdma_ring_emit_hdp_flush */ + 3 + /* cik_sdma_ring_emit_hdp_invalidate */ + 6 + /* cik_sdma_ring_emit_pipeline_sync */ + 12 + /* cik_sdma_ring_emit_vm_flush */ + 9 + 9 + 9, /* cik_sdma_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 4, /* cik_sdma_ring_emit_ib */ .emit_ib = cik_sdma_ring_emit_ib, .emit_fence = cik_sdma_ring_emit_fence, .emit_pipeline_sync = cik_sdma_ring_emit_pipeline_sync, @@ -1235,8 +1226,6 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .test_ib = cik_sdma_ring_test_ib, .insert_nop = cik_sdma_ring_insert_nop, .pad_ib = cik_sdma_ring_pad_ib, - .get_emit_ib_size = cik_sdma_ring_get_emit_ib_size, - .get_dma_frame_size = cik_sdma_ring_get_dma_frame_size, }; static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 4e35e16..a86b179 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2814,33 +2814,6 @@ static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) amdgpu_ring_write(ring, 0); } -static unsigned gfx_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 6; /* gfx_v6_0_ring_emit_ib */ -} - -static unsigned gfx_v6_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) -{ - return - 5 + /* gfx_v6_0_ring_emit_hdp_flush */ - 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ - 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ - 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ - 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ - 3; /* gfx_v6_ring_emit_cntxcntl */ -} - -static unsigned gfx_v6_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) -{ - return - 5 + /* gfx_v6_0_ring_emit_hdp_flush */ - 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v6_0_ring_emit_vm_flush */ - 14 + 14 + 14; /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ -} - static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter, .select_se_sh = &gfx_v6_0_select_se_sh, @@ -3258,6 +3231,14 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, + .emit_frame_size = + 5 + /* gfx_v6_0_ring_emit_hdp_flush */ + 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */ + 17 + 6 + /* gfx_v6_0_ring_emit_vm_flush */ + 3, /* gfx_v6_ring_emit_cntxcntl */ + .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, @@ -3268,14 +3249,19 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .test_ib = gfx_v6_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_compute, + .emit_frame_size = + 5 + /* gfx_v6_0_ring_emit_hdp_flush */ + 5 + /* gfx_v6_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v6_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v6_0_ring_emit_vm_flush */ + 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */ .emit_ib = gfx_v6_0_ring_emit_ib, .emit_fence = gfx_v6_0_ring_emit_fence, .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync, @@ -3285,8 +3271,6 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { .test_ring = gfx_v6_0_ring_test_ring, .test_ib = gfx_v6_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, - .get_emit_ib_size = gfx_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = gfx_v6_0_ring_get_dma_frame_size_compute, }; static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index d4db26d..99fb839 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4351,41 +4351,6 @@ static void gfx_v7_0_ring_emit_gds_switch(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static unsigned gfx_v7_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v7_0_ring_emit_ib_gfx */ -} - -static unsigned gfx_v7_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v7_0_ring_emit_gds_switch */ - 7 + /* gfx_v7_0_ring_emit_hdp_flush */ - 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ - 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ - 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ - 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ - 3; /* gfx_v7_ring_emit_cntxcntl */ -} - -static unsigned gfx_v7_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v7_0_ring_emit_ib_compute */ -} - -static unsigned gfx_v7_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v7_0_ring_emit_gds_switch */ - 7 + /* gfx_v7_0_ring_emit_hdp_flush */ - 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v7_0_ring_emit_vm_flush */ - 7 + 7 + 7; /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ -} - static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = { .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, .select_se_sh = &gfx_v7_0_select_se_sh, @@ -5141,6 +5106,15 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ + 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 12 + 12 + 12 + /* gfx_v7_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + 4 + /* gfx_v7_0_ring_emit_pipeline_sync */ + 17 + 6 + /* gfx_v7_0_ring_emit_vm_flush */ + 3, /* gfx_v7_ring_emit_cntxcntl */ + .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_gfx */ .emit_ib = gfx_v7_0_ring_emit_ib_gfx, .emit_fence = gfx_v7_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, @@ -5153,14 +5127,20 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, .emit_cntxcntl = gfx_v7_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_gfx, - .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, + .emit_frame_size = + 20 + /* gfx_v7_0_ring_emit_gds_switch */ + 7 + /* gfx_v7_0_ring_emit_hdp_flush */ + 5 + /* gfx_v7_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v7_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v7_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v7_0_ring_emit_fence_compute x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v7_0_ring_emit_ib_compute */ .emit_ib = gfx_v7_0_ring_emit_ib_compute, .emit_fence = gfx_v7_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v7_0_ring_emit_pipeline_sync, @@ -5172,8 +5152,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .test_ib = gfx_v7_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, - .get_emit_ib_size = gfx_v7_0_ring_get_emit_ib_size_compute, - .get_dma_frame_size = gfx_v7_0_ring_get_dma_frame_size_compute, }; static void gfx_v7_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 5aca9de..768a8fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6367,42 +6367,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags) amdgpu_ring_write(ring, 0); } -static unsigned gfx_v8_0_ring_get_emit_ib_size_gfx(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v8_0_ring_emit_ib_gfx */ -} - -static unsigned gfx_v8_0_ring_get_dma_frame_size_gfx(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v8_0_ring_emit_gds_switch */ - 7 + /* gfx_v8_0_ring_emit_hdp_flush */ - 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ - 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */ - 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ - 256 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ - 2 + /* gfx_v8_ring_emit_sb */ - 3; /* gfx_v8_ring_emit_cntxcntl */ -} - -static unsigned gfx_v8_0_ring_get_emit_ib_size_compute(struct amdgpu_ring *ring) -{ - return - 4; /* gfx_v8_0_ring_emit_ib_compute */ -} - -static unsigned gfx_v8_0_ring_get_dma_frame_size_compute(struct amdgpu_ring *ring) -{ - return - 20 + /* gfx_v8_0_ring_emit_gds_switch */ - 7 + /* gfx_v8_0_ring_emit_hdp_flush */ - 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ - 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ - 17 + /* gfx_v8_0_ring_emit_vm_flush */ - 7 + 7 + 7; /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ -} - static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, enum amdgpu_interrupt_state state) { @@ -6572,6 +6536,16 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ + 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 6 + 6 + 6 +/* gfx_v8_0_ring_emit_fence_gfx x3 for user fence, vm fence */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 256 + 19 + /* gfx_v8_0_ring_emit_vm_flush */ + 2 + /* gfx_v8_ring_emit_sb */ + 3, /* gfx_v8_ring_emit_cntxcntl */ + .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */ .emit_ib = gfx_v8_0_ring_emit_ib_gfx, .emit_fence = gfx_v8_0_ring_emit_fence_gfx, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, @@ -6585,14 +6559,20 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .pad_ib = amdgpu_ring_generic_pad_ib, .emit_switch_buffer = gfx_v8_ring_emit_sb, .emit_cntxcntl = gfx_v8_ring_emit_cntxcntl, - .get_emit_ib_size = gfx_v8_0_ring_get_emit_ib_size_gfx, - .get_dma_frame_size = gfx_v8_0_ring_get_dma_frame_size_gfx, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, + .emit_frame_size = + 20 + /* gfx_v8_0_ring_emit_gds_switch */ + 7 + /* gfx_v8_0_ring_emit_hdp_flush */ + 5 + /* gfx_v8_0_ring_emit_hdp_invalidate */ + 7 + /* gfx_v8_0_ring_emit_pipeline_sync */ + 17 + /* gfx_v8_0_ring_emit_vm_flush */ + 7 + 7 + 7, /* gfx_v8_0_ring_emit_fence_compute x3 for user fence, vm fence */ + .emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_compute */ .emit_ib = gfx_v8_0_ring_emit_ib_compute, .emit_fence = gfx_v8_0_ring_emit_fence_compute, .emit_pipeline_sync = gfx_v8_0_ring_emit_pipeline_sync, @@ -6604,8 +6584,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .test_ib = gfx_v8_0_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = amdgpu_ring_generic_pad_ib, - .get_emit_ib_size = gfx_v8_0_ring_get_emit_ib_size_compute, - .get_dma_frame_size = gfx_v8_0_ring_get_dma_frame_size_compute, }; static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 2e3fd35..b797900 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -906,22 +906,6 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static unsigned sdma_v2_4_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 6; /* sdma_v2_4_ring_emit_ib */ -} - -static unsigned sdma_v2_4_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* sdma_v2_4_ring_emit_hdp_flush */ - 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ - 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ - 12 + /* sdma_v2_4_ring_emit_vm_flush */ - 10 + 10 + 10; /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ -} - static int sdma_v2_4_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1229,6 +1213,13 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v2_4_ring_emit_hdp_flush */ + 3 + /* sdma_v2_4_ring_emit_hdp_invalidate */ + 6 + /* sdma_v2_4_ring_emit_pipeline_sync */ + 12 + /* sdma_v2_4_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */ .emit_ib = sdma_v2_4_ring_emit_ib, .emit_fence = sdma_v2_4_ring_emit_fence, .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync, @@ -1239,8 +1230,6 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .test_ib = sdma_v2_4_ring_test_ib, .insert_nop = sdma_v2_4_ring_insert_nop, .pad_ib = sdma_v2_4_ring_pad_ib, - .get_emit_ib_size = sdma_v2_4_ring_get_emit_ib_size, - .get_dma_frame_size = sdma_v2_4_ring_get_dma_frame_size, }; static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index d7d5f5f..891de21 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1108,22 +1108,6 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring, SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ } -static unsigned sdma_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 6; /* sdma_v3_0_ring_emit_ib */ -} - -static unsigned sdma_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 6 + /* sdma_v3_0_ring_emit_hdp_flush */ - 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ - 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ - 12 + /* sdma_v3_0_ring_emit_vm_flush */ - 10 + 10 + 10; /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ -} - static int sdma_v3_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1574,6 +1558,13 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, + .emit_frame_size = + 6 + /* sdma_v3_0_ring_emit_hdp_flush */ + 3 + /* sdma_v3_0_ring_emit_hdp_invalidate */ + 6 + /* sdma_v3_0_ring_emit_pipeline_sync */ + 12 + /* sdma_v3_0_ring_emit_vm_flush */ + 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */ .emit_ib = sdma_v3_0_ring_emit_ib, .emit_fence = sdma_v3_0_ring_emit_fence, .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync, @@ -1584,8 +1575,6 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .test_ib = sdma_v3_0_ring_test_ib, .insert_nop = sdma_v3_0_ring_insert_nop, .pad_ib = sdma_v3_0_ring_pad_ib, - .get_emit_ib_size = sdma_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = sdma_v3_0_ring_get_dma_frame_size, }; static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 9f11e37..c1c1b51 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -495,22 +495,6 @@ static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring, amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */ } -static unsigned si_dma_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 7 + 3; /* si_dma_ring_emit_ib */ -} - -static unsigned si_dma_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 3 + /* si_dma_ring_emit_hdp_flush */ - 3 + /* si_dma_ring_emit_hdp_invalidate */ - 6 + /* si_dma_ring_emit_pipeline_sync */ - 12 + /* si_dma_ring_emit_vm_flush */ - 9 + 9 + 9; /* si_dma_ring_emit_fence x3 for user fence, vm fence */ -} - static int si_dma_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -783,6 +767,13 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, + .emit_frame_size = + 3 + /* si_dma_ring_emit_hdp_flush */ + 3 + /* si_dma_ring_emit_hdp_invalidate */ + 6 + /* si_dma_ring_emit_pipeline_sync */ + 12 + /* si_dma_ring_emit_vm_flush */ + 9 + 9 + 9, /* si_dma_ring_emit_fence x3 for user fence, vm fence */ + .emit_ib_size = 7 + 3, /* si_dma_ring_emit_ib */ .emit_ib = si_dma_ring_emit_ib, .emit_fence = si_dma_ring_emit_fence, .emit_pipeline_sync = si_dma_ring_emit_pipeline_sync, @@ -793,8 +784,6 @@ static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .test_ib = si_dma_ring_test_ib, .insert_nop = amdgpu_ring_insert_nop, .pad_ib = si_dma_ring_pad_ib, - .get_emit_ib_size = si_dma_ring_get_emit_ib_size, - .get_dma_frame_size = si_dma_ring_get_dma_frame_size, }; static void si_dma_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index f6c9415..708de99 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -526,20 +526,6 @@ static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ib->length_dw); } -static unsigned uvd_v4_2_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 4; /* uvd_v4_2_ring_emit_ib */ -} - -static unsigned uvd_v4_2_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v4_2_ring_emit_hdp_flush */ - 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ - 14; /* uvd_v4_2_ring_emit_fence x1 no user fence */ -} - /** * uvd_v4_2_mc_resume - memory controller programming * @@ -760,6 +746,11 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v4_2_ring_emit_hdp_flush */ + 2 + /* uvd_v4_2_ring_emit_hdp_invalidate */ + 14, /* uvd_v4_2_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* uvd_v4_2_ring_emit_ib */ .emit_ib = uvd_v4_2_ring_emit_ib, .emit_fence = uvd_v4_2_ring_emit_fence, .emit_hdp_flush = uvd_v4_2_ring_emit_hdp_flush, @@ -770,8 +761,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v4_2_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v4_2_ring_get_dma_frame_size, }; static void uvd_v4_2_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 400c16f..9e695e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -577,20 +577,6 @@ static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, ib->length_dw); } -static unsigned uvd_v5_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 6; /* uvd_v5_0_ring_emit_ib */ -} - -static unsigned uvd_v5_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v5_0_ring_emit_hdp_flush */ - 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ - 14; /* uvd_v5_0_ring_emit_fence x1 no user fence */ -} - static bool uvd_v5_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -811,6 +797,11 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v5_0_ring_emit_hdp_flush */ + 2 + /* uvd_v5_0_ring_emit_hdp_invalidate */ + 14, /* uvd_v5_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 6, /* uvd_v5_0_ring_emit_ib */ .emit_ib = uvd_v5_0_ring_emit_ib, .emit_fence = uvd_v5_0_ring_emit_fence, .emit_hdp_flush = uvd_v5_0_ring_emit_hdp_flush, @@ -821,8 +812,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v5_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v5_0_ring_get_dma_frame_size, }; static void uvd_v5_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index fec5a15..e6abd86 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -725,31 +725,6 @@ static void uvd_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0xE); } -static unsigned uvd_v6_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 8; /* uvd_v6_0_ring_emit_ib */ -} - -static unsigned uvd_v6_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v6_0_ring_emit_hdp_flush */ - 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ - 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ - 14; /* uvd_v6_0_ring_emit_fence x1 no user fence */ -} - -static unsigned uvd_v6_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) -{ - return - 2 + /* uvd_v6_0_ring_emit_hdp_flush */ - 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ - 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ - 20 + /* uvd_v6_0_ring_emit_vm_flush */ - 14 + 14; /* uvd_v6_0_ring_emit_fence x2 vm fence */ -} - static bool uvd_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1052,6 +1027,12 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, .parse_cs = amdgpu_uvd_ring_parse_cs, + .emit_frame_size = + 2 + /* uvd_v6_0_ring_emit_hdp_flush */ + 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 14, /* uvd_v6_0_ring_emit_fence x1 no user fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ .emit_ib = uvd_v6_0_ring_emit_ib, .emit_fence = uvd_v6_0_ring_emit_fence, .emit_hdp_flush = uvd_v6_0_ring_emit_hdp_flush, @@ -1062,14 +1043,19 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size, }; static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, + .emit_frame_size = + 2 + /* uvd_v6_0_ring_emit_hdp_flush */ + 2 + /* uvd_v6_0_ring_emit_hdp_invalidate */ + 10 + /* uvd_v6_0_ring_emit_pipeline_sync */ + 20 + /* uvd_v6_0_ring_emit_vm_flush */ + 14 + 14, /* uvd_v6_0_ring_emit_fence x2 vm fence */ + .emit_ib_size = 8, /* uvd_v6_0_ring_emit_ib */ .emit_ib = uvd_v6_0_ring_emit_ib, .emit_fence = uvd_v6_0_ring_emit_fence, .emit_vm_flush = uvd_v6_0_ring_emit_vm_flush, @@ -1082,8 +1068,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_uvd_ring_begin_use, .end_use = amdgpu_uvd_ring_end_use, - .get_emit_ib_size = uvd_v6_0_ring_get_emit_ib_size, - .get_dma_frame_size = uvd_v6_0_ring_get_dma_frame_size_vm, }; static void uvd_v6_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 76e64ad..7ada30d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -614,6 +614,8 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .get_wptr = vce_v2_0_ring_get_wptr, .set_wptr = vce_v2_0_ring_set_wptr, .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_frame_size = 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ + .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ .emit_ib = amdgpu_vce_ring_emit_ib, .emit_fence = amdgpu_vce_ring_emit_fence, .test_ring = amdgpu_vce_ring_test_ring, @@ -622,8 +624,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = amdgpu_vce_ring_get_emit_ib_size, - .get_dma_frame_size = amdgpu_vce_ring_get_dma_frame_size, }; static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index af91421..6303f2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -809,27 +809,6 @@ static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, seq); } -static unsigned vce_v3_0_ring_get_emit_ib_size(struct amdgpu_ring *ring) -{ - return - 5; /* vce_v3_0_ring_emit_ib */ -} - -static unsigned vce_v3_0_ring_get_dma_frame_size(struct amdgpu_ring *ring) -{ - return - 4 + /* vce_v3_0_emit_pipeline_sync */ - 6; /* amdgpu_vce_ring_emit_fence x1 no user fence */ -} - -static unsigned vce_v3_0_ring_get_dma_frame_size_vm(struct amdgpu_ring *ring) -{ - return - 6 + /* vce_v3_0_emit_vm_flush */ - 4 + /* vce_v3_0_emit_pipeline_sync */ - 6 + 6; /* amdgpu_vce_ring_emit_fence x2 vm fence */ -} - const struct amd_ip_funcs vce_v3_0_ip_funcs = { .name = "vce_v3_0", .early_init = vce_v3_0_early_init, @@ -855,6 +834,10 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, .parse_cs = amdgpu_vce_ring_parse_cs, + .emit_frame_size = + 4 + /* vce_v3_0_emit_pipeline_sync */ + 6, /* amdgpu_vce_ring_emit_fence x1 no user fence */ + .emit_ib_size = 5, /* vce_v3_0_ring_emit_ib */ .emit_ib = amdgpu_vce_ring_emit_ib, .emit_fence = amdgpu_vce_ring_emit_fence, .test_ring = amdgpu_vce_ring_test_ring, @@ -863,14 +846,17 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size, }; static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, + .emit_frame_size = + 6 + /* vce_v3_0_emit_vm_flush */ + 4 + /* vce_v3_0_emit_pipeline_sync */ + 6 + 6, /* amdgpu_vce_ring_emit_fence x2 vm fence */ + .emit_ib_size = 4, /* amdgpu_vce_ring_emit_ib */ .emit_ib = vce_v3_0_ring_emit_ib, .emit_vm_flush = vce_v3_0_emit_vm_flush, .emit_pipeline_sync = vce_v3_0_emit_pipeline_sync, @@ -881,8 +867,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .pad_ib = amdgpu_ring_generic_pad_ib, .begin_use = amdgpu_vce_ring_begin_use, .end_use = amdgpu_vce_ring_end_use, - .get_emit_ib_size = vce_v3_0_ring_get_emit_ib_size, - .get_dma_frame_size = vce_v3_0_ring_get_dma_frame_size_vm, }; static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev) -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 7/8] drm/amdgpu: move the ring type into the funcs structure [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> ` (4 preceding siblings ...) 2016-10-05 14:13 ` [PATCH 6/8] drm/amdgpu: move IB and frame size directly into the engine description Christian König @ 2016-10-05 14:13 ` Christian König 2016-10-05 14:13 ` [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well Christian König 6 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> It's constant, so it doesn't make to much sense to keep it with the variable data. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 4 +--- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 16 ++++++++-------- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++++++------- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 3 ++- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 3 ++- 16 files changed, 50 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index a13e551..04b7aaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -942,8 +942,8 @@ static int amdgpu_cs_ib_fill(struct amdgpu_device *adev, /* UVD & VCE fw doesn't support user fences */ if (parser->job->uf_addr && ( - parser->job->ring->type == AMDGPU_RING_TYPE_UVD || - parser->job->ring->type == AMDGPU_RING_TYPE_VCE)) + parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD || + parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE)) return -EINVAL; return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index e1fa873..b2df735 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -164,8 +164,7 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) */ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned max_dw, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type, - enum amdgpu_ring_type ring_type) + struct amdgpu_irq_src *irq_src, unsigned irq_type) { int r; @@ -218,7 +217,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, amdgpu_sched_hw_submission); ring->align_mask = align_mask; ring->nop = nop; - ring->type = ring_type; /* Allocate ring buffer */ if (ring->ring_obj == NULL) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 767843c..6cf89c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -92,6 +92,8 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); /* provided by hw blocks that expose a ring buffer for commands */ struct amdgpu_ring_funcs { + enum amdgpu_ring_type type; + /* ring read/write ptr handling */ u32 (*get_rptr)(struct amdgpu_ring *ring); u32 (*get_wptr)(struct amdgpu_ring *ring); @@ -161,7 +163,6 @@ struct amdgpu_ring { unsigned wptr_offs; unsigned fence_offs; uint64_t current_ctx; - enum amdgpu_ring_type type; char name[16]; unsigned cond_exe_offs; u64 cond_exe_gpu_addr; @@ -178,8 +179,7 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, unsigned ring_size, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type, - enum amdgpu_ring_type ring_type); + struct amdgpu_irq_src *irq_src, unsigned irq_type); void amdgpu_ring_fini(struct amdgpu_ring *ring); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index b8620d3..da66823 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -348,7 +348,7 @@ static bool amdgpu_vm_ring_has_compute_vm_bug(struct amdgpu_ring *ring) struct amdgpu_device *adev = ring->adev; const struct amdgpu_ip_block_version *ip_block; - if (ring->type != AMDGPU_RING_TYPE_COMPUTE) + if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE) /* only compute rings */ return false; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index bac3c14..f91f02f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -945,8 +945,8 @@ static int cik_sdma_sw_init(void *handle) SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1206,6 +1206,7 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { }; static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index a86b179..1f8687fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -1940,7 +1940,7 @@ static int gfx_v6_0_cp_resume(struct amdgpu_device *adev) static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -1966,7 +1966,7 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); /* write new base address */ amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); @@ -2870,8 +2870,7 @@ static int gfx_v6_0_sw_init(void *handle) sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, 0x80000000, 0xff, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -2894,8 +2893,7 @@ static int gfx_v6_0_sw_init(void *handle) irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; r = amdgpu_ring_init(adev, ring, 1024, 0x80000000, 0xff, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + &adev->gfx.eop_irq, irq_type); if (r) return r; } @@ -3228,6 +3226,7 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3251,7 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { }; static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 99fb839..be3881e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2077,9 +2077,9 @@ static int gfx_v7_0_ring_test_ring(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask; - int usepfp = ring->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; + int usepfp = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE ? 0 : 1; - if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { case 1: ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; @@ -3216,7 +3216,7 @@ static int gfx_v7_0_cp_resume(struct amdgpu_device *adev) */ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -3256,7 +3256,7 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -4606,8 +4606,7 @@ static int gfx_v7_0_sw_init(void *handle) sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -4633,8 +4632,7 @@ static int gfx_v7_0_sw_init(void *handle) /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + &adev->gfx.eop_irq, irq_type); if (r) return r; } @@ -5103,6 +5101,7 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5129,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 768a8fd..0d66f49 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2063,8 +2063,7 @@ static int gfx_v8_0_sw_init(void *handle) r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP, - AMDGPU_RING_TYPE_GFX); + &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -2090,8 +2089,7 @@ static int gfx_v8_0_sw_init(void *handle) /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, irq_type, - AMDGPU_RING_TYPE_COMPUTE); + &adev->gfx.eop_irq, irq_type); if (r) return r; } @@ -6131,7 +6129,7 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct amdgpu_ring *ring) { u32 ref_and_mask, reg_mem_engine; - if (ring->type == AMDGPU_RING_TYPE_COMPUTE) { + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) { switch (ring->me) { case 1: ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; @@ -6233,7 +6231,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); uint32_t seq = ring->fence_drv.sync_seq; uint64_t addr = ring->fence_drv.gpu_addr; @@ -6251,7 +6249,7 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vm_id, uint64_t pd_addr) { - int usepfp = (ring->type == AMDGPU_RING_TYPE_GFX); + int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX); amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | @@ -6533,6 +6531,7 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { + .type = AMDGPU_RING_TYPE_GFX, .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6561,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { + .type = AMDGPU_RING_TYPE_COMPUTE, .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index b797900..b11a81e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -956,8 +956,8 @@ static int sdma_v2_4_sw_init(void *handle) SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1210,6 +1210,7 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { }; static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 891de21..accf4d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1168,8 +1168,8 @@ static int sdma_v3_0_sw_init(void *handle) SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -1555,6 +1555,7 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { }; static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index c1c1b51..1aee45b 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -534,8 +534,8 @@ static int si_dma_sw_init(void *handle) DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? - AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1, - AMDGPU_RING_TYPE_SDMA); + AMDGPU_SDMA_IRQ_TRAP0 : + AMDGPU_SDMA_IRQ_TRAP1); if (r) return r; } @@ -764,6 +764,7 @@ const struct amd_ip_funcs si_dma_ip_funcs = { }; static const struct amdgpu_ring_funcs si_dma_ring_funcs = { + .type = AMDGPU_RING_TYPE_SDMA, .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 708de99..55af8ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -117,7 +117,7 @@ static int uvd_v4_2_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + &adev->uvd.irq, 0); return r; } @@ -742,6 +742,7 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { }; static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { + .type = AMDGPU_RING_TYPE_UVD, .get_rptr = uvd_v4_2_ring_get_rptr, .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 9e695e0..21e725b 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -113,7 +113,7 @@ static int uvd_v5_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + &adev->uvd.irq, 0); return r; } @@ -793,6 +793,7 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { }; static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_UVD, .get_rptr = uvd_v5_0_ring_get_rptr, .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index e6abd86..2ce1818 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -117,7 +117,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0, AMDGPU_RING_TYPE_UVD); + &adev->uvd.irq, 0); return r; } @@ -1046,6 +1046,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { }; static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_UVD, .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 7ada30d..cf0c68f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -225,7 +225,7 @@ static int vce_v2_0_sw_init(void *handle) ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, - &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + &adev->vce.irq, 0); if (r) return r; } @@ -610,6 +610,7 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { }; static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { + .type = AMDGPU_RING_TYPE_VCE, .get_rptr = vce_v2_0_ring_get_rptr, .get_wptr = vce_v2_0_ring_get_wptr, .set_wptr = vce_v2_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 6303f2b..56a3feb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -390,7 +390,7 @@ static int vce_v3_0_sw_init(void *handle) ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, - &adev->vce.irq, 0, AMDGPU_RING_TYPE_VCE); + &adev->vce.irq, 0); if (r) return r; } @@ -849,6 +849,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { }; static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { + .type = AMDGPU_RING_TYPE_VCE, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> ` (5 preceding siblings ...) 2016-10-05 14:13 ` [PATCH 7/8] drm/amdgpu: move the ring type into the funcs structure Christian König @ 2016-10-05 14:13 ` Christian König [not found] ` <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 6 siblings, 1 reply; 22+ messages in thread From: Christian König @ 2016-10-05 14:13 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW From: Christian König <christian.koenig@amd.com> They are constant as well. Signed-off-by: Christian König <christian.koenig@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- 14 files changed, 58 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index b2df735..a141b46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw) { /* Align requested size with padding so unlock_commit can * pad safely */ - ndw = (ndw + ring->align_mask) & ~ring->align_mask; + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; /* Make sure we aren't trying to allocate more space * than the maximum for one submission @@ -94,7 +94,7 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) int i; for (i = 0; i < count; i++) - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ -106,8 +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) */ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib) { - while (ib->length_dw & ring->align_mask) - ib->ptr[ib->length_dw++] = ring->nop; + while (ib->length_dw & ring->funcs->align_mask) + ib->ptr[ib->length_dw++] = ring->funcs->nop; } /** @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) uint32_t count; /* We pad to match fetch size */ - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); - count %= ring->align_mask + 1; + count = ring->funcs->align_mask + 1 - + (ring->wptr & ring->funcs->align_mask); + count %= ring->funcs->align_mask + 1; ring->funcs->insert_nop(ring, count); mb(); @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) * Returns 0 on success, error on failure. */ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned max_dw, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type) + unsigned max_dw, struct amdgpu_irq_src *irq_src, + unsigned irq_type) { int r; @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, ring->ring_size = roundup_pow_of_two(max_dw * 4 * amdgpu_sched_hw_submission); - ring->align_mask = align_mask; - ring->nop = nop; /* Allocate ring buffer */ if (ring->ring_obj == NULL) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 6cf89c9..1ee1b65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); /* provided by hw blocks that expose a ring buffer for commands */ struct amdgpu_ring_funcs { enum amdgpu_ring_type type; + uint32_t align_mask; + u32 nop; /* ring read/write ptr handling */ u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ struct amdgpu_ring { unsigned max_dw; int count_dw; uint64_t gpu_addr; - uint32_t align_mask; uint32_t ptr_mask; bool ready; - u32 nop; u32 idx; u32 me; u32 pipe; @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); void amdgpu_ring_commit(struct amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned ring_size, u32 nop, u32 align_mask, - struct amdgpu_irq_src *irq_src, unsigned irq_type); + unsigned ring_size, struct amdgpu_irq_src *irq_src, + unsigned irq_type); void amdgpu_ring_fini(struct amdgpu_ring *ring); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index f91f02f..664f894 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_NOP_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), .get_rptr = cik_sdma_ring_get_rptr, .get_wptr = cik_sdma_ring_get_wptr, .set_wptr = cik_sdma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 1f8687fd..367b14e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, - 0x80000000, 0xff, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; r = amdgpu_ring_init(adev, ring, 1024, - 0x80000000, 0xff, &adev->gfx.eop_irq, irq_type); if (r) return r; @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = 0x80000000, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = 0x80000000, .get_rptr = gfx_v6_0_ring_get_rptr, .get_wptr = gfx_v6_0_ring_get_wptr, .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index be3881e..15f24bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) ring->ring_obj = NULL; sprintf(ring->name, "gfx"); r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, &adev->gfx.eop_irq, irq_type); if (r) return r; @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_gfx, .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v7_0_ring_get_rptr, .get_wptr = gfx_v7_0_ring_get_wptr_compute, .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 0d66f49..51f1139 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0; } - r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP); + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, + AMDGPU_CP_IRQ_GFX_EOP); if (r) return r; } @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue); irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe; /* type-2 packets are deprecated on MEC, use type-3 instead */ - r = amdgpu_ring_init(adev, ring, 1024, - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, - &adev->gfx.eop_irq, irq_type); + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, + irq_type); if (r) return r; } @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .type = AMDGPU_RING_TYPE_GFX, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_gfx, .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { .type = AMDGPU_RING_TYPE_COMPUTE, + .align_mask = 0xff, + .nop = PACKET3(PACKET3_NOP, 0x3FFF), .get_rptr = gfx_v8_0_ring_get_rptr, .get_wptr = gfx_v8_0_ring_get_wptr_compute, .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index b11a81e..49c47d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) ring->use_doorbell = false; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), .get_rptr = sdma_v2_4_ring_get_rptr, .get_wptr = sdma_v2_4_ring_get_wptr, .set_wptr = sdma_v2_4_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index accf4d1..f8ec370 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) for (i = 0; i < count; i++) if (sdma && sdma->burst_nop && (i == 0)) - amdgpu_ring_write(ring, ring->nop | + amdgpu_ring_write(ring, ring->funcs->nop | SDMA_PKT_NOP_HEADER_COUNT(count - 1)); else - amdgpu_ring_write(ring, ring->nop); + amdgpu_ring_write(ring, ring->funcs->nop); } /** @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), .get_rptr = sdma_v3_0_ring_get_rptr, .get_wptr = sdma_v3_0_ring_get_wptr, .set_wptr = sdma_v3_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 1aee45b..7fece1f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) ring->use_doorbell = false; sprintf(ring->name, "sdma%d", i); r = amdgpu_ring_init(adev, ring, 1024, - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), 0xf, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { static const struct amdgpu_ring_funcs si_dma_ring_funcs = { .type = AMDGPU_RING_TYPE_SDMA, + .align_mask = 0xf, + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), .get_rptr = si_dma_ring_get_rptr, .get_wptr = si_dma_ring_get_wptr, .set_wptr = si_dma_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 55af8ac..1bab75a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v4_2_ring_get_rptr, .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 21e725b..ec848fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v5_0_ring_get_rptr, .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 2ce1818..15708f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) ring = &adev->uvd.ring; sprintf(ring->name, "uvd"); - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), 0xf, - &adev->uvd.irq, 0); + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); return r; } @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_UVD, + .align_mask = 0xf, + .nop = PACKET0(mmUVD_NO_OP, 0), .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index cf0c68f..d585839 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) for (i = 0; i < adev->vce.num_rings; i++) { ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); if (r) return r; @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, .get_rptr = vce_v2_0_ring_get_rptr, .get_wptr = vce_v2_0_ring_get_wptr, .set_wptr = vce_v2_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 56a3feb..f7dbd0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) for (i = 0; i < adev->vce.num_rings; i++) { ring = &adev->vce.ring[i]; sprintf(ring->name, "vce%d", i); - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, - &adev->vce.irq, 0); + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); if (r) return r; } @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = { static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCE, + .align_mask = 0xf, + .nop = VCE_CMD_NO_OP, .get_rptr = vce_v3_0_ring_get_rptr, .get_wptr = vce_v3_0_ring_get_wptr, .set_wptr = vce_v3_0_ring_set_wptr, -- 2.5.0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 22+ messages in thread
[parent not found: <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-05 15:24 ` Deucher, Alexander 2016-10-11 13:13 ` Andy Furniss 2016-10-26 7:34 ` Yu, Xiangliang 2 siblings, 0 replies; 22+ messages in thread From: Deucher, Alexander @ 2016-10-05 15:24 UTC (permalink / raw) To: 'Christian König', amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Christian König > Sent: Wednesday, October 05, 2016 10:13 AM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs > as well > > From: Christian König <christian.koenig@amd.com> > > They are constant as well. > > Signed-off-by: Christian König <christian.koenig@amd.com> Patches 1-3, 5-8 are: Reviewed-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++---------- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > 14 files changed, 58 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index b2df735..a141b46 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, > unsigned ndw) > { > /* Align requested size with padding so unlock_commit can > * pad safely */ > - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; > > /* Make sure we aren't trying to allocate more space > * than the maximum for one submission > @@ -94,7 +94,7 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring > *ring, uint32_t count) > int i; > > for (i = 0; i < count; i++) > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets > @@ -106,8 +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring > *ring, uint32_t count) > */ > void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct > amdgpu_ib *ib) > { > - while (ib->length_dw & ring->align_mask) > - ib->ptr[ib->length_dw++] = ring->nop; > + while (ib->length_dw & ring->funcs->align_mask) > + ib->ptr[ib->length_dw++] = ring->funcs->nop; > } > > /** > @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) > uint32_t count; > > /* We pad to match fetch size */ > - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > - count %= ring->align_mask + 1; > + count = ring->funcs->align_mask + 1 - > + (ring->wptr & ring->funcs->align_mask); > + count %= ring->funcs->align_mask + 1; > ring->funcs->insert_nop(ring, count); > > mb(); > @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) > * Returns 0 on success, error on failure. > */ > int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > *ring, > - unsigned max_dw, u32 nop, u32 align_mask, > - struct amdgpu_irq_src *irq_src, unsigned irq_type) > + unsigned max_dw, struct amdgpu_irq_src *irq_src, > + unsigned irq_type) > { > int r; > > @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, > struct amdgpu_ring *ring, > > ring->ring_size = roundup_pow_of_two(max_dw * 4 * > amdgpu_sched_hw_submission); > - ring->align_mask = align_mask; > - ring->nop = nop; > > /* Allocate ring buffer */ > if (ring->ring_obj == NULL) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 6cf89c9..1ee1b65 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct > amdgpu_ring *ring); > /* provided by hw blocks that expose a ring buffer for commands */ > struct amdgpu_ring_funcs { > enum amdgpu_ring_type type; > + uint32_t align_mask; > + u32 nop; > > /* ring read/write ptr handling */ > u32 (*get_rptr)(struct amdgpu_ring *ring); > @@ -149,10 +151,8 @@ struct amdgpu_ring { > unsigned max_dw; > int count_dw; > uint64_t gpu_addr; > - uint32_t align_mask; > uint32_t ptr_mask; > bool ready; > - u32 nop; > u32 idx; > u32 me; > u32 pipe; > @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > amdgpu_ring *ring, struct amdgpu_ib *ib); > void amdgpu_ring_commit(struct amdgpu_ring *ring); > void amdgpu_ring_undo(struct amdgpu_ring *ring); > int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > *ring, > - unsigned ring_size, u32 nop, u32 align_mask, > - struct amdgpu_irq_src *irq_src, unsigned irq_type); > + unsigned ring_size, struct amdgpu_irq_src *irq_src, > + unsigned irq_type); > void amdgpu_ring_fini(struct amdgpu_ring *ring); > > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > index f91f02f..664f894 100644 > --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_NOP_COUNT(count - 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > 0), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { > > static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > .get_rptr = cik_sdma_ring_get_rptr, > .get_wptr = cik_sdma_ring_get_wptr, > .set_wptr = cik_sdma_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index 1f8687fd..367b14e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "gfx"); > r = amdgpu_ring_init(adev, ring, 1024, > - 0x80000000, 0xff, > &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) > sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, > ring->queue); > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > r = amdgpu_ring_init(adev, ring, 1024, > - 0x80000000, 0xff, > &adev->gfx.eop_irq, irq_type); > if (r) > return r; > @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = 0x80000000, > .get_rptr = gfx_v6_0_ring_get_rptr, > .get_wptr = gfx_v6_0_ring_get_wptr, > .set_wptr = gfx_v6_0_ring_set_wptr_gfx, > @@ -3252,6 +3252,8 @@ static const struct amdgpu_ring_funcs > gfx_v6_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = 0x80000000, > .get_rptr = gfx_v6_0_ring_get_rptr, > .get_wptr = gfx_v6_0_ring_get_wptr, > .set_wptr = gfx_v6_0_ring_set_wptr_compute, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index be3881e..15f24bd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "gfx"); > r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > /* type-2 packets are deprecated on MEC, use type-3 instead > */ > r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > &adev->gfx.eop_irq, irq_type); > if (r) > return r; > @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v7_0_ring_get_rptr, > .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > .set_wptr = gfx_v7_0_ring_set_wptr_gfx, > @@ -5130,6 +5130,8 @@ static const struct amdgpu_ring_funcs > gfx_v7_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v7_0_ring_get_rptr, > .get_wptr = gfx_v7_0_ring_get_wptr_compute, > .set_wptr = gfx_v7_0_ring_set_wptr_compute, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 0d66f49..51f1139 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > ring->doorbell_index = > AMDGPU_DOORBELL_GFX_RING0; > } > > - r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > - &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > + AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > } > @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- > >pipe, ring->queue); > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > /* type-2 packets are deprecated on MEC, use type-3 instead > */ > - r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > - &adev->gfx.eop_irq, irq_type); > + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > + irq_type); > if (r) > return r; > } > @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v8_0_ring_get_rptr, > .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > .set_wptr = gfx_v8_0_ring_set_wptr_gfx, > @@ -6562,6 +6562,8 @@ static const struct amdgpu_ring_funcs > gfx_v8_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v8_0_ring_get_rptr, > .get_wptr = gfx_v8_0_ring_get_wptr_compute, > .set_wptr = gfx_v8_0_ring_set_wptr_compute, > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > index b11a81e..49c47d6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > ring->use_doorbell = false; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - > SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { > > static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .get_rptr = sdma_v2_4_ring_get_rptr, > .get_wptr = sdma_v2_4_ring_get_wptr, > .set_wptr = sdma_v2_4_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index accf4d1..f8ec370 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) > > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - > SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { > > static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .get_rptr = sdma_v3_0_ring_get_rptr, > .get_wptr = sdma_v3_0_ring_get_wptr, > .set_wptr = sdma_v3_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c > b/drivers/gpu/drm/amd/amdgpu/si_dma.c > index 1aee45b..7fece1f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > ring->use_doorbell = false; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > 0), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { > > static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > .get_rptr = si_dma_ring_get_rptr, > .get_wptr = si_dma_ring_get_wptr, > .set_wptr = si_dma_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > index 55af8ac..1bab75a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { > > static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v4_2_ring_get_rptr, > .get_wptr = uvd_v4_2_ring_get_wptr, > .set_wptr = uvd_v4_2_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 21e725b..ec848fc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > > static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v5_0_ring_get_rptr, > .get_wptr = uvd_v5_0_ring_get_wptr, > .set_wptr = uvd_v5_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 2ce1818..15708f8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_ring_phys_funcs = { > > static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > index cf0c68f..d585839 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > for (i = 0; i < adev->vce.num_rings; i++) { > ring = &adev->vce.ring[i]; > sprintf(ring->name, "vce%d", i); > - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > + r = amdgpu_ring_init(adev, ring, 512, > &adev->vce.irq, 0); > if (r) > return r; > @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { > > static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_VCE, > + .align_mask = 0xf, > + .nop = VCE_CMD_NO_OP, > .get_rptr = vce_v2_0_ring_get_rptr, > .get_wptr = vce_v2_0_ring_get_wptr, > .set_wptr = vce_v2_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 56a3feb..f7dbd0d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > for (i = 0; i < adev->vce.num_rings; i++) { > ring = &adev->vce.ring[i]; > sprintf(ring->name, "vce%d", i); > - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > - &adev->vce.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); > if (r) > return r; > } > @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > vce_v3_0_ring_phys_funcs = { > > static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCE, > + .align_mask = 0xf, > + .nop = VCE_CMD_NO_OP, > .get_rptr = vce_v3_0_ring_get_rptr, > .get_wptr = vce_v3_0_ring_get_wptr, > .set_wptr = vce_v3_0_ring_set_wptr, > -- > 2.5.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2016-10-05 15:24 ` Deucher, Alexander @ 2016-10-11 13:13 ` Andy Furniss [not found] ` <57FCE58E.5040107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2016-10-26 7:34 ` Yu, Xiangliang 2 siblings, 1 reply; 22+ messages in thread From: Andy Furniss @ 2016-10-11 13:13 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Christian König wrote: > From: Christian König <christian.koenig@amd.com> > > They are constant as well. I die on driver load with this commit on R9285 testing on 4.9-wip. _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <57FCE58E.5040107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <57FCE58E.5040107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2016-10-11 13:26 ` Christian König [not found] ` <82e102e9-cd1b-10ce-75ca-201ef4b802d4-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Christian König @ 2016-10-11 13:26 UTC (permalink / raw) To: Andy Furniss, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 11.10.2016 um 15:13 schrieb Andy Furniss: > Christian König wrote: >> From: Christian König <christian.koenig@amd.com> >> >> They are constant as well. > > I die on driver load with this commit on R9285 testing on 4.9-wip. > > Probably just a typo in the hardware handling. Going to switch to my Tonga in a minute, but I only got about half an hour left before I need to get my daughter from kindergarten. Christian. _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <82e102e9-cd1b-10ce-75ca-201ef4b802d4-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <82e102e9-cd1b-10ce-75ca-201ef4b802d4-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-11 13:28 ` StDenis, Tom [not found] ` <CY4PR12MB1768C74FCED56F7663ABCE5BF7DA0-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: StDenis, Tom @ 2016-10-11 13:28 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org [-- Attachment #1.1: Type: text/plain, Size: 1399 bytes --] It dies on my Tonga just FYI (save you some trouble). Tom ________________________________ From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> Sent: Tuesday, October 11, 2016 09:26 To: Andy Furniss; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Subject: Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well Am 11.10.2016 um 15:13 schrieb Andy Furniss: > Christian König wrote: >> From: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org> >> >> They are constant as well. > > I die on driver load with this commit on R9285 testing on 4.9-wip. > > Probably just a typo in the hardware handling. Going to switch to my Tonga in a minute, but I only got about half an hour left before I need to get my daughter from kindergarten. Christian. _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx amd-gfx Info Page - lists.freedesktop.org<https://lists.freedesktop.org/mailman/listinfo/amd-gfx> lists.freedesktop.org To see the collection of prior postings to the list, visit the amd-gfx Archives. Using amd-gfx: To post a message to all the list members, send email ... [-- Attachment #1.2: Type: text/html, Size: 4177 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CY4PR12MB1768C74FCED56F7663ABCE5BF7DA0-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CY4PR12MB1768C74FCED56F7663ABCE5BF7DA0-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-10-11 17:34 ` Christian König 0 siblings, 0 replies; 22+ messages in thread From: Christian König @ 2016-10-11 17:34 UTC (permalink / raw) To: StDenis, Tom, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org [-- Attachment #1.1: Type: text/plain, Size: 1924 bytes --] Turned out I just missed adding the three lines to the physical mode for VCE on Tonga as well. Please test and review the patch I've just send to the mailing list. Regards, Christian. Am 11.10.2016 um 15:28 schrieb StDenis, Tom: > > It dies on my Tonga just FYI (save you some trouble). > > > Tom > > > > ------------------------------------------------------------------------ > *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of > Christian König <deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> > *Sent:* Tuesday, October 11, 2016 09:26 > *To:* Andy Furniss; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > *Subject:* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into > ring funcs as well > Am 11.10.2016 um 15:13 schrieb Andy Furniss: > > Christian König wrote: > >> From: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org> > >> > >> They are constant as well. > > > > I die on driver load with this commit on R9285 testing on 4.9-wip. > > > > > Probably just a typo in the hardware handling. > > Going to switch to my Tonga in a minute, but I only got about half an > hour left before I need to get my daughter from kindergarten. > > Christian. > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > amd-gfx Info Page - lists.freedesktop.org > <https://lists.freedesktop.org/mailman/listinfo/amd-gfx> > lists.freedesktop.org > To see the collection of prior postings to the list, visit the amd-gfx > Archives. Using amd-gfx: To post a message to all the list members, > send email ... > > > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx [-- Attachment #1.2: Type: text/html, Size: 7976 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2016-10-05 15:24 ` Deucher, Alexander 2016-10-11 13:13 ` Andy Furniss @ 2016-10-26 7:34 ` Yu, Xiangliang [not found] ` <CY4PR12MB1701A02391D1C48C729FF51EEBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 2 siblings, 1 reply; 22+ messages in thread From: Yu, Xiangliang @ 2016-10-26 7:34 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Hi Christian, Could you help put type, aligan_mask, nop of amdgpu_ring_funcs struct field into amdgpu_ring struct? I think amdgpu_ring_funcs should include function pointer, not attribute. Your patches is not follow the struct design, and the amdgpu_ring will lost the meaning. Thanks! Xiangliang Yu > -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf > Of Christian K?nig > Sent: Wednesday, October 05, 2016 10:13 PM > To: amd-gfx@lists.freedesktop.org > Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs > as well > > From: Christian König <christian.koenig@amd.com> > > They are constant as well. > > Signed-off-by: Christian König <christian.koenig@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++---------- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > 14 files changed, 58 insertions(+), 43 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > index b2df735..a141b46 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, > unsigned ndw) { > /* Align requested size with padding so unlock_commit can > * pad safely */ > - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; > > /* Make sure we aren't trying to allocate more space > * than the maximum for one submission @@ -94,7 +94,7 @@ void > amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > int i; > > for (i = 0; i < count; i++) > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ -106,8 > +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > uint32_t count) > */ > void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct > amdgpu_ib *ib) { > - while (ib->length_dw & ring->align_mask) > - ib->ptr[ib->length_dw++] = ring->nop; > + while (ib->length_dw & ring->funcs->align_mask) > + ib->ptr[ib->length_dw++] = ring->funcs->nop; > } > > /** > @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) > uint32_t count; > > /* We pad to match fetch size */ > - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > - count %= ring->align_mask + 1; > + count = ring->funcs->align_mask + 1 - > + (ring->wptr & ring->funcs->align_mask); > + count %= ring->funcs->align_mask + 1; > ring->funcs->insert_nop(ring, count); > > mb(); > @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) > * Returns 0 on success, error on failure. > */ > int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > *ring, > - unsigned max_dw, u32 nop, u32 align_mask, > - struct amdgpu_irq_src *irq_src, unsigned irq_type) > + unsigned max_dw, struct amdgpu_irq_src *irq_src, > + unsigned irq_type) > { > int r; > > @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, > struct amdgpu_ring *ring, > > ring->ring_size = roundup_pow_of_two(max_dw * 4 * > amdgpu_sched_hw_submission); > - ring->align_mask = align_mask; > - ring->nop = nop; > > /* Allocate ring buffer */ > if (ring->ring_obj == NULL) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 6cf89c9..1ee1b65 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct > amdgpu_ring *ring); > /* provided by hw blocks that expose a ring buffer for commands */ struct > amdgpu_ring_funcs { > enum amdgpu_ring_type type; > + uint32_t align_mask; > + u32 nop; > > /* ring read/write ptr handling */ > u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ > struct amdgpu_ring { > unsigned max_dw; > int count_dw; > uint64_t gpu_addr; > - uint32_t align_mask; > uint32_t ptr_mask; > bool ready; > - u32 nop; > u32 idx; > u32 me; > u32 pipe; > @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > amdgpu_ring *ring, struct amdgpu_ib *ib); void amdgpu_ring_commit(struct > amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); int > amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, > - unsigned ring_size, u32 nop, u32 align_mask, > - struct amdgpu_irq_src *irq_src, unsigned irq_type); > + unsigned ring_size, struct amdgpu_irq_src *irq_src, > + unsigned irq_type); > void amdgpu_ring_fini(struct amdgpu_ring *ring); > > #endif > diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > index f91f02f..664f894 100644 > --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_NOP_COUNT(count - 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > 0), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { > > static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > .get_rptr = cik_sdma_ring_get_rptr, > .get_wptr = cik_sdma_ring_get_wptr, > .set_wptr = cik_sdma_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index 1f8687fd..367b14e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "gfx"); > r = amdgpu_ring_init(adev, ring, 1024, > - 0x80000000, 0xff, > &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) > sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, > ring->queue); > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > r = amdgpu_ring_init(adev, ring, 1024, > - 0x80000000, 0xff, > &adev->gfx.eop_irq, irq_type); > if (r) > return r; > @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = 0x80000000, > .get_rptr = gfx_v6_0_ring_get_rptr, > .get_wptr = gfx_v6_0_ring_get_wptr, > .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ > static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = 0x80000000, > .get_rptr = gfx_v6_0_ring_get_rptr, > .get_wptr = gfx_v6_0_ring_get_wptr, > .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git > a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index be3881e..15f24bd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > ring->ring_obj = NULL; > sprintf(ring->name, "gfx"); > r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > /* type-2 packets are deprecated on MEC, use type-3 instead > */ > r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > &adev->gfx.eop_irq, irq_type); > if (r) > return r; > @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v7_0_ring_get_rptr, > .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ > static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v7_0_ring_get_rptr, > .get_wptr = gfx_v7_0_ring_get_wptr_compute, > .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git > a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 0d66f49..51f1139 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > ring->doorbell_index = > AMDGPU_DOORBELL_GFX_RING0; > } > > - r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > - &adev->gfx.eop_irq, > AMDGPU_CP_IRQ_GFX_EOP); > + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > + AMDGPU_CP_IRQ_GFX_EOP); > if (r) > return r; > } > @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- > >pipe, ring->queue); > irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > + ring->pipe; > /* type-2 packets are deprecated on MEC, use type-3 instead > */ > - r = amdgpu_ring_init(adev, ring, 1024, > - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > - &adev->gfx.eop_irq, irq_type); > + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > + irq_type); > if (r) > return r; > } > @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { > > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > .type = AMDGPU_RING_TYPE_GFX, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v8_0_ring_get_rptr, > .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > > static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { > .type = AMDGPU_RING_TYPE_COMPUTE, > + .align_mask = 0xff, > + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > .get_rptr = gfx_v8_0_ring_get_rptr, > .get_wptr = gfx_v8_0_ring_get_wptr_compute, > .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git > a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > index b11a81e..49c47d6 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > ring->use_doorbell = false; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - > SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { > > static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .get_rptr = sdma_v2_4_ring_get_rptr, > .get_wptr = sdma_v2_4_ring_get_wptr, > .set_wptr = sdma_v2_4_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > index accf4d1..f8ec370 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct > amdgpu_ring *ring, uint32_t count) > > for (i = 0; i < count; i++) > if (sdma && sdma->burst_nop && (i == 0)) > - amdgpu_ring_write(ring, ring->nop | > + amdgpu_ring_write(ring, ring->funcs->nop | > SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > else > - amdgpu_ring_write(ring, ring->nop); > + amdgpu_ring_write(ring, ring->funcs->nop); > } > > /** > @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) > > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - > SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { > > static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > .get_rptr = sdma_v3_0_ring_get_rptr, > .get_wptr = sdma_v3_0_ring_get_wptr, > .set_wptr = sdma_v3_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c > b/drivers/gpu/drm/amd/amdgpu/si_dma.c > index 1aee45b..7fece1f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > ring->use_doorbell = false; > sprintf(ring->name, "sdma%d", i); > r = amdgpu_ring_init(adev, ring, 1024, > - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > 0), 0xf, > &adev->sdma.trap_irq, > (i == 0) ? > AMDGPU_SDMA_IRQ_TRAP0 : > @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { > > static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > .type = AMDGPU_RING_TYPE_SDMA, > + .align_mask = 0xf, > + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > .get_rptr = si_dma_ring_get_rptr, > .get_wptr = si_dma_ring_get_wptr, > .set_wptr = si_dma_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > index 55af8ac..1bab75a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { > > static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v4_2_ring_get_rptr, > .get_wptr = uvd_v4_2_ring_get_wptr, > .set_wptr = uvd_v4_2_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 21e725b..ec848fc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > > static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v5_0_ring_get_rptr, > .get_wptr = uvd_v5_0_ring_get_wptr, > .set_wptr = uvd_v5_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index 2ce1818..15708f8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > > ring = &adev->uvd.ring; > sprintf(ring->name, "uvd"); > - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > 0xf, > - &adev->uvd.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > return r; > } > @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > uvd_v6_0_ring_phys_funcs = { > > static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_UVD, > + .align_mask = 0xf, > + .nop = PACKET0(mmUVD_NO_OP, 0), > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > index cf0c68f..d585839 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > for (i = 0; i < adev->vce.num_rings; i++) { > ring = &adev->vce.ring[i]; > sprintf(ring->name, "vce%d", i); > - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > + r = amdgpu_ring_init(adev, ring, 512, > &adev->vce.irq, 0); > if (r) > return r; > @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { > > static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > .type = AMDGPU_RING_TYPE_VCE, > + .align_mask = 0xf, > + .nop = VCE_CMD_NO_OP, > .get_rptr = vce_v2_0_ring_get_rptr, > .get_wptr = vce_v2_0_ring_get_wptr, > .set_wptr = vce_v2_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > index 56a3feb..f7dbd0d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > for (i = 0; i < adev->vce.num_rings; i++) { > ring = &adev->vce.ring[i]; > sprintf(ring->name, "vce%d", i); > - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > - &adev->vce.irq, 0); > + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); > if (r) > return r; > } > @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > vce_v3_0_ring_phys_funcs = { > > static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCE, > + .align_mask = 0xf, > + .nop = VCE_CMD_NO_OP, > .get_rptr = vce_v3_0_ring_get_rptr, > .get_wptr = vce_v3_0_ring_get_wptr, > .set_wptr = vce_v3_0_ring_set_wptr, > -- > 2.5.0 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CY4PR12MB1701A02391D1C48C729FF51EEBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CY4PR12MB1701A02391D1C48C729FF51EEBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-10-26 9:16 ` Christian König [not found] ` <0d8b9683-01c5-0fdc-d52f-bfdf2a0fa67c-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Christian König @ 2016-10-26 9:16 UTC (permalink / raw) To: Yu, Xiangliang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Hi Xiangliang, NAK, we agreed upon moving the constant data into the functions structure as well. How about renaming the amdgpu_ring_funcs structure to make clear that it isn't only functions any more? Something amdgpu_ring_params or something like that? Regards, Christian. Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: > Hi Christian, > > Could you help put type, aligan_mask, nop of amdgpu_ring_funcs struct field into amdgpu_ring struct? > I think amdgpu_ring_funcs should include function pointer, not attribute. Your patches is not follow the > struct design, and the amdgpu_ring will lost the meaning. > > > Thanks! > Xiangliang Yu > >> -----Original Message----- >> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf >> Of Christian K?nig >> Sent: Wednesday, October 05, 2016 10:13 PM >> To: amd-gfx@lists.freedesktop.org >> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs >> as well >> >> From: Christian König <christian.koenig@amd.com> >> >> They are constant as well. >> >> Signed-off-by: Christian König <christian.koenig@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++---------- >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- >> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ >> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- >> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- >> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- >> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- >> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- >> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- >> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- >> 14 files changed, 58 insertions(+), 43 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> index b2df735..a141b46 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, >> unsigned ndw) { >> /* Align requested size with padding so unlock_commit can >> * pad safely */ >> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; >> + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; >> >> /* Make sure we aren't trying to allocate more space >> * than the maximum for one submission @@ -94,7 +94,7 @@ void >> amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) >> int i; >> >> for (i = 0; i < count; i++) >> - amdgpu_ring_write(ring, ring->nop); >> + amdgpu_ring_write(ring, ring->funcs->nop); >> } >> >> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ -106,8 >> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, >> uint32_t count) >> */ >> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct >> amdgpu_ib *ib) { >> - while (ib->length_dw & ring->align_mask) >> - ib->ptr[ib->length_dw++] = ring->nop; >> + while (ib->length_dw & ring->funcs->align_mask) >> + ib->ptr[ib->length_dw++] = ring->funcs->nop; >> } >> >> /** >> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring) >> uint32_t count; >> >> /* We pad to match fetch size */ >> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); >> - count %= ring->align_mask + 1; >> + count = ring->funcs->align_mask + 1 - >> + (ring->wptr & ring->funcs->align_mask); >> + count %= ring->funcs->align_mask + 1; >> ring->funcs->insert_nop(ring, count); >> >> mb(); >> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) >> * Returns 0 on success, error on failure. >> */ >> int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring >> *ring, >> - unsigned max_dw, u32 nop, u32 align_mask, >> - struct amdgpu_irq_src *irq_src, unsigned irq_type) >> + unsigned max_dw, struct amdgpu_irq_src *irq_src, >> + unsigned irq_type) >> { >> int r; >> >> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, >> struct amdgpu_ring *ring, >> >> ring->ring_size = roundup_pow_of_two(max_dw * 4 * >> amdgpu_sched_hw_submission); >> - ring->align_mask = align_mask; >> - ring->nop = nop; >> >> /* Allocate ring buffer */ >> if (ring->ring_obj == NULL) { >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> index 6cf89c9..1ee1b65 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct >> amdgpu_ring *ring); >> /* provided by hw blocks that expose a ring buffer for commands */ struct >> amdgpu_ring_funcs { >> enum amdgpu_ring_type type; >> + uint32_t align_mask; >> + u32 nop; >> >> /* ring read/write ptr handling */ >> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ >> struct amdgpu_ring { >> unsigned max_dw; >> int count_dw; >> uint64_t gpu_addr; >> - uint32_t align_mask; >> uint32_t ptr_mask; >> bool ready; >> - u32 nop; >> u32 idx; >> u32 me; >> u32 pipe; >> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct >> amdgpu_ring *ring, struct amdgpu_ib *ib); void amdgpu_ring_commit(struct >> amdgpu_ring *ring); void amdgpu_ring_undo(struct amdgpu_ring *ring); int >> amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, >> - unsigned ring_size, u32 nop, u32 align_mask, >> - struct amdgpu_irq_src *irq_src, unsigned irq_type); >> + unsigned ring_size, struct amdgpu_irq_src *irq_src, >> + unsigned irq_type); >> void amdgpu_ring_fini(struct amdgpu_ring *ring); >> >> #endif >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> index f91f02f..664f894 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct >> amdgpu_ring *ring, uint32_t count) >> >> for (i = 0; i < count; i++) >> if (sdma && sdma->burst_nop && (i == 0)) >> - amdgpu_ring_write(ring, ring->nop | >> + amdgpu_ring_write(ring, ring->funcs->nop | >> SDMA_NOP_COUNT(count - 1)); >> else >> - amdgpu_ring_write(ring, ring->nop); >> + amdgpu_ring_write(ring, ring->funcs->nop); >> } >> >> /** >> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) >> ring->ring_obj = NULL; >> sprintf(ring->name, "sdma%d", i); >> r = amdgpu_ring_init(adev, ring, 1024, >> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, >> 0), 0xf, >> &adev->sdma.trap_irq, >> (i == 0) ? >> AMDGPU_SDMA_IRQ_TRAP0 : >> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = { >> >> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { >> .type = AMDGPU_RING_TYPE_SDMA, >> + .align_mask = 0xf, >> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), >> .get_rptr = cik_sdma_ring_get_rptr, >> .get_wptr = cik_sdma_ring_get_wptr, >> .set_wptr = cik_sdma_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> index 1f8687fd..367b14e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) >> ring->ring_obj = NULL; >> sprintf(ring->name, "gfx"); >> r = amdgpu_ring_init(adev, ring, 1024, >> - 0x80000000, 0xff, >> &adev->gfx.eop_irq, >> AMDGPU_CP_IRQ_GFX_EOP); >> if (r) >> return r; >> @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) >> sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, >> ring->queue); >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> + ring->pipe; >> r = amdgpu_ring_init(adev, ring, 1024, >> - 0x80000000, 0xff, >> &adev->gfx.eop_irq, irq_type); >> if (r) >> return r; >> @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { >> .type = AMDGPU_RING_TYPE_GFX, >> + .align_mask = 0xff, >> + .nop = 0x80000000, >> .get_rptr = gfx_v6_0_ring_get_rptr, >> .get_wptr = gfx_v6_0_ring_get_wptr, >> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { >> >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { >> .type = AMDGPU_RING_TYPE_COMPUTE, >> + .align_mask = 0xff, >> + .nop = 0x80000000, >> .get_rptr = gfx_v6_0_ring_get_rptr, >> .get_wptr = gfx_v6_0_ring_get_wptr, >> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git >> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> index be3881e..15f24bd 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) >> ring->ring_obj = NULL; >> sprintf(ring->name, "gfx"); >> r = amdgpu_ring_init(adev, ring, 1024, >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> &adev->gfx.eop_irq, >> AMDGPU_CP_IRQ_GFX_EOP); >> if (r) >> return r; >> @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> + ring->pipe; >> /* type-2 packets are deprecated on MEC, use type-3 instead >> */ >> r = amdgpu_ring_init(adev, ring, 1024, >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> &adev->gfx.eop_irq, irq_type); >> if (r) >> return r; >> @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { >> .type = AMDGPU_RING_TYPE_GFX, >> + .align_mask = 0xff, >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> .get_rptr = gfx_v7_0_ring_get_rptr, >> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, >> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { >> >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { >> .type = AMDGPU_RING_TYPE_COMPUTE, >> + .align_mask = 0xff, >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> .get_rptr = gfx_v7_0_ring_get_rptr, >> .get_wptr = gfx_v7_0_ring_get_wptr_compute, >> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git >> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> index 0d66f49..51f1139 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) >> ring->doorbell_index = >> AMDGPU_DOORBELL_GFX_RING0; >> } >> >> - r = amdgpu_ring_init(adev, ring, 1024, >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> - &adev->gfx.eop_irq, >> AMDGPU_CP_IRQ_GFX_EOP); >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >> + AMDGPU_CP_IRQ_GFX_EOP); >> if (r) >> return r; >> } >> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) >> sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- >>> pipe, ring->queue); >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> + ring->pipe; >> /* type-2 packets are deprecated on MEC, use type-3 instead >> */ >> - r = amdgpu_ring_init(adev, ring, 1024, >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> - &adev->gfx.eop_irq, irq_type); >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >> + irq_type); >> if (r) >> return r; >> } >> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { >> .type = AMDGPU_RING_TYPE_GFX, >> + .align_mask = 0xff, >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> .get_rptr = gfx_v8_0_ring_get_rptr, >> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, >> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { >> >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { >> .type = AMDGPU_RING_TYPE_COMPUTE, >> + .align_mask = 0xff, >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> .get_rptr = gfx_v8_0_ring_get_rptr, >> .get_wptr = gfx_v8_0_ring_get_wptr_compute, >> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> index b11a81e..49c47d6 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct >> amdgpu_ring *ring, uint32_t count) >> >> for (i = 0; i < count; i++) >> if (sdma && sdma->burst_nop && (i == 0)) >> - amdgpu_ring_write(ring, ring->nop | >> + amdgpu_ring_write(ring, ring->funcs->nop | >> SDMA_PKT_NOP_HEADER_COUNT(count - >> 1)); >> else >> - amdgpu_ring_write(ring, ring->nop); >> + amdgpu_ring_write(ring, ring->funcs->nop); >> } >> >> /** >> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) >> ring->use_doorbell = false; >> sprintf(ring->name, "sdma%d", i); >> r = amdgpu_ring_init(adev, ring, 1024, >> - >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >> &adev->sdma.trap_irq, >> (i == 0) ? >> AMDGPU_SDMA_IRQ_TRAP0 : >> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = { >> >> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { >> .type = AMDGPU_RING_TYPE_SDMA, >> + .align_mask = 0xf, >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >> .get_rptr = sdma_v2_4_ring_get_rptr, >> .get_wptr = sdma_v2_4_ring_get_wptr, >> .set_wptr = sdma_v2_4_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> index accf4d1..f8ec370 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct >> amdgpu_ring *ring, uint32_t count) >> >> for (i = 0; i < count; i++) >> if (sdma && sdma->burst_nop && (i == 0)) >> - amdgpu_ring_write(ring, ring->nop | >> + amdgpu_ring_write(ring, ring->funcs->nop | >> SDMA_PKT_NOP_HEADER_COUNT(count - >> 1)); >> else >> - amdgpu_ring_write(ring, ring->nop); >> + amdgpu_ring_write(ring, ring->funcs->nop); >> } >> >> /** >> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) >> >> sprintf(ring->name, "sdma%d", i); >> r = amdgpu_ring_init(adev, ring, 1024, >> - >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >> &adev->sdma.trap_irq, >> (i == 0) ? >> AMDGPU_SDMA_IRQ_TRAP0 : >> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { >> .type = AMDGPU_RING_TYPE_SDMA, >> + .align_mask = 0xf, >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >> .get_rptr = sdma_v3_0_ring_get_rptr, >> .get_wptr = sdma_v3_0_ring_get_wptr, >> .set_wptr = sdma_v3_0_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c >> b/drivers/gpu/drm/amd/amdgpu/si_dma.c >> index 1aee45b..7fece1f 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c >> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c >> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) >> ring->use_doorbell = false; >> sprintf(ring->name, "sdma%d", i); >> r = amdgpu_ring_init(adev, ring, 1024, >> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, >> 0), 0xf, >> &adev->sdma.trap_irq, >> (i == 0) ? >> AMDGPU_SDMA_IRQ_TRAP0 : >> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { >> >> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { >> .type = AMDGPU_RING_TYPE_SDMA, >> + .align_mask = 0xf, >> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), >> .get_rptr = si_dma_ring_get_rptr, >> .get_wptr = si_dma_ring_get_wptr, >> .set_wptr = si_dma_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> index 55af8ac..1bab75a 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) >> >> ring = &adev->uvd.ring; >> sprintf(ring->name, "uvd"); >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> 0xf, >> - &adev->uvd.irq, 0); >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> >> return r; >> } >> @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { >> >> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { >> .type = AMDGPU_RING_TYPE_UVD, >> + .align_mask = 0xf, >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> .get_rptr = uvd_v4_2_ring_get_rptr, >> .get_wptr = uvd_v4_2_ring_get_wptr, >> .set_wptr = uvd_v4_2_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> index 21e725b..ec848fc 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) >> >> ring = &adev->uvd.ring; >> sprintf(ring->name, "uvd"); >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> 0xf, >> - &adev->uvd.irq, 0); >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> >> return r; >> } >> @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { >> .type = AMDGPU_RING_TYPE_UVD, >> + .align_mask = 0xf, >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> .get_rptr = uvd_v5_0_ring_get_rptr, >> .get_wptr = uvd_v5_0_ring_get_wptr, >> .set_wptr = uvd_v5_0_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> index 2ce1818..15708f8 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) >> >> ring = &adev->uvd.ring; >> sprintf(ring->name, "uvd"); >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> 0xf, >> - &adev->uvd.irq, 0); >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> >> return r; >> } >> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs >> uvd_v6_0_ring_phys_funcs = { >> >> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { >> .type = AMDGPU_RING_TYPE_UVD, >> + .align_mask = 0xf, >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> .get_rptr = uvd_v6_0_ring_get_rptr, >> .get_wptr = uvd_v6_0_ring_get_wptr, >> .set_wptr = uvd_v6_0_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> index cf0c68f..d585839 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) >> for (i = 0; i < adev->vce.num_rings; i++) { >> ring = &adev->vce.ring[i]; >> sprintf(ring->name, "vce%d", i); >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, >> + r = amdgpu_ring_init(adev, ring, 512, >> &adev->vce.irq, 0); >> if (r) >> return r; >> @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { >> >> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { >> .type = AMDGPU_RING_TYPE_VCE, >> + .align_mask = 0xf, >> + .nop = VCE_CMD_NO_OP, >> .get_rptr = vce_v2_0_ring_get_rptr, >> .get_wptr = vce_v2_0_ring_get_wptr, >> .set_wptr = vce_v2_0_ring_set_wptr, >> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> index 56a3feb..f7dbd0d 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) >> for (i = 0; i < adev->vce.num_rings; i++) { >> ring = &adev->vce.ring[i]; >> sprintf(ring->name, "vce%d", i); >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, >> - &adev->vce.irq, 0); >> + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); >> if (r) >> return r; >> } >> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs >> vce_v3_0_ring_phys_funcs = { >> >> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { >> .type = AMDGPU_RING_TYPE_VCE, >> + .align_mask = 0xf, >> + .nop = VCE_CMD_NO_OP, >> .get_rptr = vce_v3_0_ring_get_rptr, >> .get_wptr = vce_v3_0_ring_get_wptr, >> .set_wptr = vce_v3_0_ring_set_wptr, >> -- >> 2.5.0 >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <0d8b9683-01c5-0fdc-d52f-bfdf2a0fa67c-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <0d8b9683-01c5-0fdc-d52f-bfdf2a0fa67c-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-26 14:18 ` Yu, Xiangliang [not found] ` <CY4PR12MB170187E251705A2617860F49EBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Yu, Xiangliang @ 2016-10-26 14:18 UTC (permalink / raw) To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > Hi Xiangliang, > > NAK, we agreed upon moving the constant data into the functions structure > as well. > > How about renaming the amdgpu_ring_funcs structure to make clear that it > isn't only functions any more? Something amdgpu_ring_params or > something like that? Why not create a new structure for the constant data? It can make code more flexible. Actually, I'm working on SRIOV patches, I need the amdgpu_ring_funcs structure so That easy to inherint all of function. > > Regards, > Christian. > > Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: > > Hi Christian, > > > > Could you help put type, aligan_mask, nop of amdgpu_ring_funcs struct > field into amdgpu_ring struct? > > I think amdgpu_ring_funcs should include function pointer, not > > attribute. Your patches is not follow the struct design, and the > amdgpu_ring will lost the meaning. > > > > > > Thanks! > > Xiangliang Yu > > > >> -----Original Message----- > >> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On > >> Behalf Of Christian K?nig > >> Sent: Wednesday, October 05, 2016 10:13 PM > >> To: amd-gfx@lists.freedesktop.org > >> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring > >> funcs as well > >> > >> From: Christian König <christian.koenig@amd.com> > >> > >> They are constant as well. > >> > >> Signed-off-by: Christian König <christian.koenig@amd.com> > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++---------- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > >> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > >> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > >> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > >> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > >> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > >> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > >> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > >> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > >> 14 files changed, 58 insertions(+), 43 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> index b2df735..a141b46 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, > >> unsigned ndw) { > >> /* Align requested size with padding so unlock_commit can > >> * pad safely */ > >> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > >> + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; > >> > >> /* Make sure we aren't trying to allocate more space > >> * than the maximum for one submission @@ -94,7 +94,7 @@ void > >> amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > >> int i; > >> > >> for (i = 0; i < count; i++) > >> - amdgpu_ring_write(ring, ring->nop); > >> + amdgpu_ring_write(ring, ring->funcs->nop); > >> } > >> > >> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ -106,8 > >> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > >> uint32_t count) > >> */ > >> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct > >> amdgpu_ib *ib) { > >> - while (ib->length_dw & ring->align_mask) > >> - ib->ptr[ib->length_dw++] = ring->nop; > >> + while (ib->length_dw & ring->funcs->align_mask) > >> + ib->ptr[ib->length_dw++] = ring->funcs->nop; > >> } > >> > >> /** > >> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring > *ring) > >> uint32_t count; > >> > >> /* We pad to match fetch size */ > >> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > >> - count %= ring->align_mask + 1; > >> + count = ring->funcs->align_mask + 1 - > >> + (ring->wptr & ring->funcs->align_mask); > >> + count %= ring->funcs->align_mask + 1; > >> ring->funcs->insert_nop(ring, count); > >> > >> mb(); > >> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring *ring) > >> * Returns 0 on success, error on failure. > >> */ > >> int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > >> *ring, > >> - unsigned max_dw, u32 nop, u32 align_mask, > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type) > >> + unsigned max_dw, struct amdgpu_irq_src *irq_src, > >> + unsigned irq_type) > >> { > >> int r; > >> > >> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, > >> struct amdgpu_ring *ring, > >> > >> ring->ring_size = roundup_pow_of_two(max_dw * 4 * > >> amdgpu_sched_hw_submission); > >> - ring->align_mask = align_mask; > >> - ring->nop = nop; > >> > >> /* Allocate ring buffer */ > >> if (ring->ring_obj == NULL) { > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> index 6cf89c9..1ee1b65 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct > >> amdgpu_ring *ring); > >> /* provided by hw blocks that expose a ring buffer for commands */ > >> struct amdgpu_ring_funcs { > >> enum amdgpu_ring_type type; > >> + uint32_t align_mask; > >> + u32 nop; > >> > >> /* ring read/write ptr handling */ > >> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ > >> struct amdgpu_ring { > >> unsigned max_dw; > >> int count_dw; > >> uint64_t gpu_addr; > >> - uint32_t align_mask; > >> uint32_t ptr_mask; > >> bool ready; > >> - u32 nop; > >> u32 idx; > >> u32 me; > >> u32 pipe; > >> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > >> amdgpu_ring *ring, struct amdgpu_ib *ib); void > >> amdgpu_ring_commit(struct amdgpu_ring *ring); void > >> amdgpu_ring_undo(struct amdgpu_ring *ring); int > amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, > >> - unsigned ring_size, u32 nop, u32 align_mask, > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type); > >> + unsigned ring_size, struct amdgpu_irq_src *irq_src, > >> + unsigned irq_type); > >> void amdgpu_ring_fini(struct amdgpu_ring *ring); > >> > >> #endif > >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> index f91f02f..664f894 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct > >> amdgpu_ring *ring, uint32_t count) > >> > >> for (i = 0; i < count; i++) > >> if (sdma && sdma->burst_nop && (i == 0)) > >> - amdgpu_ring_write(ring, ring->nop | > >> + amdgpu_ring_write(ring, ring->funcs->nop | > >> SDMA_NOP_COUNT(count - 1)); > >> else > >> - amdgpu_ring_write(ring, ring->nop); > >> + amdgpu_ring_write(ring, ring->funcs->nop); > >> } > >> > >> /** > >> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > >> ring->ring_obj = NULL; > >> sprintf(ring->name, "sdma%d", i); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > >> 0), 0xf, > >> &adev->sdma.trap_irq, > >> (i == 0) ? > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = > { > >> > >> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_SDMA, > >> + .align_mask = 0xf, > >> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > >> .get_rptr = cik_sdma_ring_get_rptr, > >> .get_wptr = cik_sdma_ring_get_wptr, > >> .set_wptr = cik_sdma_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> index 1f8687fd..367b14e 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > >> ring->ring_obj = NULL; > >> sprintf(ring->name, "gfx"); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - 0x80000000, 0xff, > >> &adev->gfx.eop_irq, > >> AMDGPU_CP_IRQ_GFX_EOP); > >> if (r) > >> return r; > >> @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) > >> sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, > >> ring->queue); > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> + ring->pipe; > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - 0x80000000, 0xff, > >> &adev->gfx.eop_irq, irq_type); > >> if (r) > >> return r; > >> @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs = > { > >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > >> .type = AMDGPU_RING_TYPE_GFX, > >> + .align_mask = 0xff, > >> + .nop = 0x80000000, > >> .get_rptr = gfx_v6_0_ring_get_rptr, > >> .get_wptr = gfx_v6_0_ring_get_wptr, > >> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = { > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> + .align_mask = 0xff, > >> + .nop = 0x80000000, > >> .get_rptr = gfx_v6_0_ring_get_rptr, > >> .get_wptr = gfx_v6_0_ring_get_wptr, > >> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> index be3881e..15f24bd 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > >> ring->ring_obj = NULL; > >> sprintf(ring->name, "gfx"); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> &adev->gfx.eop_irq, > >> AMDGPU_CP_IRQ_GFX_EOP); > >> if (r) > >> return r; > >> @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> + ring->pipe; > >> /* type-2 packets are deprecated on MEC, use type-3 instead > */ > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> &adev->gfx.eop_irq, irq_type); > >> if (r) > >> return r; > >> @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = > { > >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > >> .type = AMDGPU_RING_TYPE_GFX, > >> + .align_mask = 0xff, > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> .get_rptr = gfx_v7_0_ring_get_rptr, > >> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > >> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> + .align_mask = 0xff, > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> .get_rptr = gfx_v7_0_ring_get_rptr, > >> .get_wptr = gfx_v7_0_ring_get_wptr_compute, > >> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> index 0d66f49..51f1139 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > >> ring->doorbell_index = > >> AMDGPU_DOORBELL_GFX_RING0; > >> } > >> > >> - r = amdgpu_ring_init(adev, ring, 1024, > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> - &adev->gfx.eop_irq, > >> AMDGPU_CP_IRQ_GFX_EOP); > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > >> + AMDGPU_CP_IRQ_GFX_EOP); > >> if (r) > >> return r; > >> } > >> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > >> sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- > >>> pipe, ring->queue); > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> + ring->pipe; > >> /* type-2 packets are deprecated on MEC, use type-3 instead > */ > >> - r = amdgpu_ring_init(adev, ring, 1024, > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> - &adev->gfx.eop_irq, irq_type); > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > >> + irq_type); > >> if (r) > >> return r; > >> } > >> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = > { > >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > >> .type = AMDGPU_RING_TYPE_GFX, > >> + .align_mask = 0xff, > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> .get_rptr = gfx_v8_0_ring_get_rptr, > >> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > >> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> + .align_mask = 0xff, > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> .get_rptr = gfx_v8_0_ring_get_rptr, > >> .get_wptr = gfx_v8_0_ring_get_wptr_compute, > >> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> index b11a81e..49c47d6 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct > >> amdgpu_ring *ring, uint32_t count) > >> > >> for (i = 0; i < count; i++) > >> if (sdma && sdma->burst_nop && (i == 0)) > >> - amdgpu_ring_write(ring, ring->nop | > >> + amdgpu_ring_write(ring, ring->funcs->nop | > >> SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > >> else > >> - amdgpu_ring_write(ring, ring->nop); > >> + amdgpu_ring_write(ring, ring->funcs->nop); > >> } > >> > >> /** > >> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > >> ring->use_doorbell = false; > >> sprintf(ring->name, "sdma%d", i); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >> &adev->sdma.trap_irq, > >> (i == 0) ? > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs > = > >> { > >> > >> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_SDMA, > >> + .align_mask = 0xf, > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >> .get_rptr = sdma_v2_4_ring_get_rptr, > >> .get_wptr = sdma_v2_4_ring_get_wptr, > >> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> index accf4d1..f8ec370 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct > >> amdgpu_ring *ring, uint32_t count) > >> > >> for (i = 0; i < count; i++) > >> if (sdma && sdma->burst_nop && (i == 0)) > >> - amdgpu_ring_write(ring, ring->nop | > >> + amdgpu_ring_write(ring, ring->funcs->nop | > >> SDMA_PKT_NOP_HEADER_COUNT(count - > 1)); > >> else > >> - amdgpu_ring_write(ring, ring->nop); > >> + amdgpu_ring_write(ring, ring->funcs->nop); > >> } > >> > >> /** > >> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) > >> > >> sprintf(ring->name, "sdma%d", i); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >> &adev->sdma.trap_irq, > >> (i == 0) ? > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs > = > >> { > >> > >> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_SDMA, > >> + .align_mask = 0xf, > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >> .get_rptr = sdma_v3_0_ring_get_rptr, > >> .get_wptr = sdma_v3_0_ring_get_wptr, > >> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> index 1aee45b..7fece1f 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > >> ring->use_doorbell = false; > >> sprintf(ring->name, "sdma%d", i); > >> r = amdgpu_ring_init(adev, ring, 1024, > >> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > >> 0), 0xf, > >> &adev->sdma.trap_irq, > >> (i == 0) ? > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { > >> > >> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_SDMA, > >> + .align_mask = 0xf, > >> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > >> .get_rptr = si_dma_ring_get_rptr, > >> .get_wptr = si_dma_ring_get_wptr, > >> .set_wptr = si_dma_ring_set_wptr, > >> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> index 55af8ac..1bab75a 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > >> > >> ring = &adev->uvd.ring; > >> sprintf(ring->name, "uvd"); > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > >> 0xf, > >> - &adev->uvd.irq, 0); > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > >> > >> return r; > >> } > >> @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = { > >> > >> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_UVD, > >> + .align_mask = 0xf, > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> .get_rptr = uvd_v4_2_ring_get_rptr, > >> .get_wptr = uvd_v4_2_ring_get_wptr, > >> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> index 21e725b..ec848fc 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > >> > >> ring = &adev->uvd.ring; > >> sprintf(ring->name, "uvd"); > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > >> 0xf, > >> - &adev->uvd.irq, 0); > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > >> > >> return r; > >> } > >> @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = { > >> > >> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_UVD, > >> + .align_mask = 0xf, > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> .get_rptr = uvd_v5_0_ring_get_rptr, > >> .get_wptr = uvd_v5_0_ring_get_wptr, > >> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> index 2ce1818..15708f8 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > >> > >> ring = &adev->uvd.ring; > >> sprintf(ring->name, "uvd"); > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > >> 0xf, > >> - &adev->uvd.irq, 0); > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > >> > >> return r; > >> } > >> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > >> uvd_v6_0_ring_phys_funcs = { > >> > >> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > >> .type = AMDGPU_RING_TYPE_UVD, > >> + .align_mask = 0xf, > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> .get_rptr = uvd_v6_0_ring_get_rptr, > >> .get_wptr = uvd_v6_0_ring_get_wptr, > >> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> index cf0c68f..d585839 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > >> for (i = 0; i < adev->vce.num_rings; i++) { > >> ring = &adev->vce.ring[i]; > >> sprintf(ring->name, "vce%d", i); > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > >> + r = amdgpu_ring_init(adev, ring, 512, > >> &adev->vce.irq, 0); > >> if (r) > >> return r; > >> @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = { > >> > >> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > >> .type = AMDGPU_RING_TYPE_VCE, > >> + .align_mask = 0xf, > >> + .nop = VCE_CMD_NO_OP, > >> .get_rptr = vce_v2_0_ring_get_rptr, > >> .get_wptr = vce_v2_0_ring_get_wptr, > >> .set_wptr = vce_v2_0_ring_set_wptr, diff --git > >> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> index 56a3feb..f7dbd0d 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > >> for (i = 0; i < adev->vce.num_rings; i++) { > >> ring = &adev->vce.ring[i]; > >> sprintf(ring->name, "vce%d", i); > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > >> - &adev->vce.irq, 0); > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); > >> if (r) > >> return r; > >> } > >> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > >> vce_v3_0_ring_phys_funcs = { > >> > >> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { > >> .type = AMDGPU_RING_TYPE_VCE, > >> + .align_mask = 0xf, > >> + .nop = VCE_CMD_NO_OP, > >> .get_rptr = vce_v3_0_ring_get_rptr, > >> .get_wptr = vce_v3_0_ring_get_wptr, > >> .set_wptr = vce_v3_0_ring_set_wptr, > >> -- > >> 2.5.0 > >> > >> _______________________________________________ > >> amd-gfx mailing list > >> amd-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CY4PR12MB170187E251705A2617860F49EBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CY4PR12MB170187E251705A2617860F49EBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-10-27 9:55 ` Yu, Xiangliang [not found] ` <CY4PR12MB17015B2156B539C0540A2905EBAA0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Yu, Xiangliang @ 2016-10-27 9:55 UTC (permalink / raw) To: Yu, Xiangliang, Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > > > > NAK, we agreed upon moving the constant data into the functions > > structure as well. > > > > How about renaming the amdgpu_ring_funcs structure to make clear that > > it isn't only functions any more? Something amdgpu_ring_params or > > something like that? What benefit to put the constant data into the structure? If no, I'll create a new patch that create new structure for these constant data. > Why not create a new structure for the constant data? It can make code > more flexible. > Actually, I'm working on SRIOV patches, I need the amdgpu_ring_funcs > structure so That easy to inherint all of function. > > > > > Regards, > > Christian. > > > > Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: > > > Hi Christian, > > > > > > Could you help put type, aligan_mask, nop of amdgpu_ring_funcs > > > struct > > field into amdgpu_ring struct? > > > I think amdgpu_ring_funcs should include function pointer, not > > > attribute. Your patches is not follow the struct design, and the > > amdgpu_ring will lost the meaning. > > > > > > > > > Thanks! > > > Xiangliang Yu > > > > > >> -----Original Message----- > > >> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On > > >> Behalf Of Christian K?nig > > >> Sent: Wednesday, October 05, 2016 10:13 PM > > >> To: amd-gfx@lists.freedesktop.org > > >> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring > > >> funcs as well > > >> > > >> From: Christian König <christian.koenig@amd.com> > > >> > > >> They are constant as well. > > >> > > >> Signed-off-by: Christian König <christian.koenig@amd.com> > > >> --- > > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++-------- > -- > > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > > >> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > > >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > > >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > > >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > > >> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > > >> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > > >> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > > >> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > > >> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > > >> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > > >> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > > >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > > >> 14 files changed, 58 insertions(+), 43 deletions(-) > > >> > > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > > >> index b2df735..a141b46 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > > >> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, > > >> unsigned ndw) { > > >> /* Align requested size with padding so unlock_commit can > > >> * pad safely */ > > >> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > > >> + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; > > >> > > >> /* Make sure we aren't trying to allocate more space > > >> * than the maximum for one submission @@ -94,7 +94,7 @@ void > > >> amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) > > >> int i; > > >> > > >> for (i = 0; i < count; i++) > > >> - amdgpu_ring_write(ring, ring->nop); > > >> + amdgpu_ring_write(ring, ring->funcs->nop); > > >> } > > >> > > >> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ > > >> -106,8 > > >> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > > >> uint32_t count) > > >> */ > > >> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct > > >> amdgpu_ib *ib) { > > >> - while (ib->length_dw & ring->align_mask) > > >> - ib->ptr[ib->length_dw++] = ring->nop; > > >> + while (ib->length_dw & ring->funcs->align_mask) > > >> + ib->ptr[ib->length_dw++] = ring->funcs->nop; > > >> } > > >> > > >> /** > > >> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring > > *ring) > > >> uint32_t count; > > >> > > >> /* We pad to match fetch size */ > > >> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > > >> - count %= ring->align_mask + 1; > > >> + count = ring->funcs->align_mask + 1 - > > >> + (ring->wptr & ring->funcs->align_mask); > > >> + count %= ring->funcs->align_mask + 1; > > >> ring->funcs->insert_nop(ring, count); > > >> > > >> mb(); > > >> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring > *ring) > > >> * Returns 0 on success, error on failure. > > >> */ > > >> int amdgpu_ring_init(struct amdgpu_device *adev, struct > > >> amdgpu_ring *ring, > > >> - unsigned max_dw, u32 nop, u32 align_mask, > > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type) > > >> + unsigned max_dw, struct amdgpu_irq_src *irq_src, > > >> + unsigned irq_type) > > >> { > > >> int r; > > >> > > >> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device > > >> *adev, struct amdgpu_ring *ring, > > >> > > >> ring->ring_size = roundup_pow_of_two(max_dw * 4 * > > >> amdgpu_sched_hw_submission); > > >> - ring->align_mask = align_mask; > > >> - ring->nop = nop; > > >> > > >> /* Allocate ring buffer */ > > >> if (ring->ring_obj == NULL) { > > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > > >> index 6cf89c9..1ee1b65 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > > >> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct > > >> amdgpu_ring *ring); > > >> /* provided by hw blocks that expose a ring buffer for commands > > >> */ struct amdgpu_ring_funcs { > > >> enum amdgpu_ring_type type; > > >> + uint32_t align_mask; > > >> + u32 nop; > > >> > > >> /* ring read/write ptr handling */ > > >> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ > > >> struct amdgpu_ring { > > >> unsigned max_dw; > > >> int count_dw; > > >> uint64_t gpu_addr; > > >> - uint32_t align_mask; > > >> uint32_t ptr_mask; > > >> bool ready; > > >> - u32 nop; > > >> u32 idx; > > >> u32 me; > > >> u32 pipe; > > >> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > > >> amdgpu_ring *ring, struct amdgpu_ib *ib); void > > >> amdgpu_ring_commit(struct amdgpu_ring *ring); void > > >> amdgpu_ring_undo(struct amdgpu_ring *ring); int > > amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, > > >> - unsigned ring_size, u32 nop, u32 align_mask, > > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type); > > >> + unsigned ring_size, struct amdgpu_irq_src *irq_src, > > >> + unsigned irq_type); > > >> void amdgpu_ring_fini(struct amdgpu_ring *ring); > > >> > > >> #endif > > >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > > >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > > >> index f91f02f..664f894 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > > >> @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct > > >> amdgpu_ring *ring, uint32_t count) > > >> > > >> for (i = 0; i < count; i++) > > >> if (sdma && sdma->burst_nop && (i == 0)) > > >> - amdgpu_ring_write(ring, ring->nop | > > >> + amdgpu_ring_write(ring, ring->funcs->nop | > > >> SDMA_NOP_COUNT(count - 1)); > > >> else > > >> - amdgpu_ring_write(ring, ring->nop); > > >> + amdgpu_ring_write(ring, ring->funcs->nop); > > >> } > > >> > > >> /** > > >> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > > >> ring->ring_obj = NULL; > > >> sprintf(ring->name, "sdma%d", i); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > > >> 0), 0xf, > > >> &adev->sdma.trap_irq, > > >> (i == 0) ? > > >> AMDGPU_SDMA_IRQ_TRAP0 : > > >> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs > = > > { > > >> > > >> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_SDMA, > > >> + .align_mask = 0xf, > > >> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > > >> .get_rptr = cik_sdma_ring_get_rptr, > > >> .get_wptr = cik_sdma_ring_get_wptr, > > >> .set_wptr = cik_sdma_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > >> index 1f8687fd..367b14e 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > >> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > > >> ring->ring_obj = NULL; > > >> sprintf(ring->name, "gfx"); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - 0x80000000, 0xff, > > >> &adev->gfx.eop_irq, > > >> AMDGPU_CP_IRQ_GFX_EOP); > > >> if (r) > > >> return r; > > >> @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) > > >> sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, > > >> ring->queue); > > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > > >> + ring->pipe; > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - 0x80000000, 0xff, > > >> &adev->gfx.eop_irq, irq_type); > > >> if (r) > > >> return r; > > >> @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs > = > > { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > > >> .type = AMDGPU_RING_TYPE_GFX, > > >> + .align_mask = 0xff, > > >> + .nop = 0x80000000, > > >> .get_rptr = gfx_v6_0_ring_get_rptr, > > >> .get_wptr = gfx_v6_0_ring_get_wptr, > > >> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ > > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute > = { > > >> .type = AMDGPU_RING_TYPE_COMPUTE, > > >> + .align_mask = 0xff, > > >> + .nop = 0x80000000, > > >> .get_rptr = gfx_v6_0_ring_get_rptr, > > >> .get_wptr = gfx_v6_0_ring_get_wptr, > > >> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > >> index be3881e..15f24bd 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > >> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > > >> ring->ring_obj = NULL; > > >> sprintf(ring->name, "gfx"); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > > >> &adev->gfx.eop_irq, > > >> AMDGPU_CP_IRQ_GFX_EOP); > > >> if (r) > > >> return r; > > >> @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) > > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > > >> + ring->pipe; > > >> /* type-2 packets are deprecated on MEC, use type-3 instead > > */ > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > > >> &adev->gfx.eop_irq, irq_type); > > >> if (r) > > >> return r; > > >> @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs > = > > { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > > >> .type = AMDGPU_RING_TYPE_GFX, > > >> + .align_mask = 0xff, > > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > > >> .get_rptr = gfx_v7_0_ring_get_rptr, > > >> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > > >> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ > > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute > = { > > >> .type = AMDGPU_RING_TYPE_COMPUTE, > > >> + .align_mask = 0xff, > > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > > >> .get_rptr = gfx_v7_0_ring_get_rptr, > > >> .get_wptr = gfx_v7_0_ring_get_wptr_compute, > > >> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > >> index 0d66f49..51f1139 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > > >> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > > >> ring->doorbell_index = > > >> AMDGPU_DOORBELL_GFX_RING0; > > >> } > > >> > > >> - r = amdgpu_ring_init(adev, ring, 1024, > > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > > >> - &adev->gfx.eop_irq, > > >> AMDGPU_CP_IRQ_GFX_EOP); > > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > > >> + AMDGPU_CP_IRQ_GFX_EOP); > > >> if (r) > > >> return r; > > >> } > > >> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > > >> sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- > > >>> pipe, ring->queue); > > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > > >> + ring->pipe; > > >> /* type-2 packets are deprecated on MEC, use type-3 instead > > */ > > >> - r = amdgpu_ring_init(adev, ring, 1024, > > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > > >> - &adev->gfx.eop_irq, irq_type); > > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > > >> + irq_type); > > >> if (r) > > >> return r; > > >> } > > >> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs > = > > { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > > >> .type = AMDGPU_RING_TYPE_GFX, > > >> + .align_mask = 0xff, > > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > > >> .get_rptr = gfx_v8_0_ring_get_rptr, > > >> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > > >> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ > > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > > >> > > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute > = { > > >> .type = AMDGPU_RING_TYPE_COMPUTE, > > >> + .align_mask = 0xff, > > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > > >> .get_rptr = gfx_v8_0_ring_get_rptr, > > >> .get_wptr = gfx_v8_0_ring_get_wptr_compute, > > >> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > > >> index b11a81e..49c47d6 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > > >> @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct > > >> amdgpu_ring *ring, uint32_t count) > > >> > > >> for (i = 0; i < count; i++) > > >> if (sdma && sdma->burst_nop && (i == 0)) > > >> - amdgpu_ring_write(ring, ring->nop | > > >> + amdgpu_ring_write(ring, ring->funcs->nop | > > >> SDMA_PKT_NOP_HEADER_COUNT(count - > > 1)); > > >> else > > >> - amdgpu_ring_write(ring, ring->nop); > > >> + amdgpu_ring_write(ring, ring->funcs->nop); > > >> } > > >> > > >> /** > > >> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > > >> ring->use_doorbell = false; > > >> sprintf(ring->name, "sdma%d", i); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - > > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > > >> &adev->sdma.trap_irq, > > >> (i == 0) ? > > >> AMDGPU_SDMA_IRQ_TRAP0 : > > >> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs > sdma_v2_4_ip_funcs > > = > > >> { > > >> > > >> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_SDMA, > > >> + .align_mask = 0xf, > > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > > >> .get_rptr = sdma_v2_4_ring_get_rptr, > > >> .get_wptr = sdma_v2_4_ring_get_wptr, > > >> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > >> index accf4d1..f8ec370 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > > >> @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct > > >> amdgpu_ring *ring, uint32_t count) > > >> > > >> for (i = 0; i < count; i++) > > >> if (sdma && sdma->burst_nop && (i == 0)) > > >> - amdgpu_ring_write(ring, ring->nop | > > >> + amdgpu_ring_write(ring, ring->funcs->nop | > > >> SDMA_PKT_NOP_HEADER_COUNT(count - > > 1)); > > >> else > > >> - amdgpu_ring_write(ring, ring->nop); > > >> + amdgpu_ring_write(ring, ring->funcs->nop); > > >> } > > >> > > >> /** > > >> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) > > >> > > >> sprintf(ring->name, "sdma%d", i); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - > > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > > >> &adev->sdma.trap_irq, > > >> (i == 0) ? > > >> AMDGPU_SDMA_IRQ_TRAP0 : > > >> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs > sdma_v3_0_ip_funcs > > = > > >> { > > >> > > >> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_SDMA, > > >> + .align_mask = 0xf, > > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > > >> .get_rptr = sdma_v3_0_ring_get_rptr, > > >> .get_wptr = sdma_v3_0_ring_get_wptr, > > >> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/si_dma.c > > >> b/drivers/gpu/drm/amd/amdgpu/si_dma.c > > >> index 1aee45b..7fece1f 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > > >> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > > >> ring->use_doorbell = false; > > >> sprintf(ring->name, "sdma%d", i); > > >> r = amdgpu_ring_init(adev, ring, 1024, > > >> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > > >> 0), 0xf, > > >> &adev->sdma.trap_irq, > > >> (i == 0) ? > > >> AMDGPU_SDMA_IRQ_TRAP0 : > > >> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { > > >> > > >> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_SDMA, > > >> + .align_mask = 0xf, > > >> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > > >> .get_rptr = si_dma_ring_get_rptr, > > >> .get_wptr = si_dma_ring_get_wptr, > > >> .set_wptr = si_dma_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > > >> index 55af8ac..1bab75a 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > > >> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > > >> > > >> ring = &adev->uvd.ring; > > >> sprintf(ring->name, "uvd"); > > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > > >> 0xf, > > >> - &adev->uvd.irq, 0); > > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > >> > > >> return r; > > >> } > > >> @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = > { > > >> > > >> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_UVD, > > >> + .align_mask = 0xf, > > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > > >> .get_rptr = uvd_v4_2_ring_get_rptr, > > >> .get_wptr = uvd_v4_2_ring_get_wptr, > > >> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > > >> index 21e725b..ec848fc 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > > >> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > > >> > > >> ring = &adev->uvd.ring; > > >> sprintf(ring->name, "uvd"); > > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > > >> 0xf, > > >> - &adev->uvd.irq, 0); > > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > >> > > >> return r; > > >> } > > >> @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = > { > > >> > > >> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_UVD, > > >> + .align_mask = 0xf, > > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > > >> .get_rptr = uvd_v5_0_ring_get_rptr, > > >> .get_wptr = uvd_v5_0_ring_get_wptr, > > >> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > >> index 2ce1818..15708f8 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > > >> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > > >> > > >> ring = &adev->uvd.ring; > > >> sprintf(ring->name, "uvd"); > > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), > > >> 0xf, > > >> - &adev->uvd.irq, 0); > > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); > > >> > > >> return r; > > >> } > > >> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > > >> uvd_v6_0_ring_phys_funcs = { > > >> > > >> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > > >> .type = AMDGPU_RING_TYPE_UVD, > > >> + .align_mask = 0xf, > > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > > >> .get_rptr = uvd_v6_0_ring_get_rptr, > > >> .get_wptr = uvd_v6_0_ring_get_wptr, > > >> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > > >> index cf0c68f..d585839 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > > >> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > > >> for (i = 0; i < adev->vce.num_rings; i++) { > > >> ring = &adev->vce.ring[i]; > > >> sprintf(ring->name, "vce%d", i); > > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > > >> + r = amdgpu_ring_init(adev, ring, 512, > > >> &adev->vce.irq, 0); > > >> if (r) > > >> return r; > > >> @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = > { > > >> > > >> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > > >> .type = AMDGPU_RING_TYPE_VCE, > > >> + .align_mask = 0xf, > > >> + .nop = VCE_CMD_NO_OP, > > >> .get_rptr = vce_v2_0_ring_get_rptr, > > >> .get_wptr = vce_v2_0_ring_get_wptr, > > >> .set_wptr = vce_v2_0_ring_set_wptr, diff --git > > >> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > >> index 56a3feb..f7dbd0d 100644 > > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > > >> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > > >> for (i = 0; i < adev->vce.num_rings; i++) { > > >> ring = &adev->vce.ring[i]; > > >> sprintf(ring->name, "vce%d", i); > > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, > > >> - &adev->vce.irq, 0); > > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); > > >> if (r) > > >> return r; > > >> } > > >> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > > >> vce_v3_0_ring_phys_funcs = { > > >> > > >> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { > > >> .type = AMDGPU_RING_TYPE_VCE, > > >> + .align_mask = 0xf, > > >> + .nop = VCE_CMD_NO_OP, > > >> .get_rptr = vce_v3_0_ring_get_rptr, > > >> .get_wptr = vce_v3_0_ring_get_wptr, > > >> .set_wptr = vce_v3_0_ring_set_wptr, > > >> -- > > >> 2.5.0 > > >> > > >> _______________________________________________ > > >> amd-gfx mailing list > > >> amd-gfx@lists.freedesktop.org > > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > > > > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CY4PR12MB17015B2156B539C0540A2905EBAA0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CY4PR12MB17015B2156B539C0540A2905EBAA0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-10-27 14:34 ` Alex Deucher [not found] ` <CADnq5_MS2dxbH64Q2mTv3fnqCF18bgBp7g=7EwLp9rR8Fw6tqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Alex Deucher @ 2016-10-27 14:34 UTC (permalink / raw) To: Yu, Xiangliang Cc: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org On Thu, Oct 27, 2016 at 5:55 AM, Yu, Xiangliang <Xiangliang.Yu@amd.com> wrote: > > >> > >> > NAK, we agreed upon moving the constant data into the functions >> > structure as well. >> > >> > How about renaming the amdgpu_ring_funcs structure to make clear that >> > it isn't only functions any more? Something amdgpu_ring_params or >> > something like that? > > What benefit to put the constant data into the structure? > If no, I'll create a new patch that create new structure for these constant data. The functions and the parameters should be const. I don't care how we arrange the structure(s). Feel free to re-arrange. Alex > >> Why not create a new structure for the constant data? It can make code >> more flexible. >> Actually, I'm working on SRIOV patches, I need the amdgpu_ring_funcs >> structure so That easy to inherint all of function. >> >> > >> > Regards, >> > Christian. >> > >> > Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: >> > > Hi Christian, >> > > >> > > Could you help put type, aligan_mask, nop of amdgpu_ring_funcs >> > > struct >> > field into amdgpu_ring struct? >> > > I think amdgpu_ring_funcs should include function pointer, not >> > > attribute. Your patches is not follow the struct design, and the >> > amdgpu_ring will lost the meaning. >> > > >> > > >> > > Thanks! >> > > Xiangliang Yu >> > > >> > >> -----Original Message----- >> > >> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On >> > >> Behalf Of Christian K?nig >> > >> Sent: Wednesday, October 05, 2016 10:13 PM >> > >> To: amd-gfx@lists.freedesktop.org >> > >> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring >> > >> funcs as well >> > >> >> > >> From: Christian König <christian.koenig@amd.com> >> > >> >> > >> They are constant as well. >> > >> >> > >> Signed-off-by: Christian König <christian.koenig@amd.com> >> > >> --- >> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 +++++++++-------- >> -- >> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- >> > >> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ >> > >> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- >> > >> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- >> > >> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- >> > >> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- >> > >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- >> > >> 14 files changed, 58 insertions(+), 43 deletions(-) >> > >> >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> > >> index b2df735..a141b46 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >> > >> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring *ring, >> > >> unsigned ndw) { >> > >> /* Align requested size with padding so unlock_commit can >> > >> * pad safely */ >> > >> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; >> > >> + ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask; >> > >> >> > >> /* Make sure we aren't trying to allocate more space >> > >> * than the maximum for one submission @@ -94,7 +94,7 @@ void >> > >> amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) >> > >> int i; >> > >> >> > >> for (i = 0; i < count; i++) >> > >> - amdgpu_ring_write(ring, ring->nop); >> > >> + amdgpu_ring_write(ring, ring->funcs->nop); >> > >> } >> > >> >> > >> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ >> > >> -106,8 >> > >> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, >> > >> uint32_t count) >> > >> */ >> > >> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct >> > >> amdgpu_ib *ib) { >> > >> - while (ib->length_dw & ring->align_mask) >> > >> - ib->ptr[ib->length_dw++] = ring->nop; >> > >> + while (ib->length_dw & ring->funcs->align_mask) >> > >> + ib->ptr[ib->length_dw++] = ring->funcs->nop; >> > >> } >> > >> >> > >> /** >> > >> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct amdgpu_ring >> > *ring) >> > >> uint32_t count; >> > >> >> > >> /* We pad to match fetch size */ >> > >> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); >> > >> - count %= ring->align_mask + 1; >> > >> + count = ring->funcs->align_mask + 1 - >> > >> + (ring->wptr & ring->funcs->align_mask); >> > >> + count %= ring->funcs->align_mask + 1; >> > >> ring->funcs->insert_nop(ring, count); >> > >> >> > >> mb(); >> > >> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring >> *ring) >> > >> * Returns 0 on success, error on failure. >> > >> */ >> > >> int amdgpu_ring_init(struct amdgpu_device *adev, struct >> > >> amdgpu_ring *ring, >> > >> - unsigned max_dw, u32 nop, u32 align_mask, >> > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type) >> > >> + unsigned max_dw, struct amdgpu_irq_src *irq_src, >> > >> + unsigned irq_type) >> > >> { >> > >> int r; >> > >> >> > >> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device >> > >> *adev, struct amdgpu_ring *ring, >> > >> >> > >> ring->ring_size = roundup_pow_of_two(max_dw * 4 * >> > >> amdgpu_sched_hw_submission); >> > >> - ring->align_mask = align_mask; >> > >> - ring->nop = nop; >> > >> >> > >> /* Allocate ring buffer */ >> > >> if (ring->ring_obj == NULL) { >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> > >> index 6cf89c9..1ee1b65 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >> > >> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct >> > >> amdgpu_ring *ring); >> > >> /* provided by hw blocks that expose a ring buffer for commands >> > >> */ struct amdgpu_ring_funcs { >> > >> enum amdgpu_ring_type type; >> > >> + uint32_t align_mask; >> > >> + u32 nop; >> > >> >> > >> /* ring read/write ptr handling */ >> > >> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 +151,8 @@ >> > >> struct amdgpu_ring { >> > >> unsigned max_dw; >> > >> int count_dw; >> > >> uint64_t gpu_addr; >> > >> - uint32_t align_mask; >> > >> uint32_t ptr_mask; >> > >> bool ready; >> > >> - u32 nop; >> > >> u32 idx; >> > >> u32 me; >> > >> u32 pipe; >> > >> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct >> > >> amdgpu_ring *ring, struct amdgpu_ib *ib); void >> > >> amdgpu_ring_commit(struct amdgpu_ring *ring); void >> > >> amdgpu_ring_undo(struct amdgpu_ring *ring); int >> > amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, >> > >> - unsigned ring_size, u32 nop, u32 align_mask, >> > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type); >> > >> + unsigned ring_size, struct amdgpu_irq_src *irq_src, >> > >> + unsigned irq_type); >> > >> void amdgpu_ring_fini(struct amdgpu_ring *ring); >> > >> >> > >> #endif >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> > >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> > >> index f91f02f..664f894 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >> > >> @@ -205,10 +205,10 @@ static void cik_sdma_ring_insert_nop(struct >> > >> amdgpu_ring *ring, uint32_t count) >> > >> >> > >> for (i = 0; i < count; i++) >> > >> if (sdma && sdma->burst_nop && (i == 0)) >> > >> - amdgpu_ring_write(ring, ring->nop | >> > >> + amdgpu_ring_write(ring, ring->funcs->nop | >> > >> SDMA_NOP_COUNT(count - 1)); >> > >> else >> > >> - amdgpu_ring_write(ring, ring->nop); >> > >> + amdgpu_ring_write(ring, ring->funcs->nop); >> > >> } >> > >> >> > >> /** >> > >> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) >> > >> ring->ring_obj = NULL; >> > >> sprintf(ring->name, "sdma%d", i); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, >> > >> 0), 0xf, >> > >> &adev->sdma.trap_irq, >> > >> (i == 0) ? >> > >> AMDGPU_SDMA_IRQ_TRAP0 : >> > >> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs cik_sdma_ip_funcs >> = >> > { >> > >> >> > >> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_SDMA, >> > >> + .align_mask = 0xf, >> > >> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), >> > >> .get_rptr = cik_sdma_ring_get_rptr, >> > >> .get_wptr = cik_sdma_ring_get_wptr, >> > >> .set_wptr = cik_sdma_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> > >> index 1f8687fd..367b14e 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >> > >> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) >> > >> ring->ring_obj = NULL; >> > >> sprintf(ring->name, "gfx"); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - 0x80000000, 0xff, >> > >> &adev->gfx.eop_irq, >> > >> AMDGPU_CP_IRQ_GFX_EOP); >> > >> if (r) >> > >> return r; >> > >> @@ -2892,7 +2891,6 @@ static int gfx_v6_0_sw_init(void *handle) >> > >> sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, >> > >> ring->queue); >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> > >> + ring->pipe; >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - 0x80000000, 0xff, >> > >> &adev->gfx.eop_irq, irq_type); >> > >> if (r) >> > >> return r; >> > >> @@ -3227,6 +3225,8 @@ const struct amd_ip_funcs gfx_v6_0_ip_funcs >> = >> > { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { >> > >> .type = AMDGPU_RING_TYPE_GFX, >> > >> + .align_mask = 0xff, >> > >> + .nop = 0x80000000, >> > >> .get_rptr = gfx_v6_0_ring_get_rptr, >> > >> .get_wptr = gfx_v6_0_ring_get_wptr, >> > >> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 +3252,8 @@ >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute >> = { >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, >> > >> + .align_mask = 0xff, >> > >> + .nop = 0x80000000, >> > >> .get_rptr = gfx_v6_0_ring_get_rptr, >> > >> .get_wptr = gfx_v6_0_ring_get_wptr, >> > >> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> > >> index be3881e..15f24bd 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >> > >> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) >> > >> ring->ring_obj = NULL; >> > >> sprintf(ring->name, "gfx"); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> > >> &adev->gfx.eop_irq, >> > >> AMDGPU_CP_IRQ_GFX_EOP); >> > >> if (r) >> > >> return r; >> > >> @@ -4631,7 +4630,6 @@ static int gfx_v7_0_sw_init(void *handle) >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> > >> + ring->pipe; >> > >> /* type-2 packets are deprecated on MEC, use type-3 instead >> > */ >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> > >> &adev->gfx.eop_irq, irq_type); >> > >> if (r) >> > >> return r; >> > >> @@ -5102,6 +5100,8 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs >> = >> > { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { >> > >> .type = AMDGPU_RING_TYPE_GFX, >> > >> + .align_mask = 0xff, >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> > >> .get_rptr = gfx_v7_0_ring_get_rptr, >> > >> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, >> > >> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 +5130,8 @@ >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute >> = { >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, >> > >> + .align_mask = 0xff, >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> > >> .get_rptr = gfx_v7_0_ring_get_rptr, >> > >> .get_wptr = gfx_v7_0_ring_get_wptr_compute, >> > >> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> > >> index 0d66f49..51f1139 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >> > >> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) >> > >> ring->doorbell_index = >> > >> AMDGPU_DOORBELL_GFX_RING0; >> > >> } >> > >> >> > >> - r = amdgpu_ring_init(adev, ring, 1024, >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> > >> - &adev->gfx.eop_irq, >> > >> AMDGPU_CP_IRQ_GFX_EOP); >> > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >> > >> + AMDGPU_CP_IRQ_GFX_EOP); >> > >> if (r) >> > >> return r; >> > >> } >> > >> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) >> > >> sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring- >> > >>> pipe, ring->queue); >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >> > >> + ring->pipe; >> > >> /* type-2 packets are deprecated on MEC, use type-3 instead >> > */ >> > >> - r = amdgpu_ring_init(adev, ring, 1024, >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >> > >> - &adev->gfx.eop_irq, irq_type); >> > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >> > >> + irq_type); >> > >> if (r) >> > >> return r; >> > >> } >> > >> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs >> = >> > { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { >> > >> .type = AMDGPU_RING_TYPE_GFX, >> > >> + .align_mask = 0xff, >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> > >> .get_rptr = gfx_v8_0_ring_get_rptr, >> > >> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, >> > >> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 +6562,8 @@ >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { >> > >> >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute >> = { >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, >> > >> + .align_mask = 0xff, >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >> > >> .get_rptr = gfx_v8_0_ring_get_rptr, >> > >> .get_wptr = gfx_v8_0_ring_get_wptr_compute, >> > >> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> > >> index b11a81e..49c47d6 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >> > >> @@ -236,10 +236,10 @@ static void sdma_v2_4_ring_insert_nop(struct >> > >> amdgpu_ring *ring, uint32_t count) >> > >> >> > >> for (i = 0; i < count; i++) >> > >> if (sdma && sdma->burst_nop && (i == 0)) >> > >> - amdgpu_ring_write(ring, ring->nop | >> > >> + amdgpu_ring_write(ring, ring->funcs->nop | >> > >> SDMA_PKT_NOP_HEADER_COUNT(count - >> > 1)); >> > >> else >> > >> - amdgpu_ring_write(ring, ring->nop); >> > >> + amdgpu_ring_write(ring, ring->funcs->nop); >> > >> } >> > >> >> > >> /** >> > >> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) >> > >> ring->use_doorbell = false; >> > >> sprintf(ring->name, "sdma%d", i); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - >> > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >> > >> &adev->sdma.trap_irq, >> > >> (i == 0) ? >> > >> AMDGPU_SDMA_IRQ_TRAP0 : >> > >> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs >> sdma_v2_4_ip_funcs >> > = >> > >> { >> > >> >> > >> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_SDMA, >> > >> + .align_mask = 0xf, >> > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >> > >> .get_rptr = sdma_v2_4_ring_get_rptr, >> > >> .get_wptr = sdma_v2_4_ring_get_wptr, >> > >> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> > >> index accf4d1..f8ec370 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >> > >> @@ -396,10 +396,10 @@ static void sdma_v3_0_ring_insert_nop(struct >> > >> amdgpu_ring *ring, uint32_t count) >> > >> >> > >> for (i = 0; i < count; i++) >> > >> if (sdma && sdma->burst_nop && (i == 0)) >> > >> - amdgpu_ring_write(ring, ring->nop | >> > >> + amdgpu_ring_write(ring, ring->funcs->nop | >> > >> SDMA_PKT_NOP_HEADER_COUNT(count - >> > 1)); >> > >> else >> > >> - amdgpu_ring_write(ring, ring->nop); >> > >> + amdgpu_ring_write(ring, ring->funcs->nop); >> > >> } >> > >> >> > >> /** >> > >> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) >> > >> >> > >> sprintf(ring->name, "sdma%d", i); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - >> > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >> > >> &adev->sdma.trap_irq, >> > >> (i == 0) ? >> > >> AMDGPU_SDMA_IRQ_TRAP0 : >> > >> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs >> sdma_v3_0_ip_funcs >> > = >> > >> { >> > >> >> > >> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_SDMA, >> > >> + .align_mask = 0xf, >> > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >> > >> .get_rptr = sdma_v3_0_ring_get_rptr, >> > >> .get_wptr = sdma_v3_0_ring_get_wptr, >> > >> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/si_dma.c >> > >> b/drivers/gpu/drm/amd/amdgpu/si_dma.c >> > >> index 1aee45b..7fece1f 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c >> > >> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) >> > >> ring->use_doorbell = false; >> > >> sprintf(ring->name, "sdma%d", i); >> > >> r = amdgpu_ring_init(adev, ring, 1024, >> > >> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, >> > >> 0), 0xf, >> > >> &adev->sdma.trap_irq, >> > >> (i == 0) ? >> > >> AMDGPU_SDMA_IRQ_TRAP0 : >> > >> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = { >> > >> >> > >> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_SDMA, >> > >> + .align_mask = 0xf, >> > >> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), >> > >> .get_rptr = si_dma_ring_get_rptr, >> > >> .get_wptr = si_dma_ring_get_wptr, >> > >> .set_wptr = si_dma_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> > >> index 55af8ac..1bab75a 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >> > >> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) >> > >> >> > >> ring = &adev->uvd.ring; >> > >> sprintf(ring->name, "uvd"); >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> > >> 0xf, >> > >> - &adev->uvd.irq, 0); >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> > >> >> > >> return r; >> > >> } >> > >> @@ -743,6 +742,8 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = >> { >> > >> >> > >> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_UVD, >> > >> + .align_mask = 0xf, >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> > >> .get_rptr = uvd_v4_2_ring_get_rptr, >> > >> .get_wptr = uvd_v4_2_ring_get_wptr, >> > >> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> > >> index 21e725b..ec848fc 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >> > >> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) >> > >> >> > >> ring = &adev->uvd.ring; >> > >> sprintf(ring->name, "uvd"); >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> > >> 0xf, >> > >> - &adev->uvd.irq, 0); >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> > >> >> > >> return r; >> > >> } >> > >> @@ -794,6 +793,8 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = >> { >> > >> >> > >> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_UVD, >> > >> + .align_mask = 0xf, >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> > >> .get_rptr = uvd_v5_0_ring_get_rptr, >> > >> .get_wptr = uvd_v5_0_ring_get_wptr, >> > >> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> > >> index 2ce1818..15708f8 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >> > >> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) >> > >> >> > >> ring = &adev->uvd.ring; >> > >> sprintf(ring->name, "uvd"); >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, 0), >> > >> 0xf, >> > >> - &adev->uvd.irq, 0); >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0); >> > >> >> > >> return r; >> > >> } >> > >> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs >> > >> uvd_v6_0_ring_phys_funcs = { >> > >> >> > >> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { >> > >> .type = AMDGPU_RING_TYPE_UVD, >> > >> + .align_mask = 0xf, >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), >> > >> .get_rptr = uvd_v6_0_ring_get_rptr, >> > >> .get_wptr = uvd_v6_0_ring_get_wptr, >> > >> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> > >> index cf0c68f..d585839 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >> > >> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) >> > >> for (i = 0; i < adev->vce.num_rings; i++) { >> > >> ring = &adev->vce.ring[i]; >> > >> sprintf(ring->name, "vce%d", i); >> > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, >> > >> + r = amdgpu_ring_init(adev, ring, 512, >> > >> &adev->vce.irq, 0); >> > >> if (r) >> > >> return r; >> > >> @@ -611,6 +611,8 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = >> { >> > >> >> > >> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { >> > >> .type = AMDGPU_RING_TYPE_VCE, >> > >> + .align_mask = 0xf, >> > >> + .nop = VCE_CMD_NO_OP, >> > >> .get_rptr = vce_v2_0_ring_get_rptr, >> > >> .get_wptr = vce_v2_0_ring_get_wptr, >> > >> .set_wptr = vce_v2_0_ring_set_wptr, diff --git >> > >> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> > >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> > >> index 56a3feb..f7dbd0d 100644 >> > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >> > >> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) >> > >> for (i = 0; i < adev->vce.num_rings; i++) { >> > >> ring = &adev->vce.ring[i]; >> > >> sprintf(ring->name, "vce%d", i); >> > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, 0xf, >> > >> - &adev->vce.irq, 0); >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0); >> > >> if (r) >> > >> return r; >> > >> } >> > >> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs >> > >> vce_v3_0_ring_phys_funcs = { >> > >> >> > >> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { >> > >> .type = AMDGPU_RING_TYPE_VCE, >> > >> + .align_mask = 0xf, >> > >> + .nop = VCE_CMD_NO_OP, >> > >> .get_rptr = vce_v3_0_ring_get_rptr, >> > >> .get_wptr = vce_v3_0_ring_get_wptr, >> > >> .set_wptr = vce_v3_0_ring_set_wptr, >> > >> -- >> > >> 2.5.0 >> > >> >> > >> _______________________________________________ >> > >> amd-gfx mailing list >> > >> amd-gfx@lists.freedesktop.org >> > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> > >> > >> > _______________________________________________ >> > amd-gfx mailing list >> > amd-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CADnq5_MS2dxbH64Q2mTv3fnqCF18bgBp7g=7EwLp9rR8Fw6tqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CADnq5_MS2dxbH64Q2mTv3fnqCF18bgBp7g=7EwLp9rR8Fw6tqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2016-10-28 2:06 ` Yu, Xiangliang [not found] ` <CY4PR12MB1701B0BCB6F6BE8F5281B1C0EBAD0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Yu, Xiangliang @ 2016-10-28 2:06 UTC (permalink / raw) To: Alex Deucher Cc: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > >> > NAK, we agreed upon moving the constant data into the functions > >> > structure as well. > >> > > >> > How about renaming the amdgpu_ring_funcs structure to make clear > >> > that it isn't only functions any more? Something amdgpu_ring_params > >> > or something like that? > > > > What benefit to put the constant data into the structure? > > If no, I'll create a new patch that create new structure for these constant > data. > > The functions and the parameters should be const. I don't care how we > arrange the structure(s). Feel free to re-arrange. Yes, I know. I'll replace the pointer address of function structure not the member's content. I think this is best choice for making SRIOV code independent and easy to maintain. > > > >> Why not create a new structure for the constant data? It can make > >> code more flexible. > >> Actually, I'm working on SRIOV patches, I need the amdgpu_ring_funcs > >> structure so That easy to inherint all of function. > >> > >> > > >> > Regards, > >> > Christian. > >> > > >> > Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: > >> > > Hi Christian, > >> > > > >> > > Could you help put type, aligan_mask, nop of amdgpu_ring_funcs > >> > > struct > >> > field into amdgpu_ring struct? > >> > > I think amdgpu_ring_funcs should include function pointer, not > >> > > attribute. Your patches is not follow the struct design, and the > >> > amdgpu_ring will lost the meaning. > >> > > > >> > > > >> > > Thanks! > >> > > Xiangliang Yu > >> > > > >> > >> -----Original Message----- > >> > >> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On > >> > >> Behalf Of Christian K?nig > >> > >> Sent: Wednesday, October 05, 2016 10:13 PM > >> > >> To: amd-gfx@lists.freedesktop.org > >> > >> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into > >> > >> ring funcs as well > >> > >> > >> > >> From: Christian König <christian.koenig@amd.com> > >> > >> > >> > >> They are constant as well. > >> > >> > >> > >> Signed-off-by: Christian König <christian.koenig@amd.com> > >> > >> --- > >> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 > >> > >> +++++++++-------- > >> -- > >> > >> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > >> > >> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > >> > >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > >> > >> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > >> > >> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > >> > >> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > >> > >> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > >> > >> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > >> > >> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > >> > >> 14 files changed, 58 insertions(+), 43 deletions(-) > >> > >> > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> > >> index b2df735..a141b46 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >> > >> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring > >> > >> *ring, unsigned ndw) { > >> > >> /* Align requested size with padding so unlock_commit can > >> > >> * pad safely */ > >> > >> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > >> > >> + ndw = (ndw + ring->funcs->align_mask) & > >> > >> + ~ring->funcs->align_mask; > >> > >> > >> > >> /* Make sure we aren't trying to allocate more space > >> > >> * than the maximum for one submission @@ -94,7 +94,7 > >> > >> @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > uint32_t count) > >> > >> int i; > >> > >> > >> > >> for (i = 0; i < count; i++) > >> > >> - amdgpu_ring_write(ring, ring->nop); > >> > >> + amdgpu_ring_write(ring, ring->funcs->nop); > >> > >> } > >> > >> > >> > >> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ > >> > >> -106,8 > >> > >> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > >> > >> uint32_t count) > >> > >> */ > >> > >> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, > >> > >> struct amdgpu_ib *ib) { > >> > >> - while (ib->length_dw & ring->align_mask) > >> > >> - ib->ptr[ib->length_dw++] = ring->nop; > >> > >> + while (ib->length_dw & ring->funcs->align_mask) > >> > >> + ib->ptr[ib->length_dw++] = ring->funcs->nop; > >> > >> } > >> > >> > >> > >> /** > >> > >> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct > amdgpu_ring > >> > *ring) > >> > >> uint32_t count; > >> > >> > >> > >> /* We pad to match fetch size */ > >> > >> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > >> > >> - count %= ring->align_mask + 1; > >> > >> + count = ring->funcs->align_mask + 1 - > >> > >> + (ring->wptr & ring->funcs->align_mask); > >> > >> + count %= ring->funcs->align_mask + 1; > >> > >> ring->funcs->insert_nop(ring, count); > >> > >> > >> > >> mb(); > >> > >> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring > >> *ring) > >> > >> * Returns 0 on success, error on failure. > >> > >> */ > >> > >> int amdgpu_ring_init(struct amdgpu_device *adev, struct > >> > >> amdgpu_ring *ring, > >> > >> - unsigned max_dw, u32 nop, u32 align_mask, > >> > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type) > >> > >> + unsigned max_dw, struct amdgpu_irq_src *irq_src, > >> > >> + unsigned irq_type) > >> > >> { > >> > >> int r; > >> > >> > >> > >> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device > >> > >> *adev, struct amdgpu_ring *ring, > >> > >> > >> > >> ring->ring_size = roundup_pow_of_two(max_dw * 4 * > >> > >> amdgpu_sched_hw_submission); > >> > >> - ring->align_mask = align_mask; > >> > >> - ring->nop = nop; > >> > >> > >> > >> /* Allocate ring buffer */ > >> > >> if (ring->ring_obj == NULL) { diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> > >> index 6cf89c9..1ee1b65 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >> > >> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct > >> > >> amdgpu_ring *ring); > >> > >> /* provided by hw blocks that expose a ring buffer for > >> > >> commands */ struct amdgpu_ring_funcs { > >> > >> enum amdgpu_ring_type type; > >> > >> + uint32_t align_mask; > >> > >> + u32 nop; > >> > >> > >> > >> /* ring read/write ptr handling */ > >> > >> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 > >> > >> +151,8 @@ struct amdgpu_ring { > >> > >> unsigned max_dw; > >> > >> int count_dw; > >> > >> uint64_t gpu_addr; > >> > >> - uint32_t align_mask; > >> > >> uint32_t ptr_mask; > >> > >> bool ready; > >> > >> - u32 nop; > >> > >> u32 idx; > >> > >> u32 me; > >> > >> u32 pipe; > >> > >> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > >> > >> amdgpu_ring *ring, struct amdgpu_ib *ib); void > >> > >> amdgpu_ring_commit(struct amdgpu_ring *ring); void > >> > >> amdgpu_ring_undo(struct amdgpu_ring *ring); int > >> > amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > >> > *ring, > >> > >> - unsigned ring_size, u32 nop, u32 align_mask, > >> > >> - struct amdgpu_irq_src *irq_src, unsigned irq_type); > >> > >> + unsigned ring_size, struct amdgpu_irq_src *irq_src, > >> > >> + unsigned irq_type); > >> > >> void amdgpu_ring_fini(struct amdgpu_ring *ring); > >> > >> > >> > >> #endif > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> > >> index f91f02f..664f894 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >> > >> @@ -205,10 +205,10 @@ static void > >> > >> cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >> > >> count) > >> > >> > >> > >> for (i = 0; i < count; i++) > >> > >> if (sdma && sdma->burst_nop && (i == 0)) > >> > >> - amdgpu_ring_write(ring, ring->nop | > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop | > >> > >> SDMA_NOP_COUNT(count - 1)); > >> > >> else > >> > >> - amdgpu_ring_write(ring, ring->nop); > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop); > >> > >> } > >> > >> > >> > >> /** > >> > >> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > >> > >> ring->ring_obj = NULL; > >> > >> sprintf(ring->name, "sdma%d", i); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > >> > >> 0), 0xf, > >> > >> &adev->sdma.trap_irq, > >> > >> (i == 0) ? > >> > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> > >> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs > >> > >> cik_sdma_ip_funcs > >> = > >> > { > >> > >> > >> > >> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_SDMA, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > >> > >> .get_rptr = cik_sdma_ring_get_rptr, > >> > >> .get_wptr = cik_sdma_ring_get_wptr, > >> > >> .set_wptr = cik_sdma_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> > >> index 1f8687fd..367b14e 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >> > >> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > >> > >> ring->ring_obj = NULL; > >> > >> sprintf(ring->name, "gfx"); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - 0x80000000, 0xff, > >> > >> &adev->gfx.eop_irq, > >> > >> AMDGPU_CP_IRQ_GFX_EOP); > >> > >> if (r) > >> > >> return r; @@ -2892,7 +2891,6 @@ static > >> > >> int gfx_v6_0_sw_init(void *handle) > >> > >> sprintf(ring->name, "comp %d.%d.%d", ring->me, > >> > >> ring->pipe, > >> > >> ring->queue); > >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> > >> + ring->pipe; > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - 0x80000000, 0xff, > >> > >> &adev->gfx.eop_irq, irq_type); > >> > >> if (r) > >> > >> return r; @@ -3227,6 +3225,8 @@ const > >> > >> struct amd_ip_funcs gfx_v6_0_ip_funcs > >> = > >> > { > >> > >> > >> > >> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { > >> > >> .type = AMDGPU_RING_TYPE_GFX, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = 0x80000000, > >> > >> .get_rptr = gfx_v6_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v6_0_ring_get_wptr, > >> > >> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 > >> > >> +3252,8 @@ static const struct amdgpu_ring_funcs > >> > >> gfx_v6_0_ring_funcs_gfx = { > >> > >> > >> > >> static const struct amdgpu_ring_funcs > >> > >> gfx_v6_0_ring_funcs_compute > >> = { > >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = 0x80000000, > >> > >> .get_rptr = gfx_v6_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v6_0_ring_get_wptr, > >> > >> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> > >> index be3881e..15f24bd 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >> > >> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > >> > >> ring->ring_obj = NULL; > >> > >> sprintf(ring->name, "gfx"); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> > >> &adev->gfx.eop_irq, > >> > >> AMDGPU_CP_IRQ_GFX_EOP); > >> > >> if (r) > >> > >> return r; @@ -4631,7 +4630,6 @@ static > >> > >> int gfx_v7_0_sw_init(void *handle) > >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> > >> + ring->pipe; > >> > >> /* type-2 packets are deprecated on MEC, use > >> > >> type-3 instead > >> > */ > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> > >> &adev->gfx.eop_irq, irq_type); > >> > >> if (r) > >> > >> return r; @@ -5102,6 +5100,8 @@ const > >> > >> struct amd_ip_funcs gfx_v7_0_ip_funcs > >> = > >> > { > >> > >> > >> > >> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { > >> > >> .type = AMDGPU_RING_TYPE_GFX, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> > >> .get_rptr = gfx_v7_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > >> > >> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 > >> > >> +5130,8 @@ static const struct amdgpu_ring_funcs > >> > >> gfx_v7_0_ring_funcs_gfx = { > >> > >> > >> > >> static const struct amdgpu_ring_funcs > >> > >> gfx_v7_0_ring_funcs_compute > >> = { > >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> > >> .get_rptr = gfx_v7_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v7_0_ring_get_wptr_compute, > >> > >> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> > >> index 0d66f49..51f1139 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> > >> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > >> > >> ring->doorbell_index = > >> > >> AMDGPU_DOORBELL_GFX_RING0; > >> > >> } > >> > >> > >> > >> - r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> > >> - &adev->gfx.eop_irq, > >> > >> AMDGPU_CP_IRQ_GFX_EOP); > >> > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > >> > >> + AMDGPU_CP_IRQ_GFX_EOP); > >> > >> if (r) > >> > >> return r; > >> > >> } > >> > >> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > >> > >> sprintf(ring->name, "comp_%d.%d.%d", ring->me, > >> > >> ring- > >> > >>> pipe, ring->queue); > >> > >> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >> > >> + ring->pipe; > >> > >> /* type-2 packets are deprecated on MEC, use > >> > >> type-3 instead > >> > */ > >> > >> - r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >> > >> - &adev->gfx.eop_irq, irq_type); > >> > >> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, > >> > >> + irq_type); > >> > >> if (r) > >> > >> return r; > >> > >> } > >> > >> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs > >> > >> gfx_v8_0_ip_funcs > >> = > >> > { > >> > >> > >> > >> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { > >> > >> .type = AMDGPU_RING_TYPE_GFX, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> > >> .get_rptr = gfx_v8_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > >> > >> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 > >> > >> +6562,8 @@ static const struct amdgpu_ring_funcs > >> > >> gfx_v8_0_ring_funcs_gfx = { > >> > >> > >> > >> static const struct amdgpu_ring_funcs > >> > >> gfx_v8_0_ring_funcs_compute > >> = { > >> > >> .type = AMDGPU_RING_TYPE_COMPUTE, > >> > >> + .align_mask = 0xff, > >> > >> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >> > >> .get_rptr = gfx_v8_0_ring_get_rptr, > >> > >> .get_wptr = gfx_v8_0_ring_get_wptr_compute, > >> > >> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> > >> index b11a81e..49c47d6 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >> > >> @@ -236,10 +236,10 @@ static void > >> > >> sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >> > >> count) > >> > >> > >> > >> for (i = 0; i < count; i++) > >> > >> if (sdma && sdma->burst_nop && (i == 0)) > >> > >> - amdgpu_ring_write(ring, ring->nop | > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop | > >> > >> SDMA_PKT_NOP_HEADER_COUNT(count > >> > >> - > >> > 1)); > >> > >> else > >> > >> - amdgpu_ring_write(ring, ring->nop); > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop); > >> > >> } > >> > >> > >> > >> /** > >> > >> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > >> > >> ring->use_doorbell = false; > >> > >> sprintf(ring->name, "sdma%d", i); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - > >> > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >> > >> &adev->sdma.trap_irq, > >> > >> (i == 0) ? > >> > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> > >> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs > >> sdma_v2_4_ip_funcs > >> > = > >> > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_SDMA, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >> > >> .get_rptr = sdma_v2_4_ring_get_rptr, > >> > >> .get_wptr = sdma_v2_4_ring_get_wptr, > >> > >> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> > >> index accf4d1..f8ec370 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >> > >> @@ -396,10 +396,10 @@ static void > >> > >> sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >> > >> count) > >> > >> > >> > >> for (i = 0; i < count; i++) > >> > >> if (sdma && sdma->burst_nop && (i == 0)) > >> > >> - amdgpu_ring_write(ring, ring->nop | > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop | > >> > >> SDMA_PKT_NOP_HEADER_COUNT(count > >> > >> - > >> > 1)); > >> > >> else > >> > >> - amdgpu_ring_write(ring, ring->nop); > >> > >> + amdgpu_ring_write(ring, > >> > >> + ring->funcs->nop); > >> > >> } > >> > >> > >> > >> /** > >> > >> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) > >> > >> > >> > >> sprintf(ring->name, "sdma%d", i); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - > >> > >> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >> > >> &adev->sdma.trap_irq, > >> > >> (i == 0) ? > >> > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> > >> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs > >> sdma_v3_0_ip_funcs > >> > = > >> > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_SDMA, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >> > >> .get_rptr = sdma_v3_0_ring_get_rptr, > >> > >> .get_wptr = sdma_v3_0_ring_get_wptr, > >> > >> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> > >> index 1aee45b..7fece1f 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >> > >> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > >> > >> ring->use_doorbell = false; > >> > >> sprintf(ring->name, "sdma%d", i); > >> > >> r = amdgpu_ring_init(adev, ring, 1024, > >> > >> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > >> > >> 0), 0xf, > >> > >> &adev->sdma.trap_irq, > >> > >> (i == 0) ? > >> > >> AMDGPU_SDMA_IRQ_TRAP0 : > >> > >> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = > >> > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_SDMA, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > >> > >> .get_rptr = si_dma_ring_get_rptr, > >> > >> .get_wptr = si_dma_ring_get_wptr, > >> > >> .set_wptr = si_dma_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> > >> index 55af8ac..1bab75a 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >> > >> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > >> > >> > >> > >> ring = &adev->uvd.ring; > >> > >> sprintf(ring->name, "uvd"); > >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, > 0), > >> > >> 0xf, > >> > >> - &adev->uvd.irq, 0); > >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >> > >> + 0); > >> > >> > >> > >> return r; > >> > >> } > >> > >> @@ -743,6 +742,8 @@ const struct amd_ip_funcs > uvd_v4_2_ip_funcs > >> > >> = > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_UVD, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> > >> .get_rptr = uvd_v4_2_ring_get_rptr, > >> > >> .get_wptr = uvd_v4_2_ring_get_wptr, > >> > >> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> > >> index 21e725b..ec848fc 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >> > >> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > >> > >> > >> > >> ring = &adev->uvd.ring; > >> > >> sprintf(ring->name, "uvd"); > >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, > 0), > >> > >> 0xf, > >> > >> - &adev->uvd.irq, 0); > >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >> > >> + 0); > >> > >> > >> > >> return r; > >> > >> } > >> > >> @@ -794,6 +793,8 @@ const struct amd_ip_funcs > uvd_v5_0_ip_funcs > >> > >> = > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_UVD, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> > >> .get_rptr = uvd_v5_0_ring_get_rptr, > >> > >> .get_wptr = uvd_v5_0_ring_get_wptr, > >> > >> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> > >> index 2ce1818..15708f8 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >> > >> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > >> > >> > >> > >> ring = &adev->uvd.ring; > >> > >> sprintf(ring->name, "uvd"); > >> > >> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, > 0), > >> > >> 0xf, > >> > >> - &adev->uvd.irq, 0); > >> > >> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >> > >> + 0); > >> > >> > >> > >> return r; > >> > >> } > >> > >> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > >> > >> uvd_v6_0_ring_phys_funcs = { > >> > >> > >> > >> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_UVD, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = PACKET0(mmUVD_NO_OP, 0), > >> > >> .get_rptr = uvd_v6_0_ring_get_rptr, > >> > >> .get_wptr = uvd_v6_0_ring_get_wptr, > >> > >> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> > >> index cf0c68f..d585839 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >> > >> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > >> > >> for (i = 0; i < adev->vce.num_rings; i++) { > >> > >> ring = &adev->vce.ring[i]; > >> > >> sprintf(ring->name, "vce%d", i); > >> > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, > 0xf, > >> > >> + r = amdgpu_ring_init(adev, ring, 512, > >> > >> &adev->vce.irq, 0); > >> > >> if (r) > >> > >> return r; @@ -611,6 +611,8 @@ const > >> > >> struct amd_ip_funcs vce_v2_0_ip_funcs = > >> { > >> > >> > >> > >> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_VCE, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = VCE_CMD_NO_OP, > >> > >> .get_rptr = vce_v2_0_ring_get_rptr, > >> > >> .get_wptr = vce_v2_0_ring_get_wptr, > >> > >> .set_wptr = vce_v2_0_ring_set_wptr, diff --git > >> > >> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> > >> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> > >> index 56a3feb..f7dbd0d 100644 > >> > >> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> > >> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >> > >> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > >> > >> for (i = 0; i < adev->vce.num_rings; i++) { > >> > >> ring = &adev->vce.ring[i]; > >> > >> sprintf(ring->name, "vce%d", i); > >> > >> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, > 0xf, > >> > >> - &adev->vce.irq, 0); > >> > >> + r = amdgpu_ring_init(adev, ring, 512, > >> > >> + &adev->vce.irq, 0); > >> > >> if (r) > >> > >> return r; > >> > >> } > >> > >> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > >> > >> vce_v3_0_ring_phys_funcs = { > >> > >> > >> > >> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { > >> > >> .type = AMDGPU_RING_TYPE_VCE, > >> > >> + .align_mask = 0xf, > >> > >> + .nop = VCE_CMD_NO_OP, > >> > >> .get_rptr = vce_v3_0_ring_get_rptr, > >> > >> .get_wptr = vce_v3_0_ring_get_wptr, > >> > >> .set_wptr = vce_v3_0_ring_set_wptr, > >> > >> -- > >> > >> 2.5.0 > >> > >> > >> > >> _______________________________________________ > >> > >> amd-gfx mailing list > >> > >> amd-gfx@lists.freedesktop.org > >> > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >> > > >> > > >> > _______________________________________________ > >> > amd-gfx mailing list > >> > amd-gfx@lists.freedesktop.org > >> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >> _______________________________________________ > >> amd-gfx mailing list > >> amd-gfx@lists.freedesktop.org > >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <CY4PR12MB1701B0BCB6F6BE8F5281B1C0EBAD0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>]
* Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <CY4PR12MB1701B0BCB6F6BE8F5281B1C0EBAD0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org> @ 2016-10-28 10:12 ` Christian König [not found] ` <dac6c3b7-6b15-7b0e-b9b0-a9bf5ad01832-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 22+ messages in thread From: Christian König @ 2016-10-28 10:12 UTC (permalink / raw) To: Yu, Xiangliang, Alex Deucher Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Am 28.10.2016 um 04:06 schrieb Yu, Xiangliang: >>>>> NAK, we agreed upon moving the constant data into the functions >>>>> structure as well. >>>>> >>>>> How about renaming the amdgpu_ring_funcs structure to make clear >>>>> that it isn't only functions any more? Something amdgpu_ring_params >>>>> or something like that? >>> What benefit to put the constant data into the structure? >>> If no, I'll create a new patch that create new structure for these constant >> data. >> >> The functions and the parameters should be const. I don't care how we >> arrange the structure(s). Feel free to re-arrange. > Yes, I know. I'll replace the pointer address of function structure not the member's content. > I think this is best choice for making SRIOV code independent and easy to maintain. I'm actually not sure if it is a good idea to make the SRIOV code independent, but anyway I clearly don't see the advantage of putting the constant members into a separate structure even with SRIOV. On the other hand as Alex said feel free to rearrange the members in the structure or rename the structure to better match it's purpose. Regards, Christian. > >>>> Why not create a new structure for the constant data? It can make >>>> code more flexible. >>>> Actually, I'm working on SRIOV patches, I need the amdgpu_ring_funcs >>>> structure so That easy to inherint all of function. >>>> >>>>> Regards, >>>>> Christian. >>>>> >>>>> Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: >>>>>> Hi Christian, >>>>>> >>>>>> Could you help put type, aligan_mask, nop of amdgpu_ring_funcs >>>>>> struct >>>>> field into amdgpu_ring struct? >>>>>> I think amdgpu_ring_funcs should include function pointer, not >>>>>> attribute. Your patches is not follow the struct design, and the >>>>> amdgpu_ring will lost the meaning. >>>>>> >>>>>> Thanks! >>>>>> Xiangliang Yu >>>>>> >>>>>>> -----Original Message----- >>>>>>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On >>>>>>> Behalf Of Christian K?nig >>>>>>> Sent: Wednesday, October 05, 2016 10:13 PM >>>>>>> To: amd-gfx@lists.freedesktop.org >>>>>>> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into >>>>>>> ring funcs as well >>>>>>> >>>>>>> From: Christian König <christian.koenig@amd.com> >>>>>>> >>>>>>> They are constant as well. >>>>>>> >>>>>>> Signed-off-by: Christian König <christian.koenig@amd.com> >>>>>>> --- >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 >>>>>>> +++++++++-------- >>>> -- >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- >>>>>>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ >>>>>>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- >>>>>>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- >>>>>>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- >>>>>>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- >>>>>>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- >>>>>>> 14 files changed, 58 insertions(+), 43 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >>>>>>> index b2df735..a141b46 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c >>>>>>> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring >>>>>>> *ring, unsigned ndw) { >>>>>>> /* Align requested size with padding so unlock_commit can >>>>>>> * pad safely */ >>>>>>> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; >>>>>>> + ndw = (ndw + ring->funcs->align_mask) & >>>>>>> + ~ring->funcs->align_mask; >>>>>>> >>>>>>> /* Make sure we aren't trying to allocate more space >>>>>>> * than the maximum for one submission @@ -94,7 +94,7 >>>>>>> @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, >> uint32_t count) >>>>>>> int i; >>>>>>> >>>>>>> for (i = 0; i < count; i++) >>>>>>> - amdgpu_ring_write(ring, ring->nop); >>>>>>> + amdgpu_ring_write(ring, ring->funcs->nop); >>>>>>> } >>>>>>> >>>>>>> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ >>>>>>> -106,8 >>>>>>> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, >>>>>>> uint32_t count) >>>>>>> */ >>>>>>> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, >>>>>>> struct amdgpu_ib *ib) { >>>>>>> - while (ib->length_dw & ring->align_mask) >>>>>>> - ib->ptr[ib->length_dw++] = ring->nop; >>>>>>> + while (ib->length_dw & ring->funcs->align_mask) >>>>>>> + ib->ptr[ib->length_dw++] = ring->funcs->nop; >>>>>>> } >>>>>>> >>>>>>> /** >>>>>>> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct >> amdgpu_ring >>>>> *ring) >>>>>>> uint32_t count; >>>>>>> >>>>>>> /* We pad to match fetch size */ >>>>>>> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); >>>>>>> - count %= ring->align_mask + 1; >>>>>>> + count = ring->funcs->align_mask + 1 - >>>>>>> + (ring->wptr & ring->funcs->align_mask); >>>>>>> + count %= ring->funcs->align_mask + 1; >>>>>>> ring->funcs->insert_nop(ring, count); >>>>>>> >>>>>>> mb(); >>>>>>> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct amdgpu_ring >>>> *ring) >>>>>>> * Returns 0 on success, error on failure. >>>>>>> */ >>>>>>> int amdgpu_ring_init(struct amdgpu_device *adev, struct >>>>>>> amdgpu_ring *ring, >>>>>>> - unsigned max_dw, u32 nop, u32 align_mask, >>>>>>> - struct amdgpu_irq_src *irq_src, unsigned irq_type) >>>>>>> + unsigned max_dw, struct amdgpu_irq_src *irq_src, >>>>>>> + unsigned irq_type) >>>>>>> { >>>>>>> int r; >>>>>>> >>>>>>> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device >>>>>>> *adev, struct amdgpu_ring *ring, >>>>>>> >>>>>>> ring->ring_size = roundup_pow_of_two(max_dw * 4 * >>>>>>> amdgpu_sched_hw_submission); >>>>>>> - ring->align_mask = align_mask; >>>>>>> - ring->nop = nop; >>>>>>> >>>>>>> /* Allocate ring buffer */ >>>>>>> if (ring->ring_obj == NULL) { diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>> index 6cf89c9..1ee1b65 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h >>>>>>> @@ -93,6 +93,8 @@ unsigned amdgpu_fence_count_emitted(struct >>>>>>> amdgpu_ring *ring); >>>>>>> /* provided by hw blocks that expose a ring buffer for >>>>>>> commands */ struct amdgpu_ring_funcs { >>>>>>> enum amdgpu_ring_type type; >>>>>>> + uint32_t align_mask; >>>>>>> + u32 nop; >>>>>>> >>>>>>> /* ring read/write ptr handling */ >>>>>>> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 >>>>>>> +151,8 @@ struct amdgpu_ring { >>>>>>> unsigned max_dw; >>>>>>> int count_dw; >>>>>>> uint64_t gpu_addr; >>>>>>> - uint32_t align_mask; >>>>>>> uint32_t ptr_mask; >>>>>>> bool ready; >>>>>>> - u32 nop; >>>>>>> u32 idx; >>>>>>> u32 me; >>>>>>> u32 pipe; >>>>>>> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct >>>>>>> amdgpu_ring *ring, struct amdgpu_ib *ib); void >>>>>>> amdgpu_ring_commit(struct amdgpu_ring *ring); void >>>>>>> amdgpu_ring_undo(struct amdgpu_ring *ring); int >>>>> amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring >>>>> *ring, >>>>>>> - unsigned ring_size, u32 nop, u32 align_mask, >>>>>>> - struct amdgpu_irq_src *irq_src, unsigned irq_type); >>>>>>> + unsigned ring_size, struct amdgpu_irq_src *irq_src, >>>>>>> + unsigned irq_type); >>>>>>> void amdgpu_ring_fini(struct amdgpu_ring *ring); >>>>>>> >>>>>>> #endif >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >>>>>>> index f91f02f..664f894 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c >>>>>>> @@ -205,10 +205,10 @@ static void >>>>>>> cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t >>>>>>> count) >>>>>>> >>>>>>> for (i = 0; i < count; i++) >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) >>>>>>> - amdgpu_ring_write(ring, ring->nop | >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop | >>>>>>> SDMA_NOP_COUNT(count - 1)); >>>>>>> else >>>>>>> - amdgpu_ring_write(ring, ring->nop); >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop); >>>>>>> } >>>>>>> >>>>>>> /** >>>>>>> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) >>>>>>> ring->ring_obj = NULL; >>>>>>> sprintf(ring->name, "sdma%d", i); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, >>>>>>> 0), 0xf, >>>>>>> &adev->sdma.trap_irq, >>>>>>> (i == 0) ? >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : >>>>>>> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs >>>>>>> cik_sdma_ip_funcs >>>> = >>>>> { >>>>>>> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), >>>>>>> .get_rptr = cik_sdma_ring_get_rptr, >>>>>>> .get_wptr = cik_sdma_ring_get_wptr, >>>>>>> .set_wptr = cik_sdma_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>>>> index 1f8687fd..367b14e 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c >>>>>>> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) >>>>>>> ring->ring_obj = NULL; >>>>>>> sprintf(ring->name, "gfx"); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - 0x80000000, 0xff, >>>>>>> &adev->gfx.eop_irq, >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); >>>>>>> if (r) >>>>>>> return r; @@ -2892,7 +2891,6 @@ static >>>>>>> int gfx_v6_0_sw_init(void *handle) >>>>>>> sprintf(ring->name, "comp %d.%d.%d", ring->me, >>>>>>> ring->pipe, >>>>>>> ring->queue); >>>>>>> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >>>>>>> + ring->pipe; >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - 0x80000000, 0xff, >>>>>>> &adev->gfx.eop_irq, irq_type); >>>>>>> if (r) >>>>>>> return r; @@ -3227,6 +3225,8 @@ const >>>>>>> struct amd_ip_funcs gfx_v6_0_ip_funcs >>>> = >>>>> { >>>>>>> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = { >>>>>>> .type = AMDGPU_RING_TYPE_GFX, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = 0x80000000, >>>>>>> .get_rptr = gfx_v6_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v6_0_ring_get_wptr, >>>>>>> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 >>>>>>> +3252,8 @@ static const struct amdgpu_ring_funcs >>>>>>> gfx_v6_0_ring_funcs_gfx = { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs >>>>>>> gfx_v6_0_ring_funcs_compute >>>> = { >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = 0x80000000, >>>>>>> .get_rptr = gfx_v6_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v6_0_ring_get_wptr, >>>>>>> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>>>> index be3881e..15f24bd 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c >>>>>>> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) >>>>>>> ring->ring_obj = NULL; >>>>>>> sprintf(ring->name, "gfx"); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >>>>>>> &adev->gfx.eop_irq, >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); >>>>>>> if (r) >>>>>>> return r; @@ -4631,7 +4630,6 @@ static >>>>>>> int gfx_v7_0_sw_init(void *handle) >>>>>>> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >>>>>>> + ring->pipe; >>>>>>> /* type-2 packets are deprecated on MEC, use >>>>>>> type-3 instead >>>>> */ >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >>>>>>> &adev->gfx.eop_irq, irq_type); >>>>>>> if (r) >>>>>>> return r; @@ -5102,6 +5100,8 @@ const >>>>>>> struct amd_ip_funcs gfx_v7_0_ip_funcs >>>> = >>>>> { >>>>>>> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { >>>>>>> .type = AMDGPU_RING_TYPE_GFX, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >>>>>>> .get_rptr = gfx_v7_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, >>>>>>> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 >>>>>>> +5130,8 @@ static const struct amdgpu_ring_funcs >>>>>>> gfx_v7_0_ring_funcs_gfx = { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs >>>>>>> gfx_v7_0_ring_funcs_compute >>>> = { >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >>>>>>> .get_rptr = gfx_v7_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v7_0_ring_get_wptr_compute, >>>>>>> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>>>> index 0d66f49..51f1139 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c >>>>>>> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) >>>>>>> ring->doorbell_index = >>>>>>> AMDGPU_DOORBELL_GFX_RING0; >>>>>>> } >>>>>>> >>>>>>> - r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >>>>>>> - &adev->gfx.eop_irq, >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); >>>>>>> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >>>>>>> + AMDGPU_CP_IRQ_GFX_EOP); >>>>>>> if (r) >>>>>>> return r; >>>>>>> } >>>>>>> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) >>>>>>> sprintf(ring->name, "comp_%d.%d.%d", ring->me, >>>>>>> ring- >>>>>>>> pipe, ring->queue); >>>>>>> irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP >>>>>>> + ring->pipe; >>>>>>> /* type-2 packets are deprecated on MEC, use >>>>>>> type-3 instead >>>>> */ >>>>>>> - r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, >>>>>>> - &adev->gfx.eop_irq, irq_type); >>>>>>> + r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, >>>>>>> + irq_type); >>>>>>> if (r) >>>>>>> return r; >>>>>>> } >>>>>>> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs >>>>>>> gfx_v8_0_ip_funcs >>>> = >>>>> { >>>>>>> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { >>>>>>> .type = AMDGPU_RING_TYPE_GFX, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >>>>>>> .get_rptr = gfx_v8_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, >>>>>>> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 >>>>>>> +6562,8 @@ static const struct amdgpu_ring_funcs >>>>>>> gfx_v8_0_ring_funcs_gfx = { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs >>>>>>> gfx_v8_0_ring_funcs_compute >>>> = { >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, >>>>>>> + .align_mask = 0xff, >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), >>>>>>> .get_rptr = gfx_v8_0_ring_get_rptr, >>>>>>> .get_wptr = gfx_v8_0_ring_get_wptr_compute, >>>>>>> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >>>>>>> index b11a81e..49c47d6 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c >>>>>>> @@ -236,10 +236,10 @@ static void >>>>>>> sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t >>>>>>> count) >>>>>>> >>>>>>> for (i = 0; i < count; i++) >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) >>>>>>> - amdgpu_ring_write(ring, ring->nop | >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop | >>>>>>> SDMA_PKT_NOP_HEADER_COUNT(count >>>>>>> - >>>>> 1)); >>>>>>> else >>>>>>> - amdgpu_ring_write(ring, ring->nop); >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop); >>>>>>> } >>>>>>> >>>>>>> /** >>>>>>> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) >>>>>>> ring->use_doorbell = false; >>>>>>> sprintf(ring->name, "sdma%d", i); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - >>>>>>> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >>>>>>> &adev->sdma.trap_irq, >>>>>>> (i == 0) ? >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : >>>>>>> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs >>>> sdma_v2_4_ip_funcs >>>>> = >>>>>>> { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >>>>>>> .get_rptr = sdma_v2_4_ring_get_rptr, >>>>>>> .get_wptr = sdma_v2_4_ring_get_wptr, >>>>>>> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >>>>>>> index accf4d1..f8ec370 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >>>>>>> @@ -396,10 +396,10 @@ static void >>>>>>> sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t >>>>>>> count) >>>>>>> >>>>>>> for (i = 0; i < count; i++) >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) >>>>>>> - amdgpu_ring_write(ring, ring->nop | >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop | >>>>>>> SDMA_PKT_NOP_HEADER_COUNT(count >>>>>>> - >>>>> 1)); >>>>>>> else >>>>>>> - amdgpu_ring_write(ring, ring->nop); >>>>>>> + amdgpu_ring_write(ring, >>>>>>> + ring->funcs->nop); >>>>>>> } >>>>>>> >>>>>>> /** >>>>>>> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void *handle) >>>>>>> >>>>>>> sprintf(ring->name, "sdma%d", i); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - >>>>>>> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, >>>>>>> &adev->sdma.trap_irq, >>>>>>> (i == 0) ? >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : >>>>>>> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs >>>> sdma_v3_0_ip_funcs >>>>> = >>>>>>> { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), >>>>>>> .get_rptr = sdma_v3_0_ring_get_rptr, >>>>>>> .get_wptr = sdma_v3_0_ring_get_wptr, >>>>>>> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/si_dma.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/si_dma.c >>>>>>> index 1aee45b..7fece1f 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c >>>>>>> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) >>>>>>> ring->use_doorbell = false; >>>>>>> sprintf(ring->name, "sdma%d", i); >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, >>>>>>> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, >>>>>>> 0), 0xf, >>>>>>> &adev->sdma.trap_irq, >>>>>>> (i == 0) ? >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : >>>>>>> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs = >>>>>>> { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), >>>>>>> .get_rptr = si_dma_ring_get_rptr, >>>>>>> .get_wptr = si_dma_ring_get_wptr, >>>>>>> .set_wptr = si_dma_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >>>>>>> index 55af8ac..1bab75a 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c >>>>>>> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) >>>>>>> >>>>>>> ring = &adev->uvd.ring; >>>>>>> sprintf(ring->name, "uvd"); >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, >> 0), >>>>>>> 0xf, >>>>>>> - &adev->uvd.irq, 0); >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, >>>>>>> + 0); >>>>>>> >>>>>>> return r; >>>>>>> } >>>>>>> @@ -743,6 +742,8 @@ const struct amd_ip_funcs >> uvd_v4_2_ip_funcs >>>>>>> = >>>> { >>>>>>> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_UVD, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), >>>>>>> .get_rptr = uvd_v4_2_ring_get_rptr, >>>>>>> .get_wptr = uvd_v4_2_ring_get_wptr, >>>>>>> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >>>>>>> index 21e725b..ec848fc 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c >>>>>>> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) >>>>>>> >>>>>>> ring = &adev->uvd.ring; >>>>>>> sprintf(ring->name, "uvd"); >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, >> 0), >>>>>>> 0xf, >>>>>>> - &adev->uvd.irq, 0); >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, >>>>>>> + 0); >>>>>>> >>>>>>> return r; >>>>>>> } >>>>>>> @@ -794,6 +793,8 @@ const struct amd_ip_funcs >> uvd_v5_0_ip_funcs >>>>>>> = >>>> { >>>>>>> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_UVD, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), >>>>>>> .get_rptr = uvd_v5_0_ring_get_rptr, >>>>>>> .get_wptr = uvd_v5_0_ring_get_wptr, >>>>>>> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >>>>>>> index 2ce1818..15708f8 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c >>>>>>> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) >>>>>>> >>>>>>> ring = &adev->uvd.ring; >>>>>>> sprintf(ring->name, "uvd"); >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, PACKET0(mmUVD_NO_OP, >> 0), >>>>>>> 0xf, >>>>>>> - &adev->uvd.irq, 0); >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, >>>>>>> + 0); >>>>>>> >>>>>>> return r; >>>>>>> } >>>>>>> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs >>>>>>> uvd_v6_0_ring_phys_funcs = { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_UVD, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), >>>>>>> .get_rptr = uvd_v6_0_ring_get_rptr, >>>>>>> .get_wptr = uvd_v6_0_ring_get_wptr, >>>>>>> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >>>>>>> index cf0c68f..d585839 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c >>>>>>> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) >>>>>>> for (i = 0; i < adev->vce.num_rings; i++) { >>>>>>> ring = &adev->vce.ring[i]; >>>>>>> sprintf(ring->name, "vce%d", i); >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, >> 0xf, >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, >>>>>>> &adev->vce.irq, 0); >>>>>>> if (r) >>>>>>> return r; @@ -611,6 +611,8 @@ const >>>>>>> struct amd_ip_funcs vce_v2_0_ip_funcs = >>>> { >>>>>>> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_VCE, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = VCE_CMD_NO_OP, >>>>>>> .get_rptr = vce_v2_0_ring_get_rptr, >>>>>>> .get_wptr = vce_v2_0_ring_get_wptr, >>>>>>> .set_wptr = vce_v2_0_ring_set_wptr, diff --git >>>>>>> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >>>>>>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >>>>>>> index 56a3feb..f7dbd0d 100644 >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c >>>>>>> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) >>>>>>> for (i = 0; i < adev->vce.num_rings; i++) { >>>>>>> ring = &adev->vce.ring[i]; >>>>>>> sprintf(ring->name, "vce%d", i); >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, >> 0xf, >>>>>>> - &adev->vce.irq, 0); >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, >>>>>>> + &adev->vce.irq, 0); >>>>>>> if (r) >>>>>>> return r; >>>>>>> } >>>>>>> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs >>>>>>> vce_v3_0_ring_phys_funcs = { >>>>>>> >>>>>>> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = { >>>>>>> .type = AMDGPU_RING_TYPE_VCE, >>>>>>> + .align_mask = 0xf, >>>>>>> + .nop = VCE_CMD_NO_OP, >>>>>>> .get_rptr = vce_v3_0_ring_get_rptr, >>>>>>> .get_wptr = vce_v3_0_ring_get_wptr, >>>>>>> .set_wptr = vce_v3_0_ring_set_wptr, >>>>>>> -- >>>>>>> 2.5.0 >>>>>>> >>>>>>> _______________________________________________ >>>>>>> amd-gfx mailing list >>>>>>> amd-gfx@lists.freedesktop.org >>>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >>>>> >>>>> _______________________________________________ >>>>> amd-gfx mailing list >>>>> amd-gfx@lists.freedesktop.org >>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >>>> _______________________________________________ >>>> amd-gfx mailing list >>>> amd-gfx@lists.freedesktop.org >>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
[parent not found: <dac6c3b7-6b15-7b0e-b9b0-a9bf5ad01832-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* RE: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well [not found] ` <dac6c3b7-6b15-7b0e-b9b0-a9bf5ad01832-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2016-10-28 11:22 ` Yu, Xiangliang 0 siblings, 0 replies; 22+ messages in thread From: Yu, Xiangliang @ 2016-10-28 11:22 UTC (permalink / raw) To: Christian König, Alex Deucher Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > -----Original Message----- > From: Christian König [mailto:deathsimple@vodafone.de] > Sent: Friday, October 28, 2016 6:13 PM > To: Yu, Xiangliang <Xiangliang.Yu@amd.com>; Alex Deucher > <alexdeucher@gmail.com> > Cc: amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring > funcs as well > > Am 28.10.2016 um 04:06 schrieb Yu, Xiangliang: > >>>>> NAK, we agreed upon moving the constant data into the functions > >>>>> structure as well. > >>>>> > >>>>> How about renaming the amdgpu_ring_funcs structure to make clear > >>>>> that it isn't only functions any more? Something > >>>>> amdgpu_ring_params or something like that? > >>> What benefit to put the constant data into the structure? > >>> If no, I'll create a new patch that create new structure for these > >>> constant > >> data. > >> > >> The functions and the parameters should be const. I don't care how > >> we arrange the structure(s). Feel free to re-arrange. > > Yes, I know. I'll replace the pointer address of function structure not the > member's content. > > I think this is best choice for making SRIOV code independent and easy to > maintain. > > I'm actually not sure if it is a good idea to make the SRIOV code independent, > but anyway I clearly don't see the advantage of putting the constant > members into a separate structure even with SRIOV. For you, there is not any advantage, but for me, I can use the structure for my code. And the constant structure can make the code very clear, and easy to be re-used or changed. I have spent two weeks to design SRIOV, I think you can see the advantage after Reviewing my SRIOV patches. > > On the other hand as Alex said feel free to rearrange the members in the > structure or rename the structure to better match it's purpose. I still think new structure is better, which benefit code reusing. > > > > >>>> Why not create a new structure for the constant data? It can make > >>>> code more flexible. > >>>> Actually, I'm working on SRIOV patches, I need the > >>>> amdgpu_ring_funcs structure so That easy to inherint all of function. > >>>> > >>>>> Regards, > >>>>> Christian. > >>>>> > >>>>> Am 26.10.2016 um 09:34 schrieb Yu, Xiangliang: > >>>>>> Hi Christian, > >>>>>> > >>>>>> Could you help put type, aligan_mask, nop of amdgpu_ring_funcs > >>>>>> struct > >>>>> field into amdgpu_ring struct? > >>>>>> I think amdgpu_ring_funcs should include function pointer, not > >>>>>> attribute. Your patches is not follow the struct design, and the > >>>>> amdgpu_ring will lost the meaning. > >>>>>> > >>>>>> Thanks! > >>>>>> Xiangliang Yu > >>>>>> > >>>>>>> -----Original Message----- > >>>>>>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] > On > >>>>>>> Behalf Of Christian K?nig > >>>>>>> Sent: Wednesday, October 05, 2016 10:13 PM > >>>>>>> To: amd-gfx@lists.freedesktop.org > >>>>>>> Subject: [PATCH 8/8] drm/amdgpu: move align_mask and nop into > >>>>>>> ring funcs as well > >>>>>>> > >>>>>>> From: Christian König <christian.koenig@amd.com> > >>>>>>> > >>>>>>> They are constant as well. > >>>>>>> > >>>>>>> Signed-off-by: Christian König <christian.koenig@amd.com> > >>>>>>> --- > >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 19 > >>>>>>> +++++++++-------- > >>>> -- > >>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 8 ++++---- > >>>>>>> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 7 ++++--- > >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 ++++++++------ > >>>>>>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 7 ++++--- > >>>>>>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 7 ++++--- > >>>>>>> drivers/gpu/drm/amd/amdgpu/si_dma.c | 3 ++- > >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 5 +++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 5 +++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 5 +++-- > >>>>>>> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 +++- > >>>>>>> drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 5 +++-- > >>>>>>> 14 files changed, 58 insertions(+), 43 deletions(-) > >>>>>>> > >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >>>>>>> index b2df735..a141b46 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c > >>>>>>> @@ -65,7 +65,7 @@ int amdgpu_ring_alloc(struct amdgpu_ring > >>>>>>> *ring, unsigned ndw) { > >>>>>>> /* Align requested size with padding so unlock_commit can > >>>>>>> * pad safely */ > >>>>>>> - ndw = (ndw + ring->align_mask) & ~ring->align_mask; > >>>>>>> + ndw = (ndw + ring->funcs->align_mask) & > >>>>>>> + ~ring->funcs->align_mask; > >>>>>>> > >>>>>>> /* Make sure we aren't trying to allocate more space > >>>>>>> * than the maximum for one submission @@ -94,7 +94,7 > >>>>>>> @@ void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, > >> uint32_t count) > >>>>>>> int i; > >>>>>>> > >>>>>>> for (i = 0; i < count; i++) > >>>>>>> - amdgpu_ring_write(ring, ring->nop); > >>>>>>> + amdgpu_ring_write(ring, ring->funcs->nop); > >>>>>>> } > >>>>>>> > >>>>>>> /** amdgpu_ring_generic_pad_ib - pad IB with NOP packets @@ > >>>>>>> -106,8 > >>>>>>> +106,8 @@ void amdgpu_ring_insert_nop(struct amdgpu_ring > *ring, > >>>>>>> uint32_t count) > >>>>>>> */ > >>>>>>> void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, > >>>>>>> struct amdgpu_ib *ib) { > >>>>>>> - while (ib->length_dw & ring->align_mask) > >>>>>>> - ib->ptr[ib->length_dw++] = ring->nop; > >>>>>>> + while (ib->length_dw & ring->funcs->align_mask) > >>>>>>> + ib->ptr[ib->length_dw++] = ring->funcs->nop; > >>>>>>> } > >>>>>>> > >>>>>>> /** > >>>>>>> @@ -125,8 +125,9 @@ void amdgpu_ring_commit(struct > >> amdgpu_ring > >>>>> *ring) > >>>>>>> uint32_t count; > >>>>>>> > >>>>>>> /* We pad to match fetch size */ > >>>>>>> - count = ring->align_mask + 1 - (ring->wptr & ring->align_mask); > >>>>>>> - count %= ring->align_mask + 1; > >>>>>>> + count = ring->funcs->align_mask + 1 - > >>>>>>> + (ring->wptr & ring->funcs->align_mask); > >>>>>>> + count %= ring->funcs->align_mask + 1; > >>>>>>> ring->funcs->insert_nop(ring, count); > >>>>>>> > >>>>>>> mb(); > >>>>>>> @@ -163,8 +164,8 @@ void amdgpu_ring_undo(struct > amdgpu_ring > >>>> *ring) > >>>>>>> * Returns 0 on success, error on failure. > >>>>>>> */ > >>>>>>> int amdgpu_ring_init(struct amdgpu_device *adev, struct > >>>>>>> amdgpu_ring *ring, > >>>>>>> - unsigned max_dw, u32 nop, u32 align_mask, > >>>>>>> - struct amdgpu_irq_src *irq_src, unsigned irq_type) > >>>>>>> + unsigned max_dw, struct amdgpu_irq_src *irq_src, > >>>>>>> + unsigned irq_type) > >>>>>>> { > >>>>>>> int r; > >>>>>>> > >>>>>>> @@ -215,8 +216,6 @@ int amdgpu_ring_init(struct amdgpu_device > >>>>>>> *adev, struct amdgpu_ring *ring, > >>>>>>> > >>>>>>> ring->ring_size = roundup_pow_of_two(max_dw * 4 * > >>>>>>> amdgpu_sched_hw_submission); > >>>>>>> - ring->align_mask = align_mask; > >>>>>>> - ring->nop = nop; > >>>>>>> > >>>>>>> /* Allocate ring buffer */ > >>>>>>> if (ring->ring_obj == NULL) { diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >>>>>>> index 6cf89c9..1ee1b65 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > >>>>>>> @@ -93,6 +93,8 @@ unsigned > amdgpu_fence_count_emitted(struct > >>>>>>> amdgpu_ring *ring); > >>>>>>> /* provided by hw blocks that expose a ring buffer for > >>>>>>> commands */ struct amdgpu_ring_funcs { > >>>>>>> enum amdgpu_ring_type type; > >>>>>>> + uint32_t align_mask; > >>>>>>> + u32 nop; > >>>>>>> > >>>>>>> /* ring read/write ptr handling */ > >>>>>>> u32 (*get_rptr)(struct amdgpu_ring *ring); @@ -149,10 > >>>>>>> +151,8 @@ struct amdgpu_ring { > >>>>>>> unsigned max_dw; > >>>>>>> int count_dw; > >>>>>>> uint64_t gpu_addr; > >>>>>>> - uint32_t align_mask; > >>>>>>> uint32_t ptr_mask; > >>>>>>> bool ready; > >>>>>>> - u32 nop; > >>>>>>> u32 idx; > >>>>>>> u32 me; > >>>>>>> u32 pipe; > >>>>>>> @@ -178,8 +178,8 @@ void amdgpu_ring_generic_pad_ib(struct > >>>>>>> amdgpu_ring *ring, struct amdgpu_ib *ib); void > >>>>>>> amdgpu_ring_commit(struct amdgpu_ring *ring); void > >>>>>>> amdgpu_ring_undo(struct amdgpu_ring *ring); int > >>>>> amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring > >>>>> *ring, > >>>>>>> - unsigned ring_size, u32 nop, u32 align_mask, > >>>>>>> - struct amdgpu_irq_src *irq_src, unsigned irq_type); > >>>>>>> + unsigned ring_size, struct amdgpu_irq_src *irq_src, > >>>>>>> + unsigned irq_type); > >>>>>>> void amdgpu_ring_fini(struct amdgpu_ring *ring); > >>>>>>> > >>>>>>> #endif > >>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >>>>>>> index f91f02f..664f894 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c > >>>>>>> @@ -205,10 +205,10 @@ static void > >>>>>>> cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >>>>>>> count) > >>>>>>> > >>>>>>> for (i = 0; i < count; i++) > >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) > >>>>>>> - amdgpu_ring_write(ring, ring->nop | > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop | > >>>>>>> SDMA_NOP_COUNT(count - 1)); > >>>>>>> else > >>>>>>> - amdgpu_ring_write(ring, ring->nop); > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop); > >>>>>>> } > >>>>>>> > >>>>>>> /** > >>>>>>> @@ -942,7 +942,6 @@ static int cik_sdma_sw_init(void *handle) > >>>>>>> ring->ring_obj = NULL; > >>>>>>> sprintf(ring->name, "sdma%d", i); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - SDMA_PACKET(SDMA_OPCODE_NOP, 0, > >>>>>>> 0), 0xf, > >>>>>>> &adev->sdma.trap_irq, > >>>>>>> (i == 0) ? > >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : > >>>>>>> @@ -1207,6 +1206,8 @@ const struct amd_ip_funcs > >>>>>>> cik_sdma_ip_funcs > >>>> = > >>>>> { > >>>>>>> static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), > >>>>>>> .get_rptr = cik_sdma_ring_get_rptr, > >>>>>>> .get_wptr = cik_sdma_ring_get_wptr, > >>>>>>> .set_wptr = cik_sdma_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>>>>>> index 1f8687fd..367b14e 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > >>>>>>> @@ -2869,7 +2869,6 @@ static int gfx_v6_0_sw_init(void *handle) > >>>>>>> ring->ring_obj = NULL; > >>>>>>> sprintf(ring->name, "gfx"); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - 0x80000000, 0xff, > >>>>>>> &adev->gfx.eop_irq, > >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); > >>>>>>> if (r) > >>>>>>> return r; @@ -2892,7 +2891,6 @@ static > >>>>>>> int gfx_v6_0_sw_init(void *handle) > >>>>>>> sprintf(ring->name, "comp %d.%d.%d", ring->me, > >>>>>>> ring->pipe, > >>>>>>> ring->queue); > >>>>>>> irq_type = > >>>>>>> AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >>>>>>> + ring->pipe; > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - 0x80000000, 0xff, > >>>>>>> &adev->gfx.eop_irq, irq_type); > >>>>>>> if (r) > >>>>>>> return r; @@ -3227,6 +3225,8 @@ const > >>>>>>> struct amd_ip_funcs gfx_v6_0_ip_funcs > >>>> = > >>>>> { > >>>>>>> static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = > { > >>>>>>> .type = AMDGPU_RING_TYPE_GFX, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = 0x80000000, > >>>>>>> .get_rptr = gfx_v6_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v6_0_ring_get_wptr, > >>>>>>> .set_wptr = gfx_v6_0_ring_set_wptr_gfx, @@ -3252,6 > >>>>>>> +3252,8 @@ static const struct amdgpu_ring_funcs > >>>>>>> gfx_v6_0_ring_funcs_gfx = { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs > >>>>>>> gfx_v6_0_ring_funcs_compute > >>>> = { > >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = 0x80000000, > >>>>>>> .get_rptr = gfx_v6_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v6_0_ring_get_wptr, > >>>>>>> .set_wptr = gfx_v6_0_ring_set_wptr_compute, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>>>>>> index be3881e..15f24bd 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > >>>>>>> @@ -4605,7 +4605,6 @@ static int gfx_v7_0_sw_init(void *handle) > >>>>>>> ring->ring_obj = NULL; > >>>>>>> sprintf(ring->name, "gfx"); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >>>>>>> &adev->gfx.eop_irq, > >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); > >>>>>>> if (r) > >>>>>>> return r; @@ -4631,7 +4630,6 @@ static > >>>>>>> int gfx_v7_0_sw_init(void *handle) > >>>>>>> irq_type = > >>>>>>> AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >>>>>>> + ring->pipe; > >>>>>>> /* type-2 packets are deprecated on MEC, use > >>>>>>> type-3 instead > >>>>> */ > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >>>>>>> &adev->gfx.eop_irq, irq_type); > >>>>>>> if (r) > >>>>>>> return r; @@ -5102,6 +5100,8 @@ const > >>>>>>> struct amd_ip_funcs gfx_v7_0_ip_funcs > >>>> = > >>>>> { > >>>>>>> static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = > { > >>>>>>> .type = AMDGPU_RING_TYPE_GFX, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >>>>>>> .get_rptr = gfx_v7_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v7_0_ring_get_wptr_gfx, > >>>>>>> .set_wptr = gfx_v7_0_ring_set_wptr_gfx, @@ -5130,6 > >>>>>>> +5130,8 @@ static const struct amdgpu_ring_funcs > >>>>>>> gfx_v7_0_ring_funcs_gfx = { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs > >>>>>>> gfx_v7_0_ring_funcs_compute > >>>> = { > >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >>>>>>> .get_rptr = gfx_v7_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v7_0_ring_get_wptr_compute, > >>>>>>> .set_wptr = gfx_v7_0_ring_set_wptr_compute, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>>>> index 0d66f49..51f1139 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >>>>>>> @@ -2061,9 +2061,8 @@ static int gfx_v8_0_sw_init(void *handle) > >>>>>>> ring->doorbell_index = > >>>>>>> AMDGPU_DOORBELL_GFX_RING0; > >>>>>>> } > >>>>>>> > >>>>>>> - r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >>>>>>> - &adev->gfx.eop_irq, > >>>>>>> AMDGPU_CP_IRQ_GFX_EOP); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 1024, &adev- > >gfx.eop_irq, > >>>>>>> + AMDGPU_CP_IRQ_GFX_EOP); > >>>>>>> if (r) > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -2087,9 +2086,8 @@ static int gfx_v8_0_sw_init(void *handle) > >>>>>>> sprintf(ring->name, "comp_%d.%d.%d", ring->me, > >>>>>>> ring- > >>>>>>>> pipe, ring->queue); > >>>>>>> irq_type = > >>>>>>> AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP > >>>>>>> + ring->pipe; > >>>>>>> /* type-2 packets are deprecated on MEC, use > >>>>>>> type-3 instead > >>>>> */ > >>>>>>> - r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - PACKET3(PACKET3_NOP, 0x3FFF), 0xff, > >>>>>>> - &adev->gfx.eop_irq, irq_type); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 1024, &adev- > >gfx.eop_irq, > >>>>>>> + irq_type); > >>>>>>> if (r) > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -6532,6 +6530,8 @@ const struct amd_ip_funcs > >>>>>>> gfx_v8_0_ip_funcs > >>>> = > >>>>> { > >>>>>>> static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = > { > >>>>>>> .type = AMDGPU_RING_TYPE_GFX, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >>>>>>> .get_rptr = gfx_v8_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v8_0_ring_get_wptr_gfx, > >>>>>>> .set_wptr = gfx_v8_0_ring_set_wptr_gfx, @@ -6562,6 > >>>>>>> +6562,8 @@ static const struct amdgpu_ring_funcs > >>>>>>> gfx_v8_0_ring_funcs_gfx = { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs > >>>>>>> gfx_v8_0_ring_funcs_compute > >>>> = { > >>>>>>> .type = AMDGPU_RING_TYPE_COMPUTE, > >>>>>>> + .align_mask = 0xff, > >>>>>>> + .nop = PACKET3(PACKET3_NOP, 0x3FFF), > >>>>>>> .get_rptr = gfx_v8_0_ring_get_rptr, > >>>>>>> .get_wptr = gfx_v8_0_ring_get_wptr_compute, > >>>>>>> .set_wptr = gfx_v8_0_ring_set_wptr_compute, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >>>>>>> index b11a81e..49c47d6 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c > >>>>>>> @@ -236,10 +236,10 @@ static void > >>>>>>> sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >>>>>>> count) > >>>>>>> > >>>>>>> for (i = 0; i < count; i++) > >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) > >>>>>>> - amdgpu_ring_write(ring, ring->nop | > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop | > >>>>>>> > >>>>>>> SDMA_PKT_NOP_HEADER_COUNT(count > >>>>>>> - > >>>>> 1)); > >>>>>>> else > >>>>>>> - amdgpu_ring_write(ring, ring->nop); > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop); > >>>>>>> } > >>>>>>> > >>>>>>> /** > >>>>>>> @@ -953,7 +953,6 @@ static int sdma_v2_4_sw_init(void *handle) > >>>>>>> ring->use_doorbell = false; > >>>>>>> sprintf(ring->name, "sdma%d", i); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - > >>>>>>> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >>>>>>> &adev->sdma.trap_irq, > >>>>>>> (i == 0) ? > >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : > >>>>>>> @@ -1211,6 +1210,8 @@ const struct amd_ip_funcs > >>>> sdma_v2_4_ip_funcs > >>>>> = > >>>>>>> { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >>>>>>> .get_rptr = sdma_v2_4_ring_get_rptr, > >>>>>>> .get_wptr = sdma_v2_4_ring_get_wptr, > >>>>>>> .set_wptr = sdma_v2_4_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >>>>>>> index accf4d1..f8ec370 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c > >>>>>>> @@ -396,10 +396,10 @@ static void > >>>>>>> sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t > >>>>>>> count) > >>>>>>> > >>>>>>> for (i = 0; i < count; i++) > >>>>>>> if (sdma && sdma->burst_nop && (i == 0)) > >>>>>>> - amdgpu_ring_write(ring, ring->nop | > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop | > >>>>>>> > >>>>>>> SDMA_PKT_NOP_HEADER_COUNT(count > >>>>>>> - > >>>>> 1)); > >>>>>>> else > >>>>>>> - amdgpu_ring_write(ring, ring->nop); > >>>>>>> + amdgpu_ring_write(ring, > >>>>>>> + ring->funcs->nop); > >>>>>>> } > >>>>>>> > >>>>>>> /** > >>>>>>> @@ -1165,7 +1165,6 @@ static int sdma_v3_0_sw_init(void > *handle) > >>>>>>> > >>>>>>> sprintf(ring->name, "sdma%d", i); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - > >>>>>>> SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf, > >>>>>>> &adev->sdma.trap_irq, > >>>>>>> (i == 0) ? > >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : > >>>>>>> @@ -1556,6 +1555,8 @@ const struct amd_ip_funcs > >>>> sdma_v3_0_ip_funcs > >>>>> = > >>>>>>> { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), > >>>>>>> .get_rptr = sdma_v3_0_ring_get_rptr, > >>>>>>> .get_wptr = sdma_v3_0_ring_get_wptr, > >>>>>>> .set_wptr = sdma_v3_0_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >>>>>>> index 1aee45b..7fece1f 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c > >>>>>>> @@ -531,7 +531,6 @@ static int si_dma_sw_init(void *handle) > >>>>>>> ring->use_doorbell = false; > >>>>>>> sprintf(ring->name, "sdma%d", i); > >>>>>>> r = amdgpu_ring_init(adev, ring, 1024, > >>>>>>> - DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, > >>>>>>> 0), 0xf, > >>>>>>> &adev->sdma.trap_irq, > >>>>>>> (i == 0) ? > >>>>>>> AMDGPU_SDMA_IRQ_TRAP0 : > >>>>>>> @@ -765,6 +764,8 @@ const struct amd_ip_funcs si_dma_ip_funcs > = > >>>>>>> { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs si_dma_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_SDMA, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0), > >>>>>>> .get_rptr = si_dma_ring_get_rptr, > >>>>>>> .get_wptr = si_dma_ring_get_wptr, > >>>>>>> .set_wptr = si_dma_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >>>>>>> index 55af8ac..1bab75a 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > >>>>>>> @@ -116,8 +116,7 @@ static int uvd_v4_2_sw_init(void *handle) > >>>>>>> > >>>>>>> ring = &adev->uvd.ring; > >>>>>>> sprintf(ring->name, "uvd"); > >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, > PACKET0(mmUVD_NO_OP, > >> 0), > >>>>>>> 0xf, > >>>>>>> - &adev->uvd.irq, 0); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >>>>>>> + 0); > >>>>>>> > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -743,6 +742,8 @@ const struct amd_ip_funcs > >> uvd_v4_2_ip_funcs > >>>>>>> = > >>>> { > >>>>>>> static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_UVD, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), > >>>>>>> .get_rptr = uvd_v4_2_ring_get_rptr, > >>>>>>> .get_wptr = uvd_v4_2_ring_get_wptr, > >>>>>>> .set_wptr = uvd_v4_2_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >>>>>>> index 21e725b..ec848fc 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > >>>>>>> @@ -112,8 +112,7 @@ static int uvd_v5_0_sw_init(void *handle) > >>>>>>> > >>>>>>> ring = &adev->uvd.ring; > >>>>>>> sprintf(ring->name, "uvd"); > >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, > PACKET0(mmUVD_NO_OP, > >> 0), > >>>>>>> 0xf, > >>>>>>> - &adev->uvd.irq, 0); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >>>>>>> + 0); > >>>>>>> > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -794,6 +793,8 @@ const struct amd_ip_funcs > >> uvd_v5_0_ip_funcs > >>>>>>> = > >>>> { > >>>>>>> static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_UVD, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), > >>>>>>> .get_rptr = uvd_v5_0_ring_get_rptr, > >>>>>>> .get_wptr = uvd_v5_0_ring_get_wptr, > >>>>>>> .set_wptr = uvd_v5_0_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >>>>>>> index 2ce1818..15708f8 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > >>>>>>> @@ -116,8 +116,7 @@ static int uvd_v6_0_sw_init(void *handle) > >>>>>>> > >>>>>>> ring = &adev->uvd.ring; > >>>>>>> sprintf(ring->name, "uvd"); > >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, > PACKET0(mmUVD_NO_OP, > >> 0), > >>>>>>> 0xf, > >>>>>>> - &adev->uvd.irq, 0); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, > >>>>>>> + 0); > >>>>>>> > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -1047,6 +1046,8 @@ static const struct amdgpu_ring_funcs > >>>>>>> uvd_v6_0_ring_phys_funcs = { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs > = { > >>>>>>> .type = AMDGPU_RING_TYPE_UVD, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = PACKET0(mmUVD_NO_OP, 0), > >>>>>>> .get_rptr = uvd_v6_0_ring_get_rptr, > >>>>>>> .get_wptr = uvd_v6_0_ring_get_wptr, > >>>>>>> .set_wptr = uvd_v6_0_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >>>>>>> index cf0c68f..d585839 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c > >>>>>>> @@ -224,7 +224,7 @@ static int vce_v2_0_sw_init(void *handle) > >>>>>>> for (i = 0; i < adev->vce.num_rings; i++) { > >>>>>>> ring = &adev->vce.ring[i]; > >>>>>>> sprintf(ring->name, "vce%d", i); > >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, > >> 0xf, > >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, > >>>>>>> &adev->vce.irq, 0); > >>>>>>> if (r) > >>>>>>> return r; @@ -611,6 +611,8 @@ const > >>>>>>> struct amd_ip_funcs vce_v2_0_ip_funcs = > >>>> { > >>>>>>> static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { > >>>>>>> .type = AMDGPU_RING_TYPE_VCE, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = VCE_CMD_NO_OP, > >>>>>>> .get_rptr = vce_v2_0_ring_get_rptr, > >>>>>>> .get_wptr = vce_v2_0_ring_get_wptr, > >>>>>>> .set_wptr = vce_v2_0_ring_set_wptr, diff --git > >>>>>>> a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >>>>>>> b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >>>>>>> index 56a3feb..f7dbd0d 100644 > >>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c > >>>>>>> @@ -389,8 +389,7 @@ static int vce_v3_0_sw_init(void *handle) > >>>>>>> for (i = 0; i < adev->vce.num_rings; i++) { > >>>>>>> ring = &adev->vce.ring[i]; > >>>>>>> sprintf(ring->name, "vce%d", i); > >>>>>>> - r = amdgpu_ring_init(adev, ring, 512, VCE_CMD_NO_OP, > >> 0xf, > >>>>>>> - &adev->vce.irq, 0); > >>>>>>> + r = amdgpu_ring_init(adev, ring, 512, > >>>>>>> + &adev->vce.irq, 0); > >>>>>>> if (r) > >>>>>>> return r; > >>>>>>> } > >>>>>>> @@ -850,6 +849,8 @@ static const struct amdgpu_ring_funcs > >>>>>>> vce_v3_0_ring_phys_funcs = { > >>>>>>> > >>>>>>> static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = > { > >>>>>>> .type = AMDGPU_RING_TYPE_VCE, > >>>>>>> + .align_mask = 0xf, > >>>>>>> + .nop = VCE_CMD_NO_OP, > >>>>>>> .get_rptr = vce_v3_0_ring_get_rptr, > >>>>>>> .get_wptr = vce_v3_0_ring_get_wptr, > >>>>>>> .set_wptr = vce_v3_0_ring_set_wptr, > >>>>>>> -- > >>>>>>> 2.5.0 > >>>>>>> > >>>>>>> _______________________________________________ > >>>>>>> amd-gfx mailing list > >>>>>>> amd-gfx@lists.freedesktop.org > >>>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >>>>> > >>>>> _______________________________________________ > >>>>> amd-gfx mailing list > >>>>> amd-gfx@lists.freedesktop.org > >>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >>>> _______________________________________________ > >>>> amd-gfx mailing list > >>>> amd-gfx@lists.freedesktop.org > >>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > >>> _______________________________________________ > >>> amd-gfx mailing list > >>> amd-gfx@lists.freedesktop.org > >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2016-10-28 11:22 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
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2016-10-05 14:13 [PATCH 1/8] drm/amdgpu: pad gfx and compute rings to 256 dw Christian König
[not found] ` <1475676809-3061-1-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-05 14:13 ` [PATCH 2/8] drm/amdgpu: "revert fix exclusive mode game texture blank(v2)" Christian König
2016-10-05 14:13 ` [PATCH 3/8] drm/amdgpu: remove ring type check for conditional execution Christian König
2016-10-05 14:13 ` [PATCH 4/8] drm/amdgpu: remove 128 NOP hack from vm_flush Christian König
[not found] ` <1475676809-3061-4-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-05 15:20 ` Deucher, Alexander
2016-10-05 14:13 ` [PATCH 5/8] drm/amdgpu: remove explicit NULL init for parse_cs Christian König
2016-10-05 14:13 ` [PATCH 6/8] drm/amdgpu: move IB and frame size directly into the engine description Christian König
2016-10-05 14:13 ` [PATCH 7/8] drm/amdgpu: move the ring type into the funcs structure Christian König
2016-10-05 14:13 ` [PATCH 8/8] drm/amdgpu: move align_mask and nop into ring funcs as well Christian König
[not found] ` <1475676809-3061-8-git-send-email-deathsimple-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-05 15:24 ` Deucher, Alexander
2016-10-11 13:13 ` Andy Furniss
[not found] ` <57FCE58E.5040107-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-10-11 13:26 ` Christian König
[not found] ` <82e102e9-cd1b-10ce-75ca-201ef4b802d4-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-11 13:28 ` StDenis, Tom
[not found] ` <CY4PR12MB1768C74FCED56F7663ABCE5BF7DA0-rpdhrqHFk06yjjPBNVDk/QdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-10-11 17:34 ` Christian König
2016-10-26 7:34 ` Yu, Xiangliang
[not found] ` <CY4PR12MB1701A02391D1C48C729FF51EEBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-10-26 9:16 ` Christian König
[not found] ` <0d8b9683-01c5-0fdc-d52f-bfdf2a0fa67c-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-26 14:18 ` Yu, Xiangliang
[not found] ` <CY4PR12MB170187E251705A2617860F49EBAB0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-10-27 9:55 ` Yu, Xiangliang
[not found] ` <CY4PR12MB17015B2156B539C0540A2905EBAA0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-10-27 14:34 ` Alex Deucher
[not found] ` <CADnq5_MS2dxbH64Q2mTv3fnqCF18bgBp7g=7EwLp9rR8Fw6tqA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-10-28 2:06 ` Yu, Xiangliang
[not found] ` <CY4PR12MB1701B0BCB6F6BE8F5281B1C0EBAD0-rpdhrqHFk05QaJCA3gGb3wdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2016-10-28 10:12 ` Christian König
[not found] ` <dac6c3b7-6b15-7b0e-b9b0-a9bf5ad01832-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2016-10-28 11:22 ` Yu, Xiangliang
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