* [PATCH 1/3] ARM: dts: socfpga: Add QSPI node for the Arria10 @ 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 0 siblings, 0 replies; 16+ messages in thread From: dinguyen at opensource.altera.com @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@opensource.altera.com> Add the QSPI device node for Arria10 SOC. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1149216..551c636 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -675,6 +675,20 @@ }; }; + qspi: spi at ff809000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr at ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/3] ARM: dts: socfpga: Add QSPI node for the Arria10 @ 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 0 siblings, 0 replies; 16+ messages in thread From: dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: dinh.linux-Re5JQEeQqe8AvxtiuMwx3w, dinguyen-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx, Dinh Nguyen From: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> Add the QSPI device node for Arria10 SOC. Signed-off-by: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> --- arch/arm/boot/dts/socfpga_arria10.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1149216..551c636 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -675,6 +675,20 @@ }; }; + qspi: spi@ff809000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/3] ARM: dts: socfpga: Enable QSPI in Arria10 devkit @ 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 0 siblings, 0 replies; 16+ messages in thread From: dinguyen at opensource.altera.com @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@opensource.altera.com> Enable the QSPI node and add the flash chip. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 49 ++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c5f0c3..081fd94 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -690,6 +690,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 0000000..beb2fc6 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Intel. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; + + flash0: n25q00 at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00aa"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition at qspi-boot { + label = "Boot and fpga data"; + reg = <0x0 0x2720000>; + }; + + partition at qspi-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x2720000 0x58E0000>; + }; + }; +}; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/3] ARM: dts: socfpga: Enable QSPI in Arria10 devkit @ 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 0 siblings, 0 replies; 16+ messages in thread From: dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r Cc: dinh.linux-Re5JQEeQqe8AvxtiuMwx3w, dinguyen-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA, grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx, Dinh Nguyen From: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> Enable the QSPI node and add the flash chip. Signed-off-by: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts | 49 ++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7c5f0c3..081fd94 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -690,6 +690,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ sh73a0-kzm9g.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ socfpga_cyclone5_socdk.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts new file mode 100644 index 0000000..beb2fc6 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_qspi.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Intel. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10_socdk.dtsi" + +&qspi { + status = "okay"; + + flash0: n25q00@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00aa"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + label = "Boot and fpga data"; + reg = <0x0 0x2720000>; + }; + + partition@qspi-rootfs { + label = "Root Filesystem - JFFS2"; + reg = <0x2720000 0x58E0000>; + }; + }; +}; -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx @ 2016-10-19 20:18 ` dinguyen -1 siblings, 0 replies; 16+ messages in thread From: dinguyen at opensource.altera.com @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel From: Dinh Nguyen <dinguyen@opensource.altera.com> Enable the QSPI node and add the flash chip. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 02e22f5..2f75e0f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -175,6 +175,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash at 0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition at qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition at qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-19 20:18 ` dinguyen 0 siblings, 0 replies; 16+ messages in thread From: dinguyen @ 2016-10-19 20:18 UTC (permalink / raw) To: linux-arm-kernel; +Cc: dinguyen, Dinh Nguyen, grmoore, dinh.linux, devicetree From: Dinh Nguyen <dinguyen@opensource.altera.com> Enable the QSPI node and add the flash chip. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> --- arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 33 +++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index 02e22f5..2f75e0f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -175,6 +175,39 @@ status = "okay"; }; +&qspi { + status = "okay"; + + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q256a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partition@qspi-boot { + /* 8MB for raw data. */ + label = "Flash 0 Raw Data"; + reg = <0x0 0x800000>; + }; + + partition@qspi-rootfs { + /* 120MB for jffs2 data. */ + label = "Flash 0 jffs2 Filesystem"; + reg = <0x800000 0x7800000>; + }; + }; +}; + &usb1 { status = "okay"; }; -- 1.7.9.5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-20 7:19 ` Steffen Trumtrar 0 siblings, 0 replies; 16+ messages in thread From: Steffen Trumtrar @ 2016-10-20 7:19 UTC (permalink / raw) To: linux-arm-kernel Hi! On Wed, Oct 19, 2016 at 03:18:44PM -0500, dinguyen at opensource.altera.com wrote: > From: Dinh Nguyen <dinguyen@opensource.altera.com> > > Enable the QSPI node and add the flash chip. > > Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com> > --- > arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 33 +++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > index 02e22f5..2f75e0f 100644 > --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > @@ -175,6 +175,39 @@ > status = "okay"; > }; > > +&qspi { > + status = "okay"; > + > + flash: flash at 0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "n25q256a"; > + reg = <0>; > + spi-max-frequency = <100000000>; > + > + m25p,fast-read; > + cdns,page-size = <256>; > + cdns,block-size = <16>; > + cdns,read-delay = <4>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + > + partition at qspi-boot { > + /* 8MB for raw data. */ > + label = "Flash 0 Raw Data"; > + reg = <0x0 0x800000>; > + }; > + > + partition at qspi-rootfs { > + /* 120MB for jffs2 data. */ > + label = "Flash 0 jffs2 Filesystem"; > + reg = <0x800000 0x7800000>; > + }; > + }; > +}; > + What is the current preferred way of handling the partitions? This doesn't fit my Sockit configuration for example. So I would always have to patch the devicetree. On the Socrates I didn't specify the partitions, because I did not want to force a specific configuration. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-20 7:19 ` Steffen Trumtrar 0 siblings, 0 replies; 16+ messages in thread From: Steffen Trumtrar @ 2016-10-20 7:19 UTC (permalink / raw) To: dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, dinguyen-DgEjT+Ai2ygdnm+yROfE0A, grmoore-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx, dinh.linux-Re5JQEeQqe8AvxtiuMwx3w, devicetree-u79uwXL29TY76Z2rM5mHXA Hi! On Wed, Oct 19, 2016 at 03:18:44PM -0500, dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote: > From: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> > > Enable the QSPI node and add the flash chip. > > Signed-off-by: Dinh Nguyen <dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org> > --- > arch/arm/boot/dts/socfpga_cyclone5_sockit.dts | 33 +++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > index 02e22f5..2f75e0f 100644 > --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts > @@ -175,6 +175,39 @@ > status = "okay"; > }; > > +&qspi { > + status = "okay"; > + > + flash: flash@0 { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "n25q256a"; > + reg = <0>; > + spi-max-frequency = <100000000>; > + > + m25p,fast-read; > + cdns,page-size = <256>; > + cdns,block-size = <16>; > + cdns,read-delay = <4>; > + cdns,tshsl-ns = <50>; > + cdns,tsd2d-ns = <50>; > + cdns,tchsh-ns = <4>; > + cdns,tslch-ns = <4>; > + > + partition@qspi-boot { > + /* 8MB for raw data. */ > + label = "Flash 0 Raw Data"; > + reg = <0x0 0x800000>; > + }; > + > + partition@qspi-rootfs { > + /* 120MB for jffs2 data. */ > + label = "Flash 0 jffs2 Filesystem"; > + reg = <0x800000 0x7800000>; > + }; > + }; > +}; > + What is the current preferred way of handling the partitions? This doesn't fit my Sockit configuration for example. So I would always have to patch the devicetree. On the Socrates I didn't specify the partitions, because I did not want to force a specific configuration. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit 2016-10-20 7:19 ` Steffen Trumtrar @ 2016-10-20 14:12 ` Dinh Nguyen -1 siblings, 0 replies; 16+ messages in thread From: Dinh Nguyen @ 2016-10-20 14:12 UTC (permalink / raw) To: linux-arm-kernel On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: >> + cdns,tslch-ns = <4>; >> + >> + partition at qspi-boot { >> + /* 8MB for raw data. */ >> + label = "Flash 0 Raw Data"; >> + reg = <0x0 0x800000>; >> + }; >> + >> + partition at qspi-rootfs { >> + /* 120MB for jffs2 data. */ >> + label = "Flash 0 jffs2 Filesystem"; >> + reg = <0x800000 0x7800000>; >> + }; >> + }; >> +}; >> + > > What is the current preferred way of handling the partitions? > This doesn't fit my Sockit configuration for example. So I would always > have to patch the devicetree. I'm not 100% sure on this. Graham, do you have any insight? > > On the Socrates I didn't specify the partitions, because I did not > want to force a specific configuration. > I know that on Arria10, we needed a specific configuration. Dinh ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-20 14:12 ` Dinh Nguyen 0 siblings, 0 replies; 16+ messages in thread From: Dinh Nguyen @ 2016-10-20 14:12 UTC (permalink / raw) To: Steffen Trumtrar Cc: dinguyen, devicetree, dinh.linux, linux-arm-kernel, grmoore On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: >> + cdns,tslch-ns = <4>; >> + >> + partition@qspi-boot { >> + /* 8MB for raw data. */ >> + label = "Flash 0 Raw Data"; >> + reg = <0x0 0x800000>; >> + }; >> + >> + partition@qspi-rootfs { >> + /* 120MB for jffs2 data. */ >> + label = "Flash 0 jffs2 Filesystem"; >> + reg = <0x800000 0x7800000>; >> + }; >> + }; >> +}; >> + > > What is the current preferred way of handling the partitions? > This doesn't fit my Sockit configuration for example. So I would always > have to patch the devicetree. I'm not 100% sure on this. Graham, do you have any insight? > > On the Socrates I didn't specify the partitions, because I did not > want to force a specific configuration. > I know that on Arria10, we needed a specific configuration. Dinh ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit 2016-10-20 14:12 ` Dinh Nguyen @ 2016-10-25 15:38 ` Graham Moore -1 siblings, 0 replies; 16+ messages in thread From: Graham Moore @ 2016-10-25 15:38 UTC (permalink / raw) To: linux-arm-kernel On 10/20/2016 09:12 AM, Dinh Nguyen wrote: > > > On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: > >>> + cdns,tslch-ns = <4>; >>> + >>> + partition at qspi-boot { >>> + /* 8MB for raw data. */ >>> + label = "Flash 0 Raw Data"; >>> + reg = <0x0 0x800000>; >>> + }; >>> + >>> + partition at qspi-rootfs { >>> + /* 120MB for jffs2 data. */ >>> + label = "Flash 0 jffs2 Filesystem"; >>> + reg = <0x800000 0x7800000>; >>> + }; >>> + }; >>> +}; >>> + >> >> What is the current preferred way of handling the partitions? >> This doesn't fit my Sockit configuration for example. So I would always >> have to patch the devicetree. > > I'm not 100% sure on this. Graham, do you have any insight? >> Well, strictly speaking, these partitions are only for the socdk, the Altera dev kit. Our sample designs and file systems expect this layout. Therefore, these partitions are not required for any other dev kits, and can probably be left out. Or, Steffen, if you have a standard layout you'd like to see, then put that in there. I think some people will have to patch the layout regardless. -Graham ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-25 15:38 ` Graham Moore 0 siblings, 0 replies; 16+ messages in thread From: Graham Moore @ 2016-10-25 15:38 UTC (permalink / raw) To: Dinh Nguyen, Steffen Trumtrar Cc: dinguyen, dinh.linux, linux-arm-kernel, devicetree On 10/20/2016 09:12 AM, Dinh Nguyen wrote: > > > On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: > >>> + cdns,tslch-ns = <4>; >>> + >>> + partition@qspi-boot { >>> + /* 8MB for raw data. */ >>> + label = "Flash 0 Raw Data"; >>> + reg = <0x0 0x800000>; >>> + }; >>> + >>> + partition@qspi-rootfs { >>> + /* 120MB for jffs2 data. */ >>> + label = "Flash 0 jffs2 Filesystem"; >>> + reg = <0x800000 0x7800000>; >>> + }; >>> + }; >>> +}; >>> + >> >> What is the current preferred way of handling the partitions? >> This doesn't fit my Sockit configuration for example. So I would always >> have to patch the devicetree. > > I'm not 100% sure on this. Graham, do you have any insight? >> Well, strictly speaking, these partitions are only for the socdk, the Altera dev kit. Our sample designs and file systems expect this layout. Therefore, these partitions are not required for any other dev kits, and can probably be left out. Or, Steffen, if you have a standard layout you'd like to see, then put that in there. I think some people will have to patch the layout regardless. -Graham ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-25 18:57 ` Dinh Nguyen 0 siblings, 0 replies; 16+ messages in thread From: Dinh Nguyen @ 2016-10-25 18:57 UTC (permalink / raw) To: linux-arm-kernel On 10/25/2016 10:38 AM, Graham Moore wrote: > On 10/20/2016 09:12 AM, Dinh Nguyen wrote: >> >> >> On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: >> >>>> + cdns,tslch-ns = <4>; >>>> + >>>> + partition at qspi-boot { >>>> + /* 8MB for raw data. */ >>>> + label = "Flash 0 Raw Data"; >>>> + reg = <0x0 0x800000>; >>>> + }; >>>> + >>>> + partition at qspi-rootfs { >>>> + /* 120MB for jffs2 data. */ >>>> + label = "Flash 0 jffs2 Filesystem"; >>>> + reg = <0x800000 0x7800000>; >>>> + }; >>>> + }; >>>> +}; >>>> + >>> >>> What is the current preferred way of handling the partitions? >>> This doesn't fit my Sockit configuration for example. So I would always >>> have to patch the devicetree. >> >> I'm not 100% sure on this. Graham, do you have any insight? >>> > > Well, strictly speaking, these partitions are only for the socdk, the > Altera dev kit. Our sample designs and file systems expect this layout. > > Therefore, these partitions are not required for any other dev kits, and > can probably be left out. > > Or, Steffen, if you have a standard layout you'd like to see, then put > that in there. > > I think some people will have to patch the layout regardless. > Ok, I'll remove the partitions from the none Altera boards. Dinh ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-25 18:57 ` Dinh Nguyen 0 siblings, 0 replies; 16+ messages in thread From: Dinh Nguyen @ 2016-10-25 18:57 UTC (permalink / raw) To: Graham Moore, Steffen Trumtrar Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, dinguyen-DgEjT+Ai2ygdnm+yROfE0A, dinh.linux-Re5JQEeQqe8AvxtiuMwx3w, devicetree-u79uwXL29TY76Z2rM5mHXA On 10/25/2016 10:38 AM, Graham Moore wrote: > On 10/20/2016 09:12 AM, Dinh Nguyen wrote: >> >> >> On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: >> >>>> + cdns,tslch-ns = <4>; >>>> + >>>> + partition@qspi-boot { >>>> + /* 8MB for raw data. */ >>>> + label = "Flash 0 Raw Data"; >>>> + reg = <0x0 0x800000>; >>>> + }; >>>> + >>>> + partition@qspi-rootfs { >>>> + /* 120MB for jffs2 data. */ >>>> + label = "Flash 0 jffs2 Filesystem"; >>>> + reg = <0x800000 0x7800000>; >>>> + }; >>>> + }; >>>> +}; >>>> + >>> >>> What is the current preferred way of handling the partitions? >>> This doesn't fit my Sockit configuration for example. So I would always >>> have to patch the devicetree. >> >> I'm not 100% sure on this. Graham, do you have any insight? >>> > > Well, strictly speaking, these partitions are only for the socdk, the > Altera dev kit. Our sample designs and file systems expect this layout. > > Therefore, these partitions are not required for any other dev kits, and > can probably be left out. > > Or, Steffen, if you have a standard layout you'd like to see, then put > that in there. > > I think some people will have to patch the layout regardless. > Ok, I'll remove the partitions from the none Altera boards. Dinh -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-26 7:22 ` Steffen Trumtrar 0 siblings, 0 replies; 16+ messages in thread From: Steffen Trumtrar @ 2016-10-26 7:22 UTC (permalink / raw) To: linux-arm-kernel Hi! On Tue, Oct 25, 2016 at 10:38:10AM -0500, Graham Moore wrote: > On 10/20/2016 09:12 AM, Dinh Nguyen wrote: > > > > > > On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: > > > > > > + cdns,tslch-ns = <4>; > > > > + > > > > + partition at qspi-boot { > > > > + /* 8MB for raw data. */ > > > > + label = "Flash 0 Raw Data"; > > > > + reg = <0x0 0x800000>; > > > > + }; > > > > + > > > > + partition at qspi-rootfs { > > > > + /* 120MB for jffs2 data. */ > > > > + label = "Flash 0 jffs2 Filesystem"; > > > > + reg = <0x800000 0x7800000>; > > > > + }; > > > > + }; > > > > +}; > > > > + > > > > > > What is the current preferred way of handling the partitions? > > > This doesn't fit my Sockit configuration for example. So I would always > > > have to patch the devicetree. > > > > I'm not 100% sure on this. Graham, do you have any insight? > > > > > Well, strictly speaking, these partitions are only for the socdk, the Altera > dev kit. Our sample designs and file systems expect this layout. The thing is, that I don't think these partitions belong in a mainline dts at all. But I'm not sure what the current policy is. > > Therefore, these partitions are not required for any other dev kits, and can > probably be left out. > > Or, Steffen, if you have a standard layout you'd like to see, then put that > in there. > Well in my case, it actually doesn't really matter. All the boards I use do not have u-boot as bootloader but barebox. And barebox uses devicetree fixups for adding the partition layout that fits the particular use case. All other partitions are thrown out. I don't know if u-boot does something like this. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit @ 2016-10-26 7:22 ` Steffen Trumtrar 0 siblings, 0 replies; 16+ messages in thread From: Steffen Trumtrar @ 2016-10-26 7:22 UTC (permalink / raw) To: Graham Moore Cc: Dinh Nguyen, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, dinguyen-DgEjT+Ai2ygdnm+yROfE0A, dinh.linux-Re5JQEeQqe8AvxtiuMwx3w, devicetree-u79uwXL29TY76Z2rM5mHXA Hi! On Tue, Oct 25, 2016 at 10:38:10AM -0500, Graham Moore wrote: > On 10/20/2016 09:12 AM, Dinh Nguyen wrote: > > > > > > On 10/20/2016 02:19 AM, Steffen Trumtrar wrote: > > > > > > + cdns,tslch-ns = <4>; > > > > + > > > > + partition@qspi-boot { > > > > + /* 8MB for raw data. */ > > > > + label = "Flash 0 Raw Data"; > > > > + reg = <0x0 0x800000>; > > > > + }; > > > > + > > > > + partition@qspi-rootfs { > > > > + /* 120MB for jffs2 data. */ > > > > + label = "Flash 0 jffs2 Filesystem"; > > > > + reg = <0x800000 0x7800000>; > > > > + }; > > > > + }; > > > > +}; > > > > + > > > > > > What is the current preferred way of handling the partitions? > > > This doesn't fit my Sockit configuration for example. So I would always > > > have to patch the devicetree. > > > > I'm not 100% sure on this. Graham, do you have any insight? > > > > > Well, strictly speaking, these partitions are only for the socdk, the Altera > dev kit. Our sample designs and file systems expect this layout. The thing is, that I don't think these partitions belong in a mainline dts at all. But I'm not sure what the current policy is. > > Therefore, these partitions are not required for any other dev kits, and can > probably be left out. > > Or, Steffen, if you have a standard layout you'd like to see, then put that > in there. > Well in my case, it actually doesn't really matter. All the boards I use do not have u-boot as bootloader but barebox. And barebox uses devicetree fixups for adding the partition layout that fits the particular use case. All other partitions are thrown out. I don't know if u-boot does something like this. Regards, Steffen -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-10-26 7:22 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-10-19 20:18 [PATCH 1/3] ARM: dts: socfpga: Add QSPI node for the Arria10 dinguyen at opensource.altera.com 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 2016-10-19 20:18 ` [PATCH 2/3] ARM: dts: socfpga: Enable QSPI in Arria10 devkit dinguyen at opensource.altera.com 2016-10-19 20:18 ` dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx 2016-10-19 20:18 ` [PATCH 3/3] ARM: dts: socfpga: Enable QSPI on the Cyclone5 sockit dinguyen at opensource.altera.com 2016-10-19 20:18 ` dinguyen 2016-10-20 7:19 ` Steffen Trumtrar 2016-10-20 7:19 ` Steffen Trumtrar 2016-10-20 14:12 ` Dinh Nguyen 2016-10-20 14:12 ` Dinh Nguyen 2016-10-25 15:38 ` Graham Moore 2016-10-25 15:38 ` Graham Moore 2016-10-25 18:57 ` Dinh Nguyen 2016-10-25 18:57 ` Dinh Nguyen 2016-10-26 7:22 ` Steffen Trumtrar 2016-10-26 7:22 ` Steffen Trumtrar
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