Re: [PATCH] drm/amdgpu: set bypass mode when uvd is idle.

[Andy Furniss <adf.lists-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]

Zhu, Rex wrote:
>>>> Is there any harm in just always putting it into bypass mode or
>>>> does it interact badly with PG?  Presumably it does (otherwise
>>>> we wouldn't need this patch), it would be good to note why.
>
> Rex: when UVD PG enabled, DCLK/VCLK will be turn off when uvd is
> idle(DCLK=OFF). If we set bypass mode=1, dclk/vclk will be bypassed
> to an external ‘Bypass’ clock(DCLK = 100MHz)
>
> So it is unnecessary to set bypass mode when PG enabled.
>
> +uvd_v5_0_set_bypass_mode(adev, !enable); This change is because
> tom's commit 72cb64c1f6a3a8129af341e90418a687c4971a40 Fix the
> sequence of UVD powergate function in smu7_clockgating.c.

I was about to file a bug till I tried this which fixes UVD perf
on my R9285 + agd5f drm-next-4.10-wip.

Additional unrelated question = I notice that UVD does not seem
to set other clocks quite high enough when used.

For playback the vo may bump things up a bit, but even then it can be a bit
borderline for playing high bitrate UHD with powerplay on auto.

Pure decode benchmarks like

ffmpeg -hwaccel vdpau -i high-bitrate-2160p60-vid -pix_fmt nv12 -f null -

go from 63 -> 81 fps, powerplay auto -> high.
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