* [PATCH v14 0/4] Initial Marvell PXA1908 support
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović via B4 Relay @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović,
Krzysztof Kozlowski
Hello,
This series adds initial support for the Marvell PXA1908 SoC and
"samsung,coreprimevelte", a smartphone using the SoC.
USB works and the phone can boot a rootfs from an SD card, but there are
some warnings in the dmesg:
During SMP initialization:
[ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
[ 0.006542] CPU features: Unsupported CPU feature variation detected.
[ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032]
[ 0.010710] Detected VIPT I-cache on CPU2
[ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
[ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032]
[ 0.014849] Detected VIPT I-cache on CPU3
[ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
[ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032]
SMMU probing fails:
[ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration...
[ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with:
[ 0.101816] arm-smmu c0010000.iommu: no translation support!
A 3.14 based Marvell tree is available on GitHub
acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub
CoderCharmander/g361f-kernel.
Andreas Färber attempted to upstream support for this SoC in 2017:
https://lore.kernel.org/lkml/20170222022929.10540-1-afaerber@suse.de/
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Changes in v14:
- Rebase on v6.13-rc7, dropping everything except DT
- Link to v13: https://lore.kernel.org/r/20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr
Changes in v13:
- Better describe the hardware in bindings/arm commit message
- Rebase on v6.12-rc1
- Link to v12: https://lore.kernel.org/r/20240823-pxa1908-lkml-v12-0-cc3ada51beb0@skole.hr
Changes in v12:
- Rebase on v6.11-rc4
- Fix schmitt properties in accordance with 78d8815031fb ("dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties")
- Drop a few redundant includes in clock drivers
- Link to v11: https://lore.kernel.org/r/20240730-pxa1908-lkml-v11-0-21dbb3e28793@skole.hr
Changes in v11:
- Rebase on v6.11-rc1 (conflict with DTS Makefile), no changes
- Link to v10: https://lore.kernel.org/r/20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr
Changes in v10:
- Update trailers
- Rebase on v6.9-rc5
- Clock driver changes:
- Add a couple of forgotten clocks in APBC
- The clocks are thermal_clk, ipc_clk, ssp0_clk, ssp2_clk and swjtag
- The IDs and register offsets were already present, but I forgot to
actually register them
- Split each controller block into own file
- Drop unneeded -of in clock driver filenames
- Simplify struct pxa1908_clk_unit
- Convert to platform driver
- Add module metadata
- DTS changes:
- Properly name pinctrl nodes
- Drop pinctrl #size-cells, #address-cells, ranges and #gpio-size-cells
- Fix pinctrl input-schmitt configuration
- Link to v9: https://lore.kernel.org/20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr
Changes in v9:
- Update trailers and rebase on v6.9-rc2, no changes
- Link to v8: https://lore.kernel.org/20240110-pxa1908-lkml-v8-0-fea768a59474@skole.hr
Changes in v8:
- Drop SSPA patch
- Drop broken-cd from eMMC node
- Specify S-Boot hardcoded initramfs location in device tree
- Add ARM PMU node
- Correct inverted modem memory base and size
- Update trailers
- Rebase on next-20240110
- Link to v7: https://lore.kernel.org/20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr
and https://lore.kernel.org/20231102152033.5511-1-duje.mihanovic@skole.hr
Changes in v7:
- Suppress SND_MMP_SOC_SSPA on ARM64
- Update trailers
- Rebase on v6.6-rc7
- Link to v6: https://lore.kernel.org/r/20231010-pxa1908-lkml-v6-0-b2fe09240cf8@skole.hr
Changes in v6:
- Address maintainer comments:
- Add "marvell,pxa1908-padconf" binding to pinctrl-single driver
- Drop GPIO patch as it's been pulled
- Update trailers
- Rebase on v6.6-rc5
- Link to v5: https://lore.kernel.org/r/20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr
Changes in v5:
- Address maintainer comments:
- Move *_NR_CLKS to clock driver from dt binding file
- Allocate correct number of clocks for each block instead of blindly
allocating 50 for each
- Link to v4: https://lore.kernel.org/r/20230807-pxa1908-lkml-v4-0-cb387d73b452@skole.hr
Changes in v4:
- Address maintainer comments:
- Relicense clock binding file to BSD-2
- Add pinctrl-names to SD card node
- Add vgic registers to GIC node
- Rebase on v6.5-rc5
- Link to v3: https://lore.kernel.org/r/20230804-pxa1908-lkml-v3-0-8e48fca37099@skole.hr
Changes in v3:
- Address maintainer comments:
- Drop GPIO dynamic allocation patch
- Move clock register offsets into driver (instead of bindings file)
- Add missing Tested-by trailer to u32_fract patch
- Move SoC binding to arm/mrvl/mrvl.yaml
- Add serial0 alias and stdout-path to board dts to enable UART
debugging
- Rebase on v6.5-rc4
- Link to v2: https://lore.kernel.org/r/20230727162909.6031-1-duje.mihanovic@skole.hr
Changes in v2:
- Remove earlycon patch as it's been merged into tty-next
- Address maintainer comments:
- Clarify GPIO regressions on older PXA platforms
- Add Fixes tag to commit disabling GPIO pinctrl calls for this SoC
- Add missing includes to clock driver
- Clock driver uses HZ_PER_MHZ, u32_fract and GENMASK
- Dual license clock bindings
- Change clock IDs to decimal
- Fix underscores in dt node names
- Move chosen node to top of board dts
- Clean up documentation
- Reorder commits
- Drop pxa,rev-id
- Rename muic-i2c to i2c-muic
- Reword some commits
- Move framebuffer node to chosen
- Add aliases for mmc nodes
- Rebase on v6.5-rc3
- Link to v1: https://lore.kernel.org/r/20230721210042.21535-1-duje.mihanovic@skole.hr
---
Duje Mihanović (4):
dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
MAINTAINERS: add myself as Marvell PXA1908 maintainer
.../devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +
MAINTAINERS | 9 +
arch/arm64/Kconfig.platforms | 8 +
arch/arm64/boot/dts/marvell/Makefile | 3 +
.../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++
6 files changed, 661 insertions(+)
---
base-commit: 5bc55a333a2f7316b58edc7573e8e893f7acb532
change-id: 20230803-pxa1908-lkml-6830e8da45c7
Best regards,
--
Duje Mihanović <duje.mihanovic@skole.hr>
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH v14 1/4] dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
-1 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović,
Krzysztof Kozlowski
Add dt bindings for the Marvell PXA1908 SoC and the Samsung Galaxy Core
Prime VE LTE phone (model number SM-G361F) using the SoC.
The SoC comes with 4 Cortex-A53 cores clocked up to ~1.2GHz and a
Vivante GC7000UL GPU. The phone also has a 4.5" 480x800 touchscreen, 8GB
eMMC and 1GB of LPDDR3 RAM.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index 4c43eaf3632e4ec8e7d9aeac62f7204e2af4405a..f73bb8ec3a1a1b9594eb059b72d95dcbf8c87c6b 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
+ - description: PXA1908 based boards
+ items:
+ - enum:
+ - samsung,coreprimevelte
+ - const: marvell,pxa1908
additionalProperties: true
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v14 1/4] dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović via B4 Relay @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović,
Krzysztof Kozlowski
From: Duje Mihanović <duje.mihanovic@skole.hr>
Add dt bindings for the Marvell PXA1908 SoC and the Samsung Galaxy Core
Prime VE LTE phone (model number SM-G361F) using the SoC.
The SoC comes with 4 Cortex-A53 cores clocked up to ~1.2GHz and a
Vivante GC7000UL GPU. The phone also has a 4.5" 480x800 touchscreen, 8GB
eMMC and 1GB of LPDDR3 RAM.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
index 4c43eaf3632e4ec8e7d9aeac62f7204e2af4405a..f73bb8ec3a1a1b9594eb059b72d95dcbf8c87c6b 100644
--- a/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
+++ b/Documentation/devicetree/bindings/arm/mrvl/mrvl.yaml
@@ -35,6 +35,11 @@ properties:
- enum:
- dell,wyse-ariel
- const: marvell,mmp3
+ - description: PXA1908 based boards
+ items:
+ - enum:
+ - samsung,coreprimevelte
+ - const: marvell,pxa1908
additionalProperties: true
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v14 2/4] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
-1 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/Kconfig.platforms | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 370a9d2b6919d24d6c7111b95bb69a51bdf64e5a..ff9e3c3d5dd4636745b8efd79feb6706c76ec989 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -175,6 +175,14 @@ config ARCH_MESON
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
+config ARCH_MMP
+ bool "Marvell MMP SoC Family"
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ This enables support for Marvell MMP SoC family, currently
+ supporting PXA1908 aka IAP140.
+
config ARCH_MVEBU
bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v14 2/4] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović via B4 Relay @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
From: Duje Mihanović <duje.mihanovic@skole.hr>
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/Kconfig.platforms | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 370a9d2b6919d24d6c7111b95bb69a51bdf64e5a..ff9e3c3d5dd4636745b8efd79feb6706c76ec989 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -175,6 +175,14 @@ config ARCH_MESON
This enables support for the arm64 based Amlogic SoCs
such as the s905, S905X/D, S912, A113X/D or S905X/D2
+config ARCH_MMP
+ bool "Marvell MMP SoC Family"
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ This enables support for Marvell MMP SoC family, currently
+ supporting PXA1908 aka IAP140.
+
config ARCH_MVEBU
bool "Marvell EBU SoC Family"
select ARMADA_AP806_SYSCON
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v14 2/4] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
(?)
@ 2025-01-16 7:52 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-16 7:52 UTC (permalink / raw)
To: Duje Mihanović
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On Wed, Jan 15, 2025 at 09:35:55PM +0100, Duje Mihanović wrote:
> Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
>
> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> ---
> arch/arm64/Kconfig.platforms | 8 ++++++++
> 1 file changed, 8 insertions(+)
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v14 2/4] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
(?)
(?)
@ 2025-01-17 6:13 ` kernel test robot
-1 siblings, 0 replies; 20+ messages in thread
From: kernel test robot @ 2025-01-17 6:13 UTC (permalink / raw)
To: Duje Mihanović via B4 Relay, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: Paul Gazzillo, Necip Fazil Yildiran, oe-kbuild-all, David Wronek,
Karel Balej, devicetree, linux-kernel, linux-arm-kernel,
linux-hardening, phone-devel, ~postmarketos/upstreaming,
Duje Mihanović
Hi Duje,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 5bc55a333a2f7316b58edc7573e8e893f7acb532]
url: https://github.com/intel-lab-lkp/linux/commits/Duje-Mihanovi-via-B4-Relay/dt-bindings-marvell-Document-PXA1908-SoC-and-samsung-coreprimevelte/20250116-044350
base: 5bc55a333a2f7316b58edc7573e8e893f7acb532
patch link: https://lore.kernel.org/r/20250115-pxa1908-lkml-v14-2-847d24f3665a%40skole.hr
patch subject: [PATCH v14 2/4] arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
config: arm64-kismet-CONFIG_I2C_GPIO-CONFIG_VIDEO_MMP_CAMERA-0-0 (https://download.01.org/0day-ci/archive/20250117/202501171330.0mw1PLZh-lkp@intel.com/config)
reproduce: (https://download.01.org/0day-ci/archive/20250117/202501171330.0mw1PLZh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202501171330.0mw1PLZh-lkp@intel.com/
kismet warnings: (new ones prefixed by >>)
>> kismet: WARNING: unmet direct dependencies detected for I2C_GPIO when selected by VIDEO_MMP_CAMERA
WARNING: unmet direct dependencies detected for I2C_GPIO
Depends on [n]: I2C [=y] && HAS_IOMEM [=y] && (GPIOLIB [=n] || COMPILE_TEST [=n])
Selected by [y]:
- VIDEO_MMP_CAMERA [=y] && MEDIA_SUPPORT [=y] && MEDIA_PLATFORM_SUPPORT [=y] && MEDIA_PLATFORM_DRIVERS [=y] && V4L_PLATFORM_DRIVERS [=y] && I2C [=y] && VIDEO_DEV [=y] && (ARCH_MMP [=y] || COMPILE_TEST [=n]) && COMMON_CLK [=y]
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v14 3/4] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
-1 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
Edition LTE, a smartphone based on said SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/boot/dts/marvell/Makefile | 3 +
.../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++
3 files changed, 639 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index ce751b5028e2628834340b5c50f8992092226eba..39c5749e631db33aa8fb0386a951c0a70215bc02 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -32,3 +32,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
+
+# MMP SoC Family
+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
new file mode 100644
index 0000000000000000000000000000000000000000..83b789a837d3876bf15ed0d7e10e190eacdfd56f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "pxa1908.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "Samsung Galaxy Core Prime VE LTE";
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
+
+ aliases {
+ mmc0 = &sdh2; /* eMMC */
+ mmc1 = &sdh0; /* SD card */
+ serial0 = &uart0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ /* S-Boot places the initramfs here */
+ linux,initrd-start = <0x4d70000>;
+ linux,initrd-end = <0x5000000>;
+
+ fb0: framebuffer@17177000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
+ width = <480>;
+ height = <800>;
+ stride = <(480 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ /* Bootloader fills this in */
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@17000000 {
+ reg = <0 0x17000000 0 0x1800000>;
+ no-map;
+ };
+
+ gpu@9000000 {
+ reg = <0 0x9000000 0 0x1000000>;
+ };
+
+ /* Communications processor, aka modem */
+ cp@5000000 {
+ reg = <0 0x5000000 0 0x3000000>;
+ };
+
+ cm3@a000000 {
+ reg = <0 0xa000000 0 0x80000>;
+ };
+
+ seclog@8000000 {
+ reg = <0 0x8000000 0 0x100000>;
+ };
+
+ ramoops@8100000 {
+ compatible = "ramoops";
+ reg = <0 0x8100000 0 0x40000>;
+ record-size = <0x8000>;
+ console-size = <0x20000>;
+ max-reason = <5>;
+ };
+ };
+
+
+ i2c-muic {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <3>;
+ i2c-gpio,timeout-ms = <100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_muic_pins>;
+
+ muic: extcon@14 {
+ compatible = "siliconmitus,sm5504-muic";
+ reg = <0x14>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
+ };
+
+ key-volup {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ key-voldown {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pmx {
+ pinctrl-single,gpio-range = <&range 55 55 0>,
+ <&range 110 32 0>,
+ <&range 52 1 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins_0 &board_pins_1 &board_pins_2>;
+
+ board_pins_0: board-pins-0 {
+ pinctrl-single,pins = <
+ 0x160 0
+ 0x164 0
+ 0x168 0
+ 0x16c 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_1: board-pins-1 {
+ pinctrl-single,pins = <
+ 0x44 1
+ 0x48 1
+ 0x20 1
+ 0x18 1
+ 0x14 1
+ 0x10 1
+ 0xc 1
+ 0x8 1
+ 0x68 1
+ 0x58 0
+ 0x54 0
+ 0x7c 0
+ 0x6c 0
+ 0x70 0
+ 0x4c 1
+ 0x50 1
+ 0xac 0
+ 0x90 0
+ 0x8c 0
+ 0x88 0
+ 0x84 0
+ 0xc8 0
+ 0x128 0
+ 0x190 0
+ 0x194 0
+ 0x1a0 0
+ 0x114 0
+ 0x118 0
+ 0x1d8 0
+ 0x1e4 0
+ 0xe8 0
+ 0x100 0
+ 0x204 0
+ 0x210 0
+ 0x218 0
+ >;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_2: board-pins-2 {
+ pinctrl-single,pins = <
+ 0x260 0
+ 0x264 0
+ 0x268 0
+ 0x26c 0
+ 0x270 0
+ 0x274 0
+ 0x78 0
+ 0x74 0
+ 0xb0 1
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ uart0_pins: uart0-pins {
+ pinctrl-single,pins = <
+ 0x198 6
+ 0x19c 6
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ gpio_keys_pins: gpio-keys-pins {
+ pinctrl-single,pins = <
+ 0x11c 0
+ 0x120 0
+ 0x1a4 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ i2c_muic_pins: i2c-muic-pins {
+ pinctrl-single,pins = <
+ 0x154 0
+ 0x150 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ sdh0_pins_0: sdh0-pins-0 {
+ pinctrl-single,pins = <
+ 0x108 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_1: sdh0-pins-1 {
+ pinctrl-single,pins = <
+ 0x94 0
+ 0x98 0
+ 0x9c 0
+ 0xa0 0
+ 0xa4 0
+ >;
+ pinctrl-single,drive-strength = <0x800 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_2: sdh0-pins-2 {
+ pinctrl-single,pins = <
+ 0xa8 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x208 0x388>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&twsi0 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+};
+
+&twsi2 {
+ status = "okay";
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+};
+
+&sdh2 {
+ /* Disabled for now because initialization fails with -ETIMEDOUT. */
+ status = "disabled";
+ bus-width = <8>;
+ non-removable;
+ mmc-ddr-1_8v;
+};
+
+&sdh0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>;
+ cd-gpios = <&gpio 11 0>;
+ cd-inverted;
+ bus-width = <4>;
+ wp-inverted;
+};
diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cf2b9109688ce560eec8a1397251ead68d78a239
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+/ {
+ model = "Marvell Armada PXA1908";
+ compatible = "marvell,pxa1908";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 3>;
+ enable-method = "psci";
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smmu: iommu@c0010000 {
+ compatible = "arm,mmu-400";
+ reg = <0 0xc0010000 0 0x10000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@d1df9000 {
+ compatible = "arm,gic-400";
+ reg = <0 0xd1df9000 0 0x1000>,
+ <0 0xd1dfa000 0 0x2000>,
+ /* The subsequent registers are guesses. */
+ <0 0xd1dfc000 0 0x2000>,
+ <0 0xd1dfe000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4000000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4000000 0x200000>;
+
+ pdma: dma-controller@0 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <30>;
+ #dma-cells = <2>;
+ };
+
+ twsi1: i2c@10800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10800 0x64>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi0: i2c@11000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11000 0x64>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi3: i2c@13800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x13800 0x64>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI3>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbc: clock-controller@15000 {
+ compatible = "marvell,pxa1908-apbc";
+ reg = <0x15000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@17000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x17000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART0>;
+ reg-shift = <2>;
+ };
+
+ uart1: serial@18000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x18000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART1>;
+ reg-shift = <2>;
+ };
+
+ gpio: gpio@19000 {
+ compatible = "marvell,mmp-gpio";
+ reg = <0x19000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&apbc PXA1908_CLK_GPIO>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges = <0 0x19000 0x800>;
+
+ gpio@0 {
+ reg = <0x0 0x4>;
+ };
+
+ gpio@4 {
+ reg = <0x4 0x4>;
+ };
+
+ gpio@8 {
+ reg = <0x8 0x4>;
+ };
+
+ gpio@100 {
+ reg = <0x100 0x4>;
+ };
+ };
+
+ pmx: pinmux@1e000 {
+ compatible = "marvell,pxa1908-padconf", "pinconf-single";
+ reg = <0x1e000 0x330>;
+
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ uart2: serial@36000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x36000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_UART2>;
+ reg-shift = <2>;
+ };
+
+ twsi2: i2c@37000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x37000 0x64>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_TWSI2>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbcp: clock-controller@3b000 {
+ compatible = "marvell,pxa1908-apbcp";
+ reg = <0x3b000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mpmu: clock-controller@50000 {
+ compatible = "marvell,pxa1908-mpmu";
+ reg = <0x50000 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4200000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4200000 0x200000>;
+
+ usbphy: phy@7000 {
+ compatible = "marvell,pxa1928-usb-phy";
+ reg = <0x7000 0x200>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ usb: usb@8000 {
+ compatible = "chipidea,usb2";
+ reg = <0x8000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ phys = <&usbphy>;
+ phy-names = "usb-phy";
+ };
+
+ sdh0: mmc@80000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH0>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh1: mmc@80800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80800 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH1>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh2: mmc@81000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x81000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH2>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ apmu: clock-controller@82800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0x82800 0x400>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PATCH v14 3/4] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović via B4 Relay @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
From: Duje Mihanović <duje.mihanovic@skole.hr>
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
Edition LTE, a smartphone based on said SoC.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
arch/arm64/boot/dts/marvell/Makefile | 3 +
.../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++
3 files changed, 639 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index ce751b5028e2628834340b5c50f8992092226eba..39c5749e631db33aa8fb0386a951c0a70215bc02 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -32,3 +32,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
+
+# MMP SoC Family
+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
new file mode 100644
index 0000000000000000000000000000000000000000..83b789a837d3876bf15ed0d7e10e190eacdfd56f
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "pxa1908.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ model = "Samsung Galaxy Core Prime VE LTE";
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
+
+ aliases {
+ mmc0 = &sdh2; /* eMMC */
+ mmc1 = &sdh0; /* SD card */
+ serial0 = &uart0;
+ };
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ stdout-path = "serial0:115200n8";
+
+ /* S-Boot places the initramfs here */
+ linux,initrd-start = <0x4d70000>;
+ linux,initrd-end = <0x5000000>;
+
+ fb0: framebuffer@17177000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
+ width = <480>;
+ height = <800>;
+ stride = <(480 * 4)>;
+ format = "a8r8g8b8";
+ };
+ };
+
+ /* Bootloader fills this in */
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@17000000 {
+ reg = <0 0x17000000 0 0x1800000>;
+ no-map;
+ };
+
+ gpu@9000000 {
+ reg = <0 0x9000000 0 0x1000000>;
+ };
+
+ /* Communications processor, aka modem */
+ cp@5000000 {
+ reg = <0 0x5000000 0 0x3000000>;
+ };
+
+ cm3@a000000 {
+ reg = <0 0xa000000 0 0x80000>;
+ };
+
+ seclog@8000000 {
+ reg = <0 0x8000000 0 0x100000>;
+ };
+
+ ramoops@8100000 {
+ compatible = "ramoops";
+ reg = <0 0x8100000 0 0x40000>;
+ record-size = <0x8000>;
+ console-size = <0x20000>;
+ max-reason = <5>;
+ };
+ };
+
+
+ i2c-muic {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <3>;
+ i2c-gpio,timeout-ms = <100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_muic_pins>;
+
+ muic: extcon@14 {
+ compatible = "siliconmitus,sm5504-muic";
+ reg = <0x14>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
+ };
+
+ key-volup {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ key-voldown {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pmx {
+ pinctrl-single,gpio-range = <&range 55 55 0>,
+ <&range 110 32 0>,
+ <&range 52 1 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins_0 &board_pins_1 &board_pins_2>;
+
+ board_pins_0: board-pins-0 {
+ pinctrl-single,pins = <
+ 0x160 0
+ 0x164 0
+ 0x168 0
+ 0x16c 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_1: board-pins-1 {
+ pinctrl-single,pins = <
+ 0x44 1
+ 0x48 1
+ 0x20 1
+ 0x18 1
+ 0x14 1
+ 0x10 1
+ 0xc 1
+ 0x8 1
+ 0x68 1
+ 0x58 0
+ 0x54 0
+ 0x7c 0
+ 0x6c 0
+ 0x70 0
+ 0x4c 1
+ 0x50 1
+ 0xac 0
+ 0x90 0
+ 0x8c 0
+ 0x88 0
+ 0x84 0
+ 0xc8 0
+ 0x128 0
+ 0x190 0
+ 0x194 0
+ 0x1a0 0
+ 0x114 0
+ 0x118 0
+ 0x1d8 0
+ 0x1e4 0
+ 0xe8 0
+ 0x100 0
+ 0x204 0
+ 0x210 0
+ 0x218 0
+ >;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_2: board-pins-2 {
+ pinctrl-single,pins = <
+ 0x260 0
+ 0x264 0
+ 0x268 0
+ 0x26c 0
+ 0x270 0
+ 0x274 0
+ 0x78 0
+ 0x74 0
+ 0xb0 1
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ uart0_pins: uart0-pins {
+ pinctrl-single,pins = <
+ 0x198 6
+ 0x19c 6
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ gpio_keys_pins: gpio-keys-pins {
+ pinctrl-single,pins = <
+ 0x11c 0
+ 0x120 0
+ 0x1a4 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ i2c_muic_pins: i2c-muic-pins {
+ pinctrl-single,pins = <
+ 0x154 0
+ 0x150 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ sdh0_pins_0: sdh0-pins-0 {
+ pinctrl-single,pins = <
+ 0x108 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_1: sdh0-pins-1 {
+ pinctrl-single,pins = <
+ 0x94 0
+ 0x98 0
+ 0x9c 0
+ 0xa0 0
+ 0xa4 0
+ >;
+ pinctrl-single,drive-strength = <0x800 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_2: sdh0-pins-2 {
+ pinctrl-single,pins = <
+ 0xa8 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x208 0x388>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&twsi0 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+};
+
+&twsi2 {
+ status = "okay";
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+};
+
+&sdh2 {
+ /* Disabled for now because initialization fails with -ETIMEDOUT. */
+ status = "disabled";
+ bus-width = <8>;
+ non-removable;
+ mmc-ddr-1_8v;
+};
+
+&sdh0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdh0_pins_0 &sdh0_pins_1 &sdh0_pins_2>;
+ cd-gpios = <&gpio 11 0>;
+ cd-inverted;
+ bus-width = <4>;
+ wp-inverted;
+};
diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cf2b9109688ce560eec8a1397251ead68d78a239
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+/ {
+ model = "Marvell Armada PXA1908";
+ compatible = "marvell,pxa1908";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0 3>;
+ enable-method = "psci";
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smmu: iommu@c0010000 {
+ compatible = "arm,mmu-400";
+ reg = <0 0xc0010000 0 0x10000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@d1df9000 {
+ compatible = "arm,gic-400";
+ reg = <0 0xd1df9000 0 0x1000>,
+ <0 0xd1dfa000 0 0x2000>,
+ /* The subsequent registers are guesses. */
+ <0 0xd1dfc000 0 0x2000>,
+ <0 0xd1dfe000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4000000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4000000 0x200000>;
+
+ pdma: dma-controller@0 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <30>;
+ #dma-cells = <2>;
+ };
+
+ twsi1: i2c@10800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10800 0x64>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi0: i2c@11000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11000 0x64>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi3: i2c@13800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x13800 0x64>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI3>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbc: clock-controller@15000 {
+ compatible = "marvell,pxa1908-apbc";
+ reg = <0x15000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@17000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x17000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART0>;
+ reg-shift = <2>;
+ };
+
+ uart1: serial@18000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x18000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_UART1>;
+ reg-shift = <2>;
+ };
+
+ gpio: gpio@19000 {
+ compatible = "marvell,mmp-gpio";
+ reg = <0x19000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&apbc PXA1908_CLK_GPIO>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges = <0 0x19000 0x800>;
+
+ gpio@0 {
+ reg = <0x0 0x4>;
+ };
+
+ gpio@4 {
+ reg = <0x4 0x4>;
+ };
+
+ gpio@8 {
+ reg = <0x8 0x4>;
+ };
+
+ gpio@100 {
+ reg = <0x100 0x4>;
+ };
+ };
+
+ pmx: pinmux@1e000 {
+ compatible = "marvell,pxa1908-padconf", "pinconf-single";
+ reg = <0x1e000 0x330>;
+
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ uart2: serial@36000 {
+ compatible = "mrvl,mmp-uart", "intel,xscale-uart";
+ reg = <0x36000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_UART2>;
+ reg-shift = <2>;
+ };
+
+ twsi2: i2c@37000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x37000 0x64>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_TWSI2>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbcp: clock-controller@3b000 {
+ compatible = "marvell,pxa1908-apbcp";
+ reg = <0x3b000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mpmu: clock-controller@50000 {
+ compatible = "marvell,pxa1908-mpmu";
+ reg = <0x50000 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4200000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4200000 0x200000>;
+
+ usbphy: phy@7000 {
+ compatible = "marvell,pxa1928-usb-phy";
+ reg = <0x7000 0x200>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ usb: usb@8000 {
+ compatible = "chipidea,usb2";
+ reg = <0x8000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ phys = <&usbphy>;
+ phy-names = "usb-phy";
+ };
+
+ sdh0: mmc@80000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH0>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh1: mmc@80800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80800 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH1>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh2: mmc@81000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x81000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH2>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ apmu: clock-controller@82800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0x82800 0x400>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH v14 3/4] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
(?)
@ 2025-01-16 8:00 ` Krzysztof Kozlowski
2025-01-16 15:26 ` Duje Mihanović
-1 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-16 8:00 UTC (permalink / raw)
To: Duje Mihanović
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On Wed, Jan 15, 2025 at 09:35:56PM +0100, Duje Mihanović wrote:
> Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
> Edition LTE, a smartphone based on said SoC.
>
> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> ---
> arch/arm64/boot/dts/marvell/Makefile | 3 +
> .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
> arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++
> 3 files changed, 639 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index ce751b5028e2628834340b5c50f8992092226eba..39c5749e631db33aa8fb0386a951c0a70215bc02 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -32,3 +32,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
> +
> +# MMP SoC Family
> +dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
Hm, why separate ARCH if this is part of Marvell Makefile? One ARCH per
vendor, so if you think this is different than MVEBU, then should be in
a separate subdirectory of marvell.
> diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..83b789a837d3876bf15ed0d7e10e190eacdfd56f
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
> @@ -0,0 +1,336 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +#include "pxa1908.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +
> +/ {
> + model = "Samsung Galaxy Core Prime VE LTE";
> + compatible = "samsung,coreprimevelte", "marvell,pxa1908";
> +
> + aliases {
> + mmc0 = &sdh2; /* eMMC */
> + mmc1 = &sdh0; /* SD card */
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + stdout-path = "serial0:115200n8";
> +
> + /* S-Boot places the initramfs here */
> + linux,initrd-start = <0x4d70000>;
> + linux,initrd-end = <0x5000000>;
> +
> + fb0: framebuffer@17177000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x17177000 0 (480 * 800 * 4)>;
> + width = <480>;
> + height = <800>;
> + stride = <(480 * 4)>;
> + format = "a8r8g8b8";
> + };
> + };
> +
> + /* Bootloader fills this in */
> + memory {
> + device_type = "memory";
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + framebuffer@17000000 {
> + reg = <0 0x17000000 0 0x1800000>;
> + no-map;
> + };
> +
> + gpu@9000000 {
> + reg = <0 0x9000000 0 0x1000000>;
> + };
> +
> + /* Communications processor, aka modem */
> + cp@5000000 {
> + reg = <0 0x5000000 0 0x3000000>;
> + };
> +
> + cm3@a000000 {
> + reg = <0 0xa000000 0 0x80000>;
> + };
> +
> + seclog@8000000 {
> + reg = <0 0x8000000 0 0x100000>;
> + };
> +
> + ramoops@8100000 {
> + compatible = "ramoops";
> + reg = <0 0x8100000 0 0x40000>;
> + record-size = <0x8000>;
> + console-size = <0x20000>;
> + max-reason = <5>;
> + };
> + };
> +
> +
If there is going to be resend/new version:
Just one blank line.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH v14 3/4] arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
2025-01-16 8:00 ` Krzysztof Kozlowski
@ 2025-01-16 15:26 ` Duje Mihanović
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović @ 2025-01-16 15:26 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On Thursday 16 January 2025 09:00:40 Central European Standard Time Krzysztof
Kozlowski wrote:
> On Wed, Jan 15, 2025 at 09:35:56PM +0100, Duje Mihanović wrote:
> > Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
> > Edition LTE, a smartphone based on said SoC.
> >
> > Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> > ---
> >
> > arch/arm64/boot/dts/marvell/Makefile | 3 +
> > .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336
> > +++++++++++++++++++++ arch/arm64/boot/dts/marvell/pxa1908.dtsi
|
> > 300 ++++++++++++++++++ 3 files changed, 639 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/marvell/Makefile
> > b/arch/arm64/boot/dts/marvell/Makefile index
> > ce751b5028e2628834340b5c50f8992092226eba..
39c5749e631db33aa8fb0386a951c0a70
> > 215bc02 100644 --- a/arch/arm64/boot/dts/marvell/Makefile
> > +++ b/arch/arm64/boot/dts/marvell/Makefile
> > @@ -32,3 +32,6 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
> >
> > dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
> > dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
> > dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
> >
> > +
> > +# MMP SoC Family
> > +dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
>
> Hm, why separate ARCH if this is part of Marvell Makefile? One ARCH per
> vendor, so if you think this is different than MVEBU, then should be in
> a separate subdirectory of marvell.
I see, for v15 I'll put these in a mmp/ subdir.
> > +
> > + ramoops@8100000 {
> > + compatible = "ramoops";
> > + reg = <0 0x8100000 0 0x40000>;
> > + record-size = <0x8000>;
> > + console-size = <0x20000>;
> > + max-reason = <5>;
> > + };
> > + };
> > +
> > +
>
> If there is going to be resend/new version:
> Just one blank line.
Will fix.
Regards,
--
Duje
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v14 4/4] MAINTAINERS: add myself as Marvell PXA1908 maintainer
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
-1 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
Add myself as the maintainer for Marvell PXA1908 SoC support.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a87ddad78e26f28ffd0f3433560d6db1518f9f95..caa5f6b96251a3da0f3f9d2f760b38288eb23ab3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2624,6 +2624,15 @@ F: drivers/irqchip/irq-mvebu-*
F: drivers/pinctrl/mvebu/
F: drivers/rtc/rtc-armada38x.c
+ARM/Marvell PXA1908 SOC support
+M: Duje Mihanović <duje.mihanovic@skole.hr>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+T: git https://gitlab.com/LegoLivesMatter/linux
+F: arch/arm64/boot/dts/marvell/pxa1908*
+F: drivers/clk/mmp/clk-pxa1908*.c
+F: include/dt-bindings/clock/marvell,pxa1908.h
+
ARM/Mediatek RTC DRIVER
M: Eddie Huang <eddie.huang@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v14 4/4] MAINTAINERS: add myself as Marvell PXA1908 maintainer
@ 2025-01-15 20:35 ` Duje Mihanović via B4 Relay
0 siblings, 0 replies; 20+ messages in thread
From: Duje Mihanović via B4 Relay @ 2025-01-15 20:35 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli
Cc: David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming, Duje Mihanović
From: Duje Mihanović <duje.mihanovic@skole.hr>
Add myself as the maintainer for Marvell PXA1908 SoC support.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a87ddad78e26f28ffd0f3433560d6db1518f9f95..caa5f6b96251a3da0f3f9d2f760b38288eb23ab3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2624,6 +2624,15 @@ F: drivers/irqchip/irq-mvebu-*
F: drivers/pinctrl/mvebu/
F: drivers/rtc/rtc-armada38x.c
+ARM/Marvell PXA1908 SOC support
+M: Duje Mihanović <duje.mihanovic@skole.hr>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+T: git https://gitlab.com/LegoLivesMatter/linux
+F: arch/arm64/boot/dts/marvell/pxa1908*
+F: drivers/clk/mmp/clk-pxa1908*.c
+F: include/dt-bindings/clock/marvell,pxa1908.h
+
ARM/Mediatek RTC DRIVER
M: Eddie Huang <eddie.huang@mediatek.com>
M: Sean Wang <sean.wang@mediatek.com>
--
2.48.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v14 4/4] MAINTAINERS: add myself as Marvell PXA1908 maintainer
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
(?)
@ 2025-01-16 7:56 ` Krzysztof Kozlowski
2025-01-16 15:47 ` Duje Mihanović
-1 siblings, 1 reply; 20+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-16 7:56 UTC (permalink / raw)
To: Duje Mihanović
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On Wed, Jan 15, 2025 at 09:35:57PM +0100, Duje Mihanović wrote:
> Add myself as the maintainer for Marvell PXA1908 SoC support.
>
> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> ---
> MAINTAINERS | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a87ddad78e26f28ffd0f3433560d6db1518f9f95..caa5f6b96251a3da0f3f9d2f760b38288eb23ab3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -2624,6 +2624,15 @@ F: drivers/irqchip/irq-mvebu-*
> F: drivers/pinctrl/mvebu/
> F: drivers/rtc/rtc-armada38x.c
>
> +ARM/Marvell PXA1908 SOC support
> +M: Duje Mihanović <duje.mihanovic@skole.hr>
> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> +S: Maintained
> +T: git https://gitlab.com/LegoLivesMatter/linux
Not sure if this was mentioned ever (it is v14, so it is likely) but if
that was not clear:
Pull requests from non-kernel.org repos must be signed and your key must
be in kernel.org keyring. Please get your key signed
(meetups/conferences/keysigning map/video confcalls) and submitted to
the keyring.
Patchset should be sent to soc@, as expressed in soc@ maintainer
profile.
Unless this is not going to be merged by soc@, but someone from Marvell
maintainers, but then please drop the repo. Git repos here are for
managing patches.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v14 4/4] MAINTAINERS: add myself as Marvell PXA1908 maintainer
2025-01-16 7:56 ` Krzysztof Kozlowski
@ 2025-01-16 15:47 ` Duje Mihanović
2025-01-16 20:22 ` Krzysztof Kozlowski
0 siblings, 1 reply; 20+ messages in thread
From: Duje Mihanović @ 2025-01-16 15:47 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On Thursday 16 January 2025 08:56:24 Central European Standard Time Krzysztof
Kozlowski wrote:
> On Wed, Jan 15, 2025 at 09:35:57PM +0100, Duje Mihanović wrote:
> > Add myself as the maintainer for Marvell PXA1908 SoC support.
> >
> > Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> > ---
> >
> > MAINTAINERS | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index
> >
a87ddad78e26f28ffd0f3433560d6db1518f9f95..caa5f6b96251a3da0f3f9d2f760b38288
> > eb23ab3 100644 --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -2624,6 +2624,15 @@ F: drivers/irqchip/irq-mvebu-*
> >
> > F: drivers/pinctrl/mvebu/
> > F: drivers/rtc/rtc-armada38x.c
> >
> > +ARM/Marvell PXA1908 SOC support
> > +M: Duje Mihanović <duje.mihanovic@skole.hr>
> > +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
> > +S: Maintained
> > +T: git https://gitlab.com/LegoLivesMatter/linux
>
> Not sure if this was mentioned ever (it is v14, so it is likely) but if
> that was not clear:
>
> Pull requests from non-kernel.org repos must be signed and your key must
> be in kernel.org keyring. Please get your key signed
> (meetups/conferences/keysigning map/video confcalls) and submitted to
> the keyring.
>
> Patchset should be sent to soc@, as expressed in soc@ maintainer
> profile.
>
> Unless this is not going to be merged by soc@, but someone from Marvell
> maintainers, but then please drop the repo. Git repos here are for
> managing patches.
I didn't know about Git repos being used for patch management, thanks for
letting me know.
I believe this is best merged by soc@ since it is not mvebu and is the first
arm64 MMP to be merged. However, for various reasons I'd prefer not to have my
key signed quite yet, so would it be possible for this to get merged through
soc@ if I removed the repo?
Also, I will certainly add soc@ to the Cc list in v15.
Regards,
--
Duje
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v14 4/4] MAINTAINERS: add myself as Marvell PXA1908 maintainer
2025-01-16 15:47 ` Duje Mihanović
@ 2025-01-16 20:22 ` Krzysztof Kozlowski
0 siblings, 0 replies; 20+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-16 20:22 UTC (permalink / raw)
To: Duje Mihanović
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Lubomir Rintel,
Catalin Marinas, Will Deacon, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Kees Cook, Tony Luck, Guilherme G. Piccoli,
David Wronek, Karel Balej, devicetree, linux-kernel,
linux-arm-kernel, linux-hardening, phone-devel,
~postmarketos/upstreaming
On 16/01/2025 16:47, Duje Mihanović wrote:
>>>
>>> +ARM/Marvell PXA1908 SOC support
>>> +M: Duje Mihanović <duje.mihanovic@skole.hr>
>>> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
>>> +S: Maintained
>>> +T: git https://gitlab.com/LegoLivesMatter/linux
>>
>> Not sure if this was mentioned ever (it is v14, so it is likely) but if
>> that was not clear:
>>
>> Pull requests from non-kernel.org repos must be signed and your key must
>> be in kernel.org keyring. Please get your key signed
>> (meetups/conferences/keysigning map/video confcalls) and submitted to
>> the keyring.
>>
>> Patchset should be sent to soc@, as expressed in soc@ maintainer
>> profile.
>>
>> Unless this is not going to be merged by soc@, but someone from Marvell
>> maintainers, but then please drop the repo. Git repos here are for
>> managing patches.
>
> I didn't know about Git repos being used for patch management, thanks for
> letting me know.
>
> I believe this is best merged by soc@ since it is not mvebu and is the first
> arm64 MMP to be merged. However, for various reasons I'd prefer not to have my
> key signed quite yet, so would it be possible for this to get merged through
> soc@ if I removed the repo?
Merging this now is independent of signed keys, so there is no problem
in that.
But after that, if you are maintainer handling patches, then the repo
url would be useful here. It would be used for picking up patches,
because it's you who supposed to do that. SoC is not for patches from
contributors. In general SoC is only for other maintainers.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v14 0/4] Initial Marvell PXA1908 support
2025-01-15 20:35 ` Duje Mihanović via B4 Relay
` (4 preceding siblings ...)
(?)
@ 2025-01-16 14:02 ` Rob Herring (Arm)
-1 siblings, 0 replies; 20+ messages in thread
From: Rob Herring (Arm) @ 2025-01-16 14:02 UTC (permalink / raw)
To: Duje Mihanović
Cc: Sebastian Hesselbarth, David Wronek, Kees Cook, Catalin Marinas,
Krzysztof Kozlowski, Conor Dooley, Andrew Lunn, Will Deacon,
Karel Balej, devicetree, Lubomir Rintel, phone-devel,
Krzysztof Kozlowski, ~postmarketos/upstreaming, linux-hardening,
Guilherme G. Piccoli, linux-kernel, linux-arm-kernel,
Gregory Clement, Tony Luck
On Wed, 15 Jan 2025 21:35:53 +0100, Duje Mihanović wrote:
> Hello,
>
> This series adds initial support for the Marvell PXA1908 SoC and
> "samsung,coreprimevelte", a smartphone using the SoC.
>
> USB works and the phone can boot a rootfs from an SD card, but there are
> some warnings in the dmesg:
>
> During SMP initialization:
> [ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
> [ 0.006542] CPU features: Unsupported CPU feature variation detected.
> [ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032]
> [ 0.010710] Detected VIPT I-cache on CPU2
> [ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
> [ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032]
> [ 0.014849] Detected VIPT I-cache on CPU3
> [ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
> [ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032]
>
> SMMU probing fails:
> [ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration...
> [ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with:
> [ 0.101816] arm-smmu c0010000.iommu: no translation support!
>
> A 3.14 based Marvell tree is available on GitHub
> acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub
> CoderCharmander/g361f-kernel.
>
> Andreas Färber attempted to upstream support for this SoC in 2017:
> https://lore.kernel.org/lkml/20170222022929.10540-1-afaerber@suse.de/
>
> Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
> ---
> Changes in v14:
> - Rebase on v6.13-rc7, dropping everything except DT
> - Link to v13: https://lore.kernel.org/r/20241001-pxa1908-lkml-v13-0-6b9a7f64f9ae@skole.hr
>
> Changes in v13:
> - Better describe the hardware in bindings/arm commit message
> - Rebase on v6.12-rc1
> - Link to v12: https://lore.kernel.org/r/20240823-pxa1908-lkml-v12-0-cc3ada51beb0@skole.hr
>
> Changes in v12:
> - Rebase on v6.11-rc4
> - Fix schmitt properties in accordance with 78d8815031fb ("dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties")
> - Drop a few redundant includes in clock drivers
> - Link to v11: https://lore.kernel.org/r/20240730-pxa1908-lkml-v11-0-21dbb3e28793@skole.hr
>
> Changes in v11:
> - Rebase on v6.11-rc1 (conflict with DTS Makefile), no changes
> - Link to v10: https://lore.kernel.org/r/20240424-pxa1908-lkml-v10-0-36cdfb5841f9@skole.hr
>
> Changes in v10:
> - Update trailers
> - Rebase on v6.9-rc5
> - Clock driver changes:
> - Add a couple of forgotten clocks in APBC
> - The clocks are thermal_clk, ipc_clk, ssp0_clk, ssp2_clk and swjtag
> - The IDs and register offsets were already present, but I forgot to
> actually register them
> - Split each controller block into own file
> - Drop unneeded -of in clock driver filenames
> - Simplify struct pxa1908_clk_unit
> - Convert to platform driver
> - Add module metadata
> - DTS changes:
> - Properly name pinctrl nodes
> - Drop pinctrl #size-cells, #address-cells, ranges and #gpio-size-cells
> - Fix pinctrl input-schmitt configuration
> - Link to v9: https://lore.kernel.org/20240402-pxa1908-lkml-v9-0-25a003e83c6f@skole.hr
>
> Changes in v9:
> - Update trailers and rebase on v6.9-rc2, no changes
> - Link to v8: https://lore.kernel.org/20240110-pxa1908-lkml-v8-0-fea768a59474@skole.hr
>
> Changes in v8:
> - Drop SSPA patch
> - Drop broken-cd from eMMC node
> - Specify S-Boot hardcoded initramfs location in device tree
> - Add ARM PMU node
> - Correct inverted modem memory base and size
> - Update trailers
> - Rebase on next-20240110
> - Link to v7: https://lore.kernel.org/20231102-pxa1908-lkml-v7-0-cabb1a0cb52b@skole.hr
> and https://lore.kernel.org/20231102152033.5511-1-duje.mihanovic@skole.hr
>
> Changes in v7:
> - Suppress SND_MMP_SOC_SSPA on ARM64
> - Update trailers
> - Rebase on v6.6-rc7
> - Link to v6: https://lore.kernel.org/r/20231010-pxa1908-lkml-v6-0-b2fe09240cf8@skole.hr
>
> Changes in v6:
> - Address maintainer comments:
> - Add "marvell,pxa1908-padconf" binding to pinctrl-single driver
> - Drop GPIO patch as it's been pulled
> - Update trailers
> - Rebase on v6.6-rc5
> - Link to v5: https://lore.kernel.org/r/20230812-pxa1908-lkml-v5-0-a5d51937ee34@skole.hr
>
> Changes in v5:
> - Address maintainer comments:
> - Move *_NR_CLKS to clock driver from dt binding file
> - Allocate correct number of clocks for each block instead of blindly
> allocating 50 for each
> - Link to v4: https://lore.kernel.org/r/20230807-pxa1908-lkml-v4-0-cb387d73b452@skole.hr
>
> Changes in v4:
> - Address maintainer comments:
> - Relicense clock binding file to BSD-2
> - Add pinctrl-names to SD card node
> - Add vgic registers to GIC node
> - Rebase on v6.5-rc5
> - Link to v3: https://lore.kernel.org/r/20230804-pxa1908-lkml-v3-0-8e48fca37099@skole.hr
>
> Changes in v3:
> - Address maintainer comments:
> - Drop GPIO dynamic allocation patch
> - Move clock register offsets into driver (instead of bindings file)
> - Add missing Tested-by trailer to u32_fract patch
> - Move SoC binding to arm/mrvl/mrvl.yaml
> - Add serial0 alias and stdout-path to board dts to enable UART
> debugging
> - Rebase on v6.5-rc4
> - Link to v2: https://lore.kernel.org/r/20230727162909.6031-1-duje.mihanovic@skole.hr
>
> Changes in v2:
> - Remove earlycon patch as it's been merged into tty-next
> - Address maintainer comments:
> - Clarify GPIO regressions on older PXA platforms
> - Add Fixes tag to commit disabling GPIO pinctrl calls for this SoC
> - Add missing includes to clock driver
> - Clock driver uses HZ_PER_MHZ, u32_fract and GENMASK
> - Dual license clock bindings
> - Change clock IDs to decimal
> - Fix underscores in dt node names
> - Move chosen node to top of board dts
> - Clean up documentation
> - Reorder commits
> - Drop pxa,rev-id
> - Rename muic-i2c to i2c-muic
> - Reword some commits
> - Move framebuffer node to chosen
> - Add aliases for mmc nodes
> - Rebase on v6.5-rc3
> - Link to v1: https://lore.kernel.org/r/20230721210042.21535-1-duje.mihanovic@skole.hr
>
> ---
> Duje Mihanović (4):
> dt-bindings: marvell: Document PXA1908 SoC and samsung,coreprimevelte
> arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
> arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
> MAINTAINERS: add myself as Marvell PXA1908 maintainer
>
> .../devicetree/bindings/arm/mrvl/mrvl.yaml | 5 +
> MAINTAINERS | 9 +
> arch/arm64/Kconfig.platforms | 8 +
> arch/arm64/boot/dts/marvell/Makefile | 3 +
> .../dts/marvell/pxa1908-samsung-coreprimevelte.dts | 336 +++++++++++++++++++++
> arch/arm64/boot/dts/marvell/pxa1908.dtsi | 300 ++++++++++++++++++
> 6 files changed, 661 insertions(+)
> ---
> base-commit: 5bc55a333a2f7316b58edc7573e8e893f7acb532
> change-id: 20230803-pxa1908-lkml-6830e8da45c7
>
> Best regards,
> --
> Duje Mihanović <duje.mihanovic@skole.hr>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/marvell/' for 20250115-pxa1908-lkml-v14-0-847d24f3665a@skole.hr:
arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dtb: /: memory: False schema does not allow {'device_type': ['memory'], 'reg': [[0, 0, 0, 0]]}
from schema $id: http://devicetree.org/schemas/root-node.yaml#
arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dtb: mmc@80000: pinctrl-names: ['default'] is too short
from schema $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dtb: mmc@80000: Unevaluated properties are not allowed ('pinctrl-names' was unexpected)
from schema $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
^ permalink raw reply [flat|nested] 20+ messages in thread