Re: [RFC] MIPS: Add cacheinfo support

[Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>]

On 12/12/2016 01:57 PM, Florian Fainelli wrote:
> OK, how would you want that to be represented? Should we try to "link"
> with the leaf we are coherent with? For instance, if the L1D cache is
> coherent with the L2, we have something like this:
>
> # Assuming this is L1D cache:
> /sys/devices/system/cpu/cpu0/cache/index0
> ls -1
> coherency_line_size
> level
> number_of_sets
> physical_line_partition
> power/
> shared_cpu_list
> shared_cpu_map
> size
> type
> uevent
> ways_of_associativity
>
> We add a new symbolic link, e.g:
>
> coherent_with -> ../index1
>
> that indicates that this cache is coherent with the cache pointed at by
> directory index1.
>
> Thanks!
Well, I prefer the collection of 3 flags:

flush_required        - or flush to next level is required to force 
coherency between this level and next after update of this level
invalidate_required   - or invalidate is required to force coherency 
between this level and next after update of next level
coherent_to_level     - object is coherent with this level (only one 
domain of coherency on this level is assumed)

So, the standard MIPS L1D could be "flush_required", 
"invalidate_required" and "coherent_to_level", L1I could be 
"invalidate_required" and a fully coherent MIPS I6400 L1D could be just 
"coherent_to_level" (no flush/invalidate required).

The reason why I don't like symlink here because it is more precise 
information and it immediately pulls the question "do we need to have 
horizontal links like CPU0 L1D is coherent with CPU1 L1D?" or "do we 
need to have a horizontal link like CPU0 L1D is coherent with CPU1 L1I?" 
or "do we have a MEMORY object?" or "what if coherency is not 
bidirectional (L1D snoops L2 but not vise versa). And you should 
maintain that links in case of CPU goes on/offline. And pulling info 
from that link net is nontrivial in user level, especially if "lshw" 
works in parallel with CPUx going offline.

But what you need is actually the answer on that 3 questions (see flags 
above). At least I don't see a reason for more complicated cache level 
relationship. Even the case BIG-LITTLE still is covered by flags.

- Leonid.