* [Qemu-devel] [PATCH v4 0/2] pcie_aer modification
@ 2016-12-21 8:21 Cao jin
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error Cao jin
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version Cao jin
0 siblings, 2 replies; 6+ messages in thread
From: Cao jin @ 2016-12-21 8:21 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, dmitry, jasowang
Because these 2 patches target to the same function, so put them together.
Cao's patch is simply a copy of v3; Dou's patch is taken from AER series,
rebase on Cao's, it would be no trouble letting it in first.
Both have been reviewed.
v4 changelog:
1. simply put 2 reviewed patch into a series
2. rebase & add the reviewer's R-b.
Test:
1. make check pass.
2. command line test with -device ioh3420,aer_log_max=0xffff/0/10/-1,
the results meet the expectation.
Cao jin (1):
pcie_aer: Convert pcie_aer_init to Error
Dou Liyang (1):
pcie_aer: support configurable AER capa version
hw/net/e1000e.c | 3 ++-
hw/pci-bridge/ioh3420.c | 4 +++-
hw/pci-bridge/xio3130_downstream.c | 4 +++-
hw/pci-bridge/xio3130_upstream.c | 4 +++-
hw/pci/pcie_aer.c | 19 ++++++++-----------
include/hw/pci/pcie_aer.h | 4 ++--
6 files changed, 21 insertions(+), 17 deletions(-)
--
2.1.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error
2016-12-21 8:21 [Qemu-devel] [PATCH v4 0/2] pcie_aer modification Cao jin
@ 2016-12-21 8:21 ` Cao jin
2016-12-22 15:00 ` Dmitry Fleytman
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version Cao jin
1 sibling, 1 reply; 6+ messages in thread
From: Cao jin @ 2016-12-21 8:21 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, dmitry, jasowang
When user specify invalid value for property aer_log_max, device should
fail to create, and report appropriate message.
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
Acked-by: Dmitry Fleytman <dmitry@daynix.com>
---
hw/net/e1000e.c | 2 +-
hw/pci-bridge/ioh3420.c | 3 ++-
hw/pci-bridge/xio3130_downstream.c | 3 ++-
hw/pci-bridge/xio3130_upstream.c | 3 ++-
hw/pci/pcie_aer.c | 17 +++++++----------
include/hw/pci/pcie_aer.h | 4 ++--
6 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index 4994e1ca0062..89f96eb4a076 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -472,7 +472,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
hw_error("Failed to initialize PM capability");
}
- if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) {
+ if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
hw_error("Failed to initialize AER capability");
}
diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
index c8b5ac4207c5..04180af79471 100644
--- a/hw/pci-bridge/ioh3420.c
+++ b/hw/pci-bridge/ioh3420.c
@@ -135,8 +135,9 @@ static int ioh3420_initfn(PCIDevice *d)
goto err_pcie_cap;
}
- rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF);
+ rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) {
+ error_report_err(err);
goto err;
}
pcie_aer_root_init(d);
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index cef6e1325ebf..571334185b42 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -97,8 +97,9 @@ static int xio3130_downstream_initfn(PCIDevice *d)
goto err_pcie_cap;
}
- rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
+ rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) {
+ error_report_err(err);
goto err;
}
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 4ad0440aa164..94c16910069e 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -85,8 +85,9 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_flr_init(d);
pcie_cap_deverr_init(d);
- rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
+ rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
if (rc < 0) {
+ error_report_err(err);
goto err;
}
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 048ce6a42455..2a4bd5aef639 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -29,6 +29,7 @@
#include "hw/pci/msi.h"
#include "hw/pci/pci_bus.h"
#include "hw/pci/pcie_regs.h"
+#include "qapi/error.h"
//#define DEBUG_PCIE
#ifdef DEBUG_PCIE
@@ -96,21 +97,17 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
aer_log->log_num = 0;
}
-int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size)
+int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
+ Error **errp)
{
- PCIExpressDevice *exp;
-
pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
offset, size);
- exp = &dev->exp;
- exp->aer_cap = offset;
+ dev->exp.aer_cap = offset;
- /* log_max is property */
- if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
- dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
- }
- /* clip down the value to avoid unreasobale memory usage */
+ /* clip down the value to avoid unreasonable memory usage */
if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
+ error_setg(errp, "Invalid aer_log_max %d. The max number of aer log "
+ "is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT);
return -EINVAL;
}
dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] *
diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
index c2ee4e2bdbfc..5891b6816e85 100644
--- a/include/hw/pci/pcie_aer.h
+++ b/include/hw/pci/pcie_aer.h
@@ -44,7 +44,6 @@ struct PCIEAERLog {
*/
#define PCIE_AER_LOG_MAX_DEFAULT 8
#define PCIE_AER_LOG_MAX_LIMIT 128
-#define PCIE_AER_LOG_MAX_UNSET 0xffff
uint16_t log_max;
/* Error log. log_max-sized array */
@@ -87,7 +86,8 @@ struct PCIEAERErr {
extern const VMStateDescription vmstate_pcie_aer_log;
-int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size);
+int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
+ Error **errp);
void pcie_aer_exit(PCIDevice *dev);
void pcie_aer_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len);
--
2.1.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version
2016-12-21 8:21 [Qemu-devel] [PATCH v4 0/2] pcie_aer modification Cao jin
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error Cao jin
@ 2016-12-21 8:21 ` Cao jin
2017-01-10 3:27 ` Michael S. Tsirkin
1 sibling, 1 reply; 6+ messages in thread
From: Cao jin @ 2016-12-21 8:21 UTC (permalink / raw)
To: qemu-devel; +Cc: mst, marcel, dmitry, jasowang, Dou Liyang
From: Dou Liyang <douly.fnst@cn.fujitsu.com>
Now, AER capa version is fixed to v2, if assigned device isn't v2,
then this value will be inconsistent between guest and host
Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/net/e1000e.c | 3 ++-
hw/pci-bridge/ioh3420.c | 3 ++-
hw/pci-bridge/xio3130_downstream.c | 3 ++-
hw/pci-bridge/xio3130_upstream.c | 3 ++-
hw/pci/pcie_aer.c | 6 +++---
include/hw/pci/pcie_aer.h | 4 ++--
6 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
index 89f96eb4a076..77a4b3e5bf9d 100644
--- a/hw/net/e1000e.c
+++ b/hw/net/e1000e.c
@@ -472,7 +472,8 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
hw_error("Failed to initialize PM capability");
}
- if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
+ if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
+ PCI_ERR_SIZEOF, NULL) < 0) {
hw_error("Failed to initialize AER capability");
}
diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
index 04180af79471..84b7946c3136 100644
--- a/hw/pci-bridge/ioh3420.c
+++ b/hw/pci-bridge/ioh3420.c
@@ -135,7 +135,8 @@ static int ioh3420_initfn(PCIDevice *d)
goto err_pcie_cap;
}
- rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
+ rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET,
+ PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;
diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 571334185b42..04b8e5b8479e 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -97,7 +97,8 @@ static int xio3130_downstream_initfn(PCIDevice *d)
goto err_pcie_cap;
}
- rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
+ rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
+ PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;
diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 94c16910069e..d1f59c883477 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -85,7 +85,8 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_flr_init(d);
pcie_cap_deverr_init(d);
- rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
+ rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
+ PCI_ERR_SIZEOF, &err);
if (rc < 0) {
error_report_err(err);
goto err;
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index 2a4bd5aef639..daf1f65427c2 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -97,10 +97,10 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
aer_log->log_num = 0;
}
-int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
- Error **errp)
+int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
+ uint16_t size, Error **errp)
{
- pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
+ pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
offset, size);
dev->exp.aer_cap = offset;
diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
index 5891b6816e85..526802bd312b 100644
--- a/include/hw/pci/pcie_aer.h
+++ b/include/hw/pci/pcie_aer.h
@@ -86,8 +86,8 @@ struct PCIEAERErr {
extern const VMStateDescription vmstate_pcie_aer_log;
-int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
- Error **errp);
+int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
+ uint16_t size, Error **errp);
void pcie_aer_exit(PCIDevice *dev);
void pcie_aer_write_config(PCIDevice *dev,
uint32_t addr, uint32_t val, int len);
--
2.1.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error Cao jin
@ 2016-12-22 15:00 ` Dmitry Fleytman
0 siblings, 0 replies; 6+ messages in thread
From: Dmitry Fleytman @ 2016-12-22 15:00 UTC (permalink / raw)
To: Cao jin; +Cc: qemu-devel, mst, marcel, jasowang
Acked-by: Dmitry Fleytman <dmitry@daynix.com>
> On 21 Dec 2016, at 10:21 AM, Cao jin <caoj.fnst@cn.fujitsu.com> wrote:
>
> When user specify invalid value for property aer_log_max, device should
> fail to create, and report appropriate message.
>
> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
> Acked-by: Dmitry Fleytman <dmitry@daynix.com>
> ---
> hw/net/e1000e.c | 2 +-
> hw/pci-bridge/ioh3420.c | 3 ++-
> hw/pci-bridge/xio3130_downstream.c | 3 ++-
> hw/pci-bridge/xio3130_upstream.c | 3 ++-
> hw/pci/pcie_aer.c | 17 +++++++----------
> include/hw/pci/pcie_aer.h | 4 ++--
> 6 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
> index 4994e1ca0062..89f96eb4a076 100644
> --- a/hw/net/e1000e.c
> +++ b/hw/net/e1000e.c
> @@ -472,7 +472,7 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
> hw_error("Failed to initialize PM capability");
> }
>
> - if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF) < 0) {
> + if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
> hw_error("Failed to initialize AER capability");
> }
>
> diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
> index c8b5ac4207c5..04180af79471 100644
> --- a/hw/pci-bridge/ioh3420.c
> +++ b/hw/pci-bridge/ioh3420.c
> @@ -135,8 +135,9 @@ static int ioh3420_initfn(PCIDevice *d)
> goto err_pcie_cap;
> }
>
> - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF);
> + rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> + error_report_err(err);
> goto err;
> }
> pcie_aer_root_init(d);
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index cef6e1325ebf..571334185b42 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -97,8 +97,9 @@ static int xio3130_downstream_initfn(PCIDevice *d)
> goto err_pcie_cap;
> }
>
> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
> + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> + error_report_err(err);
> goto err;
> }
>
> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
> index 4ad0440aa164..94c16910069e 100644
> --- a/hw/pci-bridge/xio3130_upstream.c
> +++ b/hw/pci-bridge/xio3130_upstream.c
> @@ -85,8 +85,9 @@ static int xio3130_upstream_initfn(PCIDevice *d)
> pcie_cap_flr_init(d);
> pcie_cap_deverr_init(d);
>
> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF);
> + rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> + error_report_err(err);
> goto err;
> }
>
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 048ce6a42455..2a4bd5aef639 100644
> --- a/hw/pci/pcie_aer.c
> +++ b/hw/pci/pcie_aer.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/msi.h"
> #include "hw/pci/pci_bus.h"
> #include "hw/pci/pcie_regs.h"
> +#include "qapi/error.h"
>
> //#define DEBUG_PCIE
> #ifdef DEBUG_PCIE
> @@ -96,21 +97,17 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
> aer_log->log_num = 0;
> }
>
> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size)
> +int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
> + Error **errp)
> {
> - PCIExpressDevice *exp;
> -
> pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
> offset, size);
> - exp = &dev->exp;
> - exp->aer_cap = offset;
> + dev->exp.aer_cap = offset;
>
> - /* log_max is property */
> - if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
> - dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
> - }
> - /* clip down the value to avoid unreasobale memory usage */
> + /* clip down the value to avoid unreasonable memory usage */
> if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
> + error_setg(errp, "Invalid aer_log_max %d. The max number of aer log "
> + "is %d", dev->exp.aer_log.log_max, PCIE_AER_LOG_MAX_LIMIT);
> return -EINVAL;
> }
> dev->exp.aer_log.log = g_malloc0(sizeof dev->exp.aer_log.log[0] *
> diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
> index c2ee4e2bdbfc..5891b6816e85 100644
> --- a/include/hw/pci/pcie_aer.h
> +++ b/include/hw/pci/pcie_aer.h
> @@ -44,7 +44,6 @@ struct PCIEAERLog {
> */
> #define PCIE_AER_LOG_MAX_DEFAULT 8
> #define PCIE_AER_LOG_MAX_LIMIT 128
> -#define PCIE_AER_LOG_MAX_UNSET 0xffff
> uint16_t log_max;
>
> /* Error log. log_max-sized array */
> @@ -87,7 +86,8 @@ struct PCIEAERErr {
>
> extern const VMStateDescription vmstate_pcie_aer_log;
>
> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size);
> +int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
> + Error **errp);
> void pcie_aer_exit(PCIDevice *dev);
> void pcie_aer_write_config(PCIDevice *dev,
> uint32_t addr, uint32_t val, int len);
> --
> 2.1.0
>
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version Cao jin
@ 2017-01-10 3:27 ` Michael S. Tsirkin
2017-01-10 3:39 ` Cao jin
0 siblings, 1 reply; 6+ messages in thread
From: Michael S. Tsirkin @ 2017-01-10 3:27 UTC (permalink / raw)
To: Cao jin; +Cc: qemu-devel, marcel, dmitry, jasowang, Dou Liyang
On Wed, Dec 21, 2016 at 04:21:31PM +0800, Cao jin wrote:
> From: Dou Liyang <douly.fnst@cn.fujitsu.com>
>
> Now, AER capa version is fixed to v2, if assigned device isn't v2,
> then this value will be inconsistent between guest and host
>
> Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
I assume this is good for AER work so I'll merge this,
but these patches don't do anything by themselves
in the future pls make this explicit in commit log.
> ---
> hw/net/e1000e.c | 3 ++-
> hw/pci-bridge/ioh3420.c | 3 ++-
> hw/pci-bridge/xio3130_downstream.c | 3 ++-
> hw/pci-bridge/xio3130_upstream.c | 3 ++-
> hw/pci/pcie_aer.c | 6 +++---
> include/hw/pci/pcie_aer.h | 4 ++--
> 6 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
> index 89f96eb4a076..77a4b3e5bf9d 100644
> --- a/hw/net/e1000e.c
> +++ b/hw/net/e1000e.c
> @@ -472,7 +472,8 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
> hw_error("Failed to initialize PM capability");
> }
>
> - if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
> + if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
> + PCI_ERR_SIZEOF, NULL) < 0) {
> hw_error("Failed to initialize AER capability");
> }
>
> diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
> index 04180af79471..84b7946c3136 100644
> --- a/hw/pci-bridge/ioh3420.c
> +++ b/hw/pci-bridge/ioh3420.c
> @@ -135,7 +135,8 @@ static int ioh3420_initfn(PCIDevice *d)
> goto err_pcie_cap;
> }
>
> - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> + rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET,
> + PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> error_report_err(err);
> goto err;
> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
> index 571334185b42..04b8e5b8479e 100644
> --- a/hw/pci-bridge/xio3130_downstream.c
> +++ b/hw/pci-bridge/xio3130_downstream.c
> @@ -97,7 +97,8 @@ static int xio3130_downstream_initfn(PCIDevice *d)
> goto err_pcie_cap;
> }
>
> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
> + PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> error_report_err(err);
> goto err;
> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
> index 94c16910069e..d1f59c883477 100644
> --- a/hw/pci-bridge/xio3130_upstream.c
> +++ b/hw/pci-bridge/xio3130_upstream.c
> @@ -85,7 +85,8 @@ static int xio3130_upstream_initfn(PCIDevice *d)
> pcie_cap_flr_init(d);
> pcie_cap_deverr_init(d);
>
> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
> + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
> + PCI_ERR_SIZEOF, &err);
> if (rc < 0) {
> error_report_err(err);
> goto err;
> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
> index 2a4bd5aef639..daf1f65427c2 100644
> --- a/hw/pci/pcie_aer.c
> +++ b/hw/pci/pcie_aer.c
> @@ -97,10 +97,10 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
> aer_log->log_num = 0;
> }
>
> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
> - Error **errp)
> +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
> + uint16_t size, Error **errp)
> {
> - pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
> + pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
> offset, size);
> dev->exp.aer_cap = offset;
>
> diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
> index 5891b6816e85..526802bd312b 100644
> --- a/include/hw/pci/pcie_aer.h
> +++ b/include/hw/pci/pcie_aer.h
> @@ -86,8 +86,8 @@ struct PCIEAERErr {
>
> extern const VMStateDescription vmstate_pcie_aer_log;
>
> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
> - Error **errp);
> +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
> + uint16_t size, Error **errp);
> void pcie_aer_exit(PCIDevice *dev);
> void pcie_aer_write_config(PCIDevice *dev,
> uint32_t addr, uint32_t val, int len);
> --
> 2.1.0
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version
2017-01-10 3:27 ` Michael S. Tsirkin
@ 2017-01-10 3:39 ` Cao jin
0 siblings, 0 replies; 6+ messages in thread
From: Cao jin @ 2017-01-10 3:39 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: qemu-devel, marcel, dmitry, jasowang, Dou Liyang
On 01/10/2017 11:27 AM, Michael S. Tsirkin wrote:
> On Wed, Dec 21, 2016 at 04:21:31PM +0800, Cao jin wrote:
>> From: Dou Liyang <douly.fnst@cn.fujitsu.com>
>>
>> Now, AER capa version is fixed to v2, if assigned device isn't v2,
>> then this value will be inconsistent between guest and host
>>
>> Signed-off-by: Dou Liyang <douly.fnst@cn.fujitsu.com>
>> Signed-off-by: Cao jin <caoj.fnst@cn.fujitsu.com>
>> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
>
> I assume this is good for AER work so I'll merge this,
> but these patches don't do anything by themselves
> in the future pls make this explicit in commit log.
>
Thanks for the reminding, please amend the commit log if you want.
--
Sincerely,
Cao jin
>> ---
>> hw/net/e1000e.c | 3 ++-
>> hw/pci-bridge/ioh3420.c | 3 ++-
>> hw/pci-bridge/xio3130_downstream.c | 3 ++-
>> hw/pci-bridge/xio3130_upstream.c | 3 ++-
>> hw/pci/pcie_aer.c | 6 +++---
>> include/hw/pci/pcie_aer.h | 4 ++--
>> 6 files changed, 13 insertions(+), 9 deletions(-)
>>
>> diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c
>> index 89f96eb4a076..77a4b3e5bf9d 100644
>> --- a/hw/net/e1000e.c
>> +++ b/hw/net/e1000e.c
>> @@ -472,7 +472,8 @@ static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
>> hw_error("Failed to initialize PM capability");
>> }
>>
>> - if (pcie_aer_init(pci_dev, e1000e_aer_offset, PCI_ERR_SIZEOF, NULL) < 0) {
>> + if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
>> + PCI_ERR_SIZEOF, NULL) < 0) {
>> hw_error("Failed to initialize AER capability");
>> }
>>
>> diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c
>> index 04180af79471..84b7946c3136 100644
>> --- a/hw/pci-bridge/ioh3420.c
>> +++ b/hw/pci-bridge/ioh3420.c
>> @@ -135,7 +135,8 @@ static int ioh3420_initfn(PCIDevice *d)
>> goto err_pcie_cap;
>> }
>>
>> - rc = pcie_aer_init(d, IOH_EP_AER_OFFSET, PCI_ERR_SIZEOF, &err);
>> + rc = pcie_aer_init(d, PCI_ERR_VER, IOH_EP_AER_OFFSET,
>> + PCI_ERR_SIZEOF, &err);
>> if (rc < 0) {
>> error_report_err(err);
>> goto err;
>> diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
>> index 571334185b42..04b8e5b8479e 100644
>> --- a/hw/pci-bridge/xio3130_downstream.c
>> +++ b/hw/pci-bridge/xio3130_downstream.c
>> @@ -97,7 +97,8 @@ static int xio3130_downstream_initfn(PCIDevice *d)
>> goto err_pcie_cap;
>> }
>>
>> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
>> + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
>> + PCI_ERR_SIZEOF, &err);
>> if (rc < 0) {
>> error_report_err(err);
>> goto err;
>> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
>> index 94c16910069e..d1f59c883477 100644
>> --- a/hw/pci-bridge/xio3130_upstream.c
>> +++ b/hw/pci-bridge/xio3130_upstream.c
>> @@ -85,7 +85,8 @@ static int xio3130_upstream_initfn(PCIDevice *d)
>> pcie_cap_flr_init(d);
>> pcie_cap_deverr_init(d);
>>
>> - rc = pcie_aer_init(d, XIO3130_AER_OFFSET, PCI_ERR_SIZEOF, &err);
>> + rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
>> + PCI_ERR_SIZEOF, &err);
>> if (rc < 0) {
>> error_report_err(err);
>> goto err;
>> diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
>> index 2a4bd5aef639..daf1f65427c2 100644
>> --- a/hw/pci/pcie_aer.c
>> +++ b/hw/pci/pcie_aer.c
>> @@ -97,10 +97,10 @@ static void aer_log_clear_all_err(PCIEAERLog *aer_log)
>> aer_log->log_num = 0;
>> }
>>
>> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
>> - Error **errp)
>> +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
>> + uint16_t size, Error **errp)
>> {
>> - pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
>> + pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, cap_ver,
>> offset, size);
>> dev->exp.aer_cap = offset;
>>
>> diff --git a/include/hw/pci/pcie_aer.h b/include/hw/pci/pcie_aer.h
>> index 5891b6816e85..526802bd312b 100644
>> --- a/include/hw/pci/pcie_aer.h
>> +++ b/include/hw/pci/pcie_aer.h
>> @@ -86,8 +86,8 @@ struct PCIEAERErr {
>>
>> extern const VMStateDescription vmstate_pcie_aer_log;
>>
>> -int pcie_aer_init(PCIDevice *dev, uint16_t offset, uint16_t size,
>> - Error **errp);
>> +int pcie_aer_init(PCIDevice *dev, uint8_t cap_ver, uint16_t offset,
>> + uint16_t size, Error **errp);
>> void pcie_aer_exit(PCIDevice *dev);
>> void pcie_aer_write_config(PCIDevice *dev,
>> uint32_t addr, uint32_t val, int len);
>> --
>> 2.1.0
>>
>>
>
>
> .
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-01-10 3:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-12-21 8:21 [Qemu-devel] [PATCH v4 0/2] pcie_aer modification Cao jin
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 1/2] pcie_aer: Convert pcie_aer_init to Error Cao jin
2016-12-22 15:00 ` Dmitry Fleytman
2016-12-21 8:21 ` [Qemu-devel] [PATCH v4 2/2] pcie_aer: support configurable AER capa version Cao jin
2017-01-10 3:27 ` Michael S. Tsirkin
2017-01-10 3:39 ` Cao jin
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