[PATCH 0/2] Exynos5433/TM2: add clocks configuration for display subsystem

[PATCH 0/2] Exynos5433/TM2: add clocks configuration for display subsystem

[Marek Szyprowski]

Hello,

This patchset is a next step to add support for all power domains on
Exynos5433 SoCs. This patchset contains patches for initial clocks
configuration on TM2/TM2e boards. Till now display subsystem worked only
because the clock hierarchy has been configured by the bootloader.
However when power domains are added, such configuration might be lost
if the display power domain get turned off before display clock
controller's probe.

Patches have been generated on top of linux-next from 25th January 2017.

This is a part of a larger task, which goal is to add support for power
domains on Exynos5433 SoCs / TM2 boards. All patches needed to get it
working have been pushed to the following git repo:
https://git.linaro.org/people/marek.szyprowski/linux-srpol.git v4.10-next-tm2-pd

Best regards
Marek Szyprowski
Samsung R&D Institute Poland


Patch summary:

Marek Szyprowski (2):
  clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
  arm64: dts: exynos: Add initial configuration for DISP clocks for
    TM2/TM2e

 .../boot/dts/exynos/exynos5433-tm2-common.dtsi     | 25 ++++++++++++++++++----
 drivers/clk/samsung/clk-exynos5433.c               |  6 ++++--
 include/dt-bindings/clock/exynos5433.h             |  5 ++++-
 3 files changed, 29 insertions(+), 7 deletions(-)

-- 
1.9.1

[PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Marek Szyprowski]

Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
 include/dt-bindings/clock/exynos5433.h | 5 ++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index 0db5204c307c..1ab4fca255e1 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)
 	FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
 	FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
 	/* PHY clocks from MIPI_DPHY0 */
-	FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
-	FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
+	FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
+			NULL, 0, 188000000),
+	FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
+			NULL, 0, 100000000),
 	/* PHY clocks from HDMI_PHY */
 	FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
 			NULL, 0, 300000000),
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 4fa6bb2136e3..be39d23e6a32 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -771,7 +771,10 @@
 
 #define CLK_PCLK_DECON					113
 
-#define DISP_NR_CLK					114
+#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
+#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
+
+#define DISP_NR_CLK					116
 
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER				1
-- 
1.9.1

Re: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Krzysztof Kozlowski]

On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote:
> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
> to setup initial clock configuration for display subsystem in device tree
> in order to avoid dependency on the configuration left by the bootloader.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Sylwester,
Could you provide a tag with this?

Best regards,
Krzysztof

Re: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Sylwester Nawrocki]

Cc: linux-clk@vger.kernel.org

On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote:
> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote:
>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
>> to setup initial clock configuration for display subsystem in device tree
>> in order to avoid dependency on the configuration left by the bootloader.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
>>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
>>  2 files changed, 8 insertions(+), 3 deletions(-)
>>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> 
> Sylwester,
> Could you provide a tag with this?

I have the tag prepared already, but please resend the patch to
linux-clk@vger.kernel.org and I will reply there.
The patches were sent only to the linux-samsung-soc mailing list.

-- 
Thanks,
Sylwester

Re: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Sylwester Nawrocki]

On 01/27/2017 12:05 PM, Sylwester Nawrocki wrote:
> Cc: linux-clk@vger.kernel.org
> 
> On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote:
>> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote:
>>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
>>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
>>> to setup initial clock configuration for display subsystem in device tree
>>> in order to avoid dependency on the configuration left by the bootloader.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
>>>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
>>>  2 files changed, 8 insertions(+), 3 deletions(-)
>>>
>> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
>>
>> Sylwester,
>> Could you provide a tag with this?
> 
> I have the tag prepared already, but please resend the patch to
> linux-clk@vger.kernel.org and I will reply there.
> The patches were sent only to the linux-samsung-soc mailing list.

Krzysztof, if you need this patch series as a dependency here is the tag:

 The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:

  Linux 4.10-rc2 (2017-01-01 14:31:53 -0800)

are available in the git repository at:

  git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.11-samsung-dphy

for you to fetch changes up to 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317:

  clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
(2017-01-27 11:34:00 +0100)

----------------------------------------------------------------
Exporting clocks for MIPI DSI DPHY and the display PLL
frequency list update for Exynos5433 SoC.

----------------------------------------------------------------
Marek Szyprowski (2):
      clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks
      clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates

 drivers/clk/samsung/clk-exynos5433.c   | 8 ++++++--
 include/dt-bindings/clock/exynos5433.h | 5 ++++-
 2 files changed, 10 insertions(+), 3 deletions(-)

Re: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Krzysztof Kozlowski]

On Fri, Jan 27, 2017 at 12:34:57PM +0100, Sylwester Nawrocki wrote:
> On 01/27/2017 12:05 PM, Sylwester Nawrocki wrote:
> > Cc: linux-clk@vger.kernel.org
> > 
> > On 01/25/2017 09:06 PM, Krzysztof Kozlowski wrote:
> >> On Wed, Jan 25, 2017 at 12:51:57PM +0100, Marek Szyprowski wrote:
> >>> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
> >>> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
> >>> to setup initial clock configuration for display subsystem in device tree
> >>> in order to avoid dependency on the configuration left by the bootloader.
> >>>
> >>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> >>> ---
> >>>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
> >>>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
> >>>  2 files changed, 8 insertions(+), 3 deletions(-)
> >>>
> >> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> >>
> >> Sylwester,
> >> Could you provide a tag with this?
> > 
> > I have the tag prepared already, but please resend the patch to
> > linux-clk@vger.kernel.org and I will reply there.
> > The patches were sent only to the linux-samsung-soc mailing list.
> 
> Krzysztof, if you need this patch series as a dependency here is the tag:
> 
>  The following changes since commit 0c744ea4f77d72b3dcebb7a8f2684633ec79be88:
> 
>   Linux 4.10-rc2 (2017-01-01 14:31:53 -0800)
> 
> are available in the git repository at:
> 
>   git://linuxtv.org/snawrocki/samsung.git tags/clk-v4.11-samsung-dphy
> 
> for you to fetch changes up to 698e0d1d22346ef03d7a13fcd9c2cc86a24bf317:
> 
>   clk: samsung: exynos5433: Add data for 250MHz and 278MHz PLL rates
> (2017-01-27 11:34:00 +0100)
>

Thanks, pulled.

Best regards,
Krzysztof

Re: [PATCH 1/2] clk: samsung: exynos5433: Add IDs for PHYCLK_MIPIDPHY0_* clocks

[Chanwoo Choi]

Hi,

On 2017년 01월 25일 20:51, Marek Szyprowski wrote:
> Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
> phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
> to setup initial clock configuration for display subsystem in device tree
> in order to avoid dependency on the configuration left by the bootloader.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5433.c   | 6 ++++--
>  include/dt-bindings/clock/exynos5433.h | 5 ++++-
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
> index 0db5204c307c..1ab4fca255e1 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -2559,8 +2559,10 @@ static void __init exynos5433_cmu_g2d_init(struct device_node *np)
>  	FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
>  	FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
>  	/* PHY clocks from MIPI_DPHY0 */
> -	FRATE(0, "phyclk_mipidphy0_bitclkdiv8_phy", NULL, 0, 188000000),
> -	FRATE(0, "phyclk_mipidphy0_rxclkesc0_phy", NULL, 0, 100000000),
> +	FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
> +			NULL, 0, 188000000),
> +	FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
> +			NULL, 0, 100000000),
>  	/* PHY clocks from HDMI_PHY */
>  	FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
>  			NULL, 0, 300000000),
> diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index 4fa6bb2136e3..be39d23e6a32 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -771,7 +771,10 @@
>  
>  #define CLK_PCLK_DECON					113
>  
> -#define DISP_NR_CLK					114
> +#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
> +#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
> +
> +#define DISP_NR_CLK					116
>  
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER				1
> 

Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsugn.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

[PATCH 2/2] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e

[Marek Szyprowski]

Add initial clock configuration for display subsystem for Exynos5433
based TM2/TM2e boards in device tree in order to avoid dependency on the
configuration left by the bootloader. This initial configuration is also
needed to ensure that display subsystem is operational if display power
domain gets turned off before clock controller is probed and the inital
clock configuration left by the bootloader saved.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../boot/dts/exynos/exynos5433-tm2-common.dtsi     | 25 ++++++++++++++++++----
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 13a0950b57e2..1b9a8a92a40c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -218,15 +218,32 @@
 };
 
 &cmu_disp {
-	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
 			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
+			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
+			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
+			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
+			  <&cmu_disp CLK_MOUT_DISP_PLL>,
+			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
 			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
 			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
-	assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
-				 <0>,
+	assigned-clock-parents = <0>, <0>,
+				 <&cmu_mif CLK_ACLK_DISP_333>,
+				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
+				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
+				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
+				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
+				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
+				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
+				 <&cmu_disp CLK_FOUT_DISP_PLL>,
+				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
 				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
-	assigned-clock-rates = <0>, <400000000>;
+	assigned-clock-rates = <266000000>, <400000000>;
 };
 
 &cmu_fsys {
-- 
1.9.1

Re: [PATCH 2/2] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e

[Chanwoo Choi]

Hi Marek,

On 2017년 01월 25일 20:51, Marek Szyprowski wrote:
> Add initial clock configuration for display subsystem for Exynos5433
> based TM2/TM2e boards in device tree in order to avoid dependency on the
> configuration left by the bootloader. This initial configuration is also
> needed to ensure that display subsystem is operational if display power
> domain gets turned off before clock controller is probed and the inital
> clock configuration left by the bootloader saved.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../boot/dts/exynos/exynos5433-tm2-common.dtsi     | 25 ++++++++++++++++++----
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> index 13a0950b57e2..1b9a8a92a40c 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
> @@ -218,15 +218,32 @@
>  };
>  
>  &cmu_disp {
> -	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
> +	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
>  			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
> +			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
> +			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> +			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
> +			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> +			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
> +			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
> +			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
> +			  <&cmu_disp CLK_MOUT_DISP_PLL>,
> +			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>  			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
>  			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
> -	assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
> -				 <0>,
> +	assigned-clock-parents = <0>, <0>,
> +				 <&cmu_mif CLK_ACLK_DISP_333>,
> +				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> +				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
> +				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> +				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
> +				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
> +				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
> +				 <&cmu_disp CLK_FOUT_DISP_PLL>,
> +				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>  				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
>  				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
> -	assigned-clock-rates = <0>, <400000000>;
> +	assigned-clock-rates = <266000000>, <400000000>;

The bootloader initialized the CLK_FOUT_DISP_PLL with 250000000. 
when checking the clock rate with clk_summary.

But, the pll table for fout_disp_pll in clk-exynos5433.c
doesn't include the entry for 250000000 rate. 

On this patch, I think you correct the frequency of CLK_FOUT_DISP_PLL.

Before applying this patch:
root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep fout_disp_pll
    fout_disp_pll                         1            1   250000000          0 0  

After applying this patch:
root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep fout_disp_pll     
    fout_disp_pll                         1            1   266000000          0 0  

>  };
>  
>  &cmu_fsys {
> 

I checked the relationship between clocks and parent clocks on this patch
with clock-exynos5433.c driver. Looks good to me.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH 2/2] arm64: dts: exynos: Add initial configuration for DISP clocks for TM2/TM2e

[Marek Szyprowski]

Hi Chanwoo,

On 2017-01-26 03:03, Chanwoo Choi wrote:
> On 2017년 01월 25일 20:51, Marek Szyprowski wrote:
>> Add initial clock configuration for display subsystem for Exynos5433
>> based TM2/TM2e boards in device tree in order to avoid dependency on the
>> configuration left by the bootloader. This initial configuration is also
>> needed to ensure that display subsystem is operational if display power
>> domain gets turned off before clock controller is probed and the inital
>> clock configuration left by the bootloader saved.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>   .../boot/dts/exynos/exynos5433-tm2-common.dtsi     | 25 ++++++++++++++++++----
>>   1 file changed, 21 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> index 13a0950b57e2..1b9a8a92a40c 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
>> @@ -218,15 +218,32 @@
>>   };
>>   
>>   &cmu_disp {
>> -	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>> +	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
>>   			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
>> +			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
>> +			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> +			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
>> +			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> +			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
>> +			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
>> +			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
>> +			  <&cmu_disp CLK_MOUT_DISP_PLL>,
>> +			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
>>   			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
>>   			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
>> -	assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>> -				 <0>,
>> +	assigned-clock-parents = <0>, <0>,
>> +				 <&cmu_mif CLK_ACLK_DISP_333>,
>> +				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
>> +				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
>> +				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
>> +				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
>> +				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
>> +				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
>> +				 <&cmu_disp CLK_FOUT_DISP_PLL>,
>> +				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
>>   				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
>>   				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
>> -	assigned-clock-rates = <0>, <400000000>;
>> +	assigned-clock-rates = <266000000>, <400000000>;
> The bootloader initialized the CLK_FOUT_DISP_PLL with 250000000.
> when checking the clock rate with clk_summary.
>
> But, the pll table for fout_disp_pll in clk-exynos5433.c
> doesn't include the entry for 250000000 rate.
>
> On this patch, I think you correct the frequency of CLK_FOUT_DISP_PLL.
>
> Before applying this patch:
> root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep fout_disp_pll
>      fout_disp_pll                         1            1   250000000          0 0
>
> After applying this patch:
> root@localhost:~# cat /sys/kernel/debug/clk/clk_summary | grep fout_disp_pll
>      fout_disp_pll                         1            1   266000000          0 0

Thanks for pointing this out. I've checked once again and bootloader 
applies 250MHz
to DISP PLL on TM2 and 278MHz on TM2e. 266MHz was working fine, but 
probably the
bootloader's values are a bit more fine tuned for each board. I would 
like to apply
exactly same values, so I will send v2 of this patchset.

>>   };
>>   
>>   &cmu_fsys {
>>
> I checked the relationship between clocks and parent clocks on this patch
> with clock-exynos5433.c driver. Looks good to me.
>
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland