[PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Jaehoon Chung]

This patcheset is for using PHY generic framework.
Current pci-exyns doesn't use the phy framework since there haven't been on
PHY subsystem when Exynos5440 had bean upstreamed.
It's making a difficult to upstream the other Exynos variants because of different
PHY registers.

This patcheset has the below modifications:
1) Introduces the phy-exynos-pcie
2) Handles PHY register from PHY framework for pci-exynos
3) Modifies the dt-binding of pci-exynos
4) Maintains the backward compatibility

Changelog on V3:
- Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
  : Will send this patch after applying this patchset.
- Fixes typo
- Based on latest PCI git repository (host-exynos branch)
- Changes commit message
- Removes the dependency

Changelog on V2:
- Keep current codes for backward compatibility
- Fixes some typos
- Split the patches for removing the dependency
- Removes the unnecessary codes
- Change the patch's sequence
- Based on latest PCI git repository.(next branch)

Jaehoon Chung (4):
  Documetation: samsung-phy: add the exynos-pcie-phy binding
  phy: phy-exynos-pcie: Add support for Exynos PCIe phy
  Documetation: binding: modify the exynos5440 pcie binding
  PCI: exynos: support the using PHY generic framework

 .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
 .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
 drivers/pci/host/pci-exynos.c                      |  54 +++-
 drivers/phy/Kconfig                                |   8 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
 6 files changed, 390 insertions(+), 4 deletions(-)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

-- 
2.10.2

[PATCH V3 1/4] Documetation: samsung-phy: add the exynos-pcie-phy binding

[Jaehoon Chung]

Adds the exynos-pcie-phy binding for Exynos PCIe PHY.
This is for using generic PHY framework.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changelog on V3:
- None

Changelog on V2:
- Remove the child node.
- Add 2nd address to the parent reg prop.

 Documentation/devicetree/bindings/phy/samsung-phy.txt | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 9872ba8..ab80bfe 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,3 +191,20 @@ Example:
 		usbdrdphy0 = &usb3_phy0;
 		usbdrdphy1 = &usb3_phy1;
 	};
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+	- First is for phy register, second is for block register.
+- reg-names : Must be set to "phy" and "block".
+
+Example:
+	pcie_phy0: pcie-phy@270000 {
+		#phy-cells = <0>;
+		compatible = "samsung,exynos5440-pcie-phy";
+		reg = <0x270000 0x1000>, <0x271000 0x40>;
+		reg-names = "phy", "block";
+	};
-- 
2.10.2

[PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

This patch adds support for Generic PHY framework about Exynos SoCs.
Current Exynos PCIe driver doesn't use the PHY framework.
It's making a difficult to upstream the other Exynos variants because of
different PHY registers.

Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
driver.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
Changelog on V3:
- Remove the dependency abot PCI_EXYNOS
- Adds a depends on COMPILE_TEST
- Use the readl_poll_timeout() instead of while()
- Fixes const type
- Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
- Changes commit message

Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig           |   8 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 294 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..8659f38 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
 	  This driver provides PHY interface for USB 3.0 DRD controller
 	  present on Exynos5 SoC series.
 
+config PHY_EXYNOS_PCIE
+	bool "Exynos PCIe PHY driver"
+	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
+	select GENERIC_PHY
+	help
+	  Enable PCIe PHY support for Exynos SoC series.
+	  This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
 	tristate "IMG Pistachio USB2.0 PHY driver"
 	depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)	+= phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 0000000..9ec1855
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,285 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET		0x000
+#define PCIE_PHY_COMMON_RESET		0x004
+#define PCIE_PHY_CMN_REG		0x008
+#define PCIE_PHY_MAC_RESET		0x00c
+#define PCIE_PHY_PLL_LOCKED		0x010
+#define PCIE_PHY_TRSVREG_RESET		0x020
+#define PCIE_PHY_TRSV_RESET		0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE		0x004
+#define PCIE_PHY_PLL_DIV_0		0x008
+#define PCIE_PHY_PLL_BIAS		0x00c
+#define PCIE_PHY_DCC_FEEDBACK		0x014
+#define PCIE_PHY_PLL_DIV_1		0x05c
+#define PCIE_PHY_COMMON_POWER		0x064
+#define PCIE_PHY_COMMON_PD_CMN		BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL		0x084
+#define PCIE_PHY_TRSV0_DRV_LVL		0x088
+#define PCIE_PHY_TRSV0_RXCDR		0x0ac
+#define PCIE_PHY_TRSV0_POWER		0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV0_LVCC		0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL		0x144
+#define PCIE_PHY_TRSV1_RXCDR		0x16c
+#define PCIE_PHY_TRSV1_POWER		0x184
+#define PCIE_PHY_TRSV1_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV1_LVCC		0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL		0x204
+#define PCIE_PHY_TRSV2_RXCDR		0x22c
+#define PCIE_PHY_TRSV2_POWER		0x244
+#define PCIE_PHY_TRSV2_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV2_LVCC		0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL		0x2c4
+#define PCIE_PHY_TRSV3_RXCDR		0x2ec
+#define PCIE_PHY_TRSV3_POWER		0x304
+#define PCIE_PHY_TRSV3_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV3_LVCC		0x31c
+
+struct exynos_pcie_phy_data {
+	const struct phy_ops	*ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+	const struct exynos_pcie_phy_data *drv_data;
+	void __iomem *phy_base;
+	void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+	writel(val, base + offset);
+}
+
+static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
+{
+	return readl(base + offset);
+}
+
+/* For Exynos5440 specific functions */
+static int exynos5440_pcie_phy_init(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+	/* DCC feedback control off */
+	exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
+
+	/* set TX/RX impedance */
+	exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
+
+	/* set 50Mhz PHY clock */
+	exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
+	exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
+
+	/* set TX Differential output for lane 0 */
+	exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+
+	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
+	exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+
+	/* set RX clock and data recovery bandwidth */
+	exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
+
+	/* change TX Pre-emphasis Level Control for lanes */
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+
+	/* set LVCC */
+	exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
+
+	/* pulse for common reset */
+	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
+	udelay(500);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_power_on(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+	u32 val;
+
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+	val &= ~PCIE_PHY_COMMON_PD_CMN;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+	val &= ~PCIE_PHY_TRSV0_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+	val &= ~PCIE_PHY_TRSV1_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+	val &= ~PCIE_PHY_TRSV2_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+	val &= ~PCIE_PHY_TRSV3_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_power_off(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+	u32 val;
+
+	if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
+				(val != 0), 1, 500)) {
+		dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
+		return -ETIMEDOUT;
+	}
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+	val |= PCIE_PHY_COMMON_PD_CMN;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+	val |= PCIE_PHY_TRSV0_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+	val |= PCIE_PHY_TRSV1_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+	val |= PCIE_PHY_TRSV2_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+	val |= PCIE_PHY_TRSV3_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_reset(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
+
+	return 0;
+}
+
+static const struct phy_ops exynos5440_phy_ops = {
+	.init		= exynos5440_pcie_phy_init,
+	.power_on	= exynos5440_pcie_phy_power_on,
+	.power_off	= exynos5440_pcie_phy_power_off,
+	.reset		= exynos5440_pcie_phy_reset,
+	.owner		= THIS_MODULE,
+};
+
+static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
+	.ops		= &exynos5440_phy_ops,
+};
+
+static const struct of_device_id exynos_pcie_phy_match[] = {
+	{
+		.compatible = "samsung,exynos5440-pcie-phy",
+		.data = &exynos5440_pcie_phy_data,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
+
+static int exynos_pcie_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct exynos_pcie_phy *exynos_phy;
+	struct phy *generic_phy;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	const struct exynos_pcie_phy_data *drv_data;
+
+	drv_data = of_device_get_match_data(dev);
+	if (!drv_data)
+		return -ENODEV;
+
+	exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
+	if (!exynos_phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	exynos_phy->phy_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(exynos_phy->phy_base))
+		return PTR_ERR(exynos_phy->phy_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	exynos_phy->blk_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(exynos_phy->phy_base))
+		return PTR_ERR(exynos_phy->phy_base);
+
+	exynos_phy->drv_data = drv_data;
+
+	generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(generic_phy);
+	}
+
+	phy_set_drvdata(generic_phy, exynos_phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver exynos_pcie_phy_driver = {
+	.probe	= exynos_pcie_phy_probe,
+	.driver = {
+		.of_match_table	= exynos_pcie_phy_match,
+		.name		= "exynos_pcie_phy",
+	}
+};
+module_platform_driver(exynos_pcie_phy_driver);
+
+MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
+MODULE_AUTHOR("Jaehoon Chung <jh80.chung@samsung.com>");
+MODULE_LICENSE("GPL v2");
-- 
2.10.2

[PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

This patch adds support for Generic PHY framework about Exynos SoCs.
Current Exynos PCIe driver doesn't use the PHY framework.
It's making a difficult to upstream the other Exynos variants because of
different PHY registers.

Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
driver.

Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Reviewed-by: Jingoo Han <jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Reviewed-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changelog on V3:
- Remove the dependency abot PCI_EXYNOS
- Adds a depends on COMPILE_TEST
- Use the readl_poll_timeout() instead of while()
- Fixes const type
- Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
- Changes commit message

Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig           |   8 ++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 294 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..8659f38 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
 	  This driver provides PHY interface for USB 3.0 DRD controller
 	  present on Exynos5 SoC series.
 
+config PHY_EXYNOS_PCIE
+	bool "Exynos PCIe PHY driver"
+	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
+	select GENERIC_PHY
+	help
+	  Enable PCIe PHY support for Exynos SoC series.
+	  This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
 	tristate "IMG Pistachio USB2.0 PHY driver"
 	depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)	+= phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 0000000..9ec1855
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,285 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET		0x000
+#define PCIE_PHY_COMMON_RESET		0x004
+#define PCIE_PHY_CMN_REG		0x008
+#define PCIE_PHY_MAC_RESET		0x00c
+#define PCIE_PHY_PLL_LOCKED		0x010
+#define PCIE_PHY_TRSVREG_RESET		0x020
+#define PCIE_PHY_TRSV_RESET		0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE		0x004
+#define PCIE_PHY_PLL_DIV_0		0x008
+#define PCIE_PHY_PLL_BIAS		0x00c
+#define PCIE_PHY_DCC_FEEDBACK		0x014
+#define PCIE_PHY_PLL_DIV_1		0x05c
+#define PCIE_PHY_COMMON_POWER		0x064
+#define PCIE_PHY_COMMON_PD_CMN		BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL		0x084
+#define PCIE_PHY_TRSV0_DRV_LVL		0x088
+#define PCIE_PHY_TRSV0_RXCDR		0x0ac
+#define PCIE_PHY_TRSV0_POWER		0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV0_LVCC		0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL		0x144
+#define PCIE_PHY_TRSV1_RXCDR		0x16c
+#define PCIE_PHY_TRSV1_POWER		0x184
+#define PCIE_PHY_TRSV1_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV1_LVCC		0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL		0x204
+#define PCIE_PHY_TRSV2_RXCDR		0x22c
+#define PCIE_PHY_TRSV2_POWER		0x244
+#define PCIE_PHY_TRSV2_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV2_LVCC		0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL		0x2c4
+#define PCIE_PHY_TRSV3_RXCDR		0x2ec
+#define PCIE_PHY_TRSV3_POWER		0x304
+#define PCIE_PHY_TRSV3_PD_TSV		BIT(7)
+#define PCIE_PHY_TRSV3_LVCC		0x31c
+
+struct exynos_pcie_phy_data {
+	const struct phy_ops	*ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+	const struct exynos_pcie_phy_data *drv_data;
+	void __iomem *phy_base;
+	void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+	writel(val, base + offset);
+}
+
+static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
+{
+	return readl(base + offset);
+}
+
+/* For Exynos5440 specific functions */
+static int exynos5440_pcie_phy_init(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+	/* DCC feedback control off */
+	exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
+
+	/* set TX/RX impedance */
+	exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
+
+	/* set 50Mhz PHY clock */
+	exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
+	exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
+
+	/* set TX Differential output for lane 0 */
+	exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+
+	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
+	exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+
+	/* set RX clock and data recovery bandwidth */
+	exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
+	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
+
+	/* change TX Pre-emphasis Level Control for lanes */
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+
+	/* set LVCC */
+	exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
+	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
+
+	/* pulse for common reset */
+	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
+	udelay(500);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_power_on(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+	u32 val;
+
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+	val &= ~PCIE_PHY_COMMON_PD_CMN;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+	val &= ~PCIE_PHY_TRSV0_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+	val &= ~PCIE_PHY_TRSV1_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+	val &= ~PCIE_PHY_TRSV2_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+	val &= ~PCIE_PHY_TRSV3_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_power_off(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+	u32 val;
+
+	if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
+				(val != 0), 1, 500)) {
+		dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
+		return -ETIMEDOUT;
+	}
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+	val |= PCIE_PHY_COMMON_PD_CMN;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+	val |= PCIE_PHY_TRSV0_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+	val |= PCIE_PHY_TRSV1_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+	val |= PCIE_PHY_TRSV2_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+	val |= PCIE_PHY_TRSV3_PD_TSV;
+	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+	return 0;
+}
+
+static int exynos5440_pcie_phy_reset(struct phy *phy)
+{
+	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
+	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
+
+	return 0;
+}
+
+static const struct phy_ops exynos5440_phy_ops = {
+	.init		= exynos5440_pcie_phy_init,
+	.power_on	= exynos5440_pcie_phy_power_on,
+	.power_off	= exynos5440_pcie_phy_power_off,
+	.reset		= exynos5440_pcie_phy_reset,
+	.owner		= THIS_MODULE,
+};
+
+static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
+	.ops		= &exynos5440_phy_ops,
+};
+
+static const struct of_device_id exynos_pcie_phy_match[] = {
+	{
+		.compatible = "samsung,exynos5440-pcie-phy",
+		.data = &exynos5440_pcie_phy_data,
+	},
+	{},
+};
+MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
+
+static int exynos_pcie_phy_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct exynos_pcie_phy *exynos_phy;
+	struct phy *generic_phy;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+	const struct exynos_pcie_phy_data *drv_data;
+
+	drv_data = of_device_get_match_data(dev);
+	if (!drv_data)
+		return -ENODEV;
+
+	exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
+	if (!exynos_phy)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	exynos_phy->phy_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(exynos_phy->phy_base))
+		return PTR_ERR(exynos_phy->phy_base);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	exynos_phy->blk_base = devm_ioremap_resource(dev, res);
+	if (IS_ERR(exynos_phy->phy_base))
+		return PTR_ERR(exynos_phy->phy_base);
+
+	exynos_phy->drv_data = drv_data;
+
+	generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+	if (IS_ERR(generic_phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(generic_phy);
+	}
+
+	phy_set_drvdata(generic_phy, exynos_phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver exynos_pcie_phy_driver = {
+	.probe	= exynos_pcie_phy_probe,
+	.driver = {
+		.of_match_table	= exynos_pcie_phy_match,
+		.name		= "exynos_pcie_phy",
+	}
+};
+module_platform_driver(exynos_pcie_phy_driver);
+
+MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
+MODULE_AUTHOR("Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
-- 
2.10.2

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Re: [PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

On 02/13/2017 01:56 PM, Jaehoon Chung wrote:
> This patch adds support for Generic PHY framework about Exynos SoCs.
> Current Exynos PCIe driver doesn't use the PHY framework.
> It's making a difficult to upstream the other Exynos variants because of
> different PHY registers.
>
> Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
> driver.
>
> Signed-off-by: Jaehoon Chung<jh80.chung@samsung.com>
> Acked-by: Krzysztof Kozlowski<krzk@kernel.org>
> Reviewed-by: Jingoo Han<jingoohan1@gmail.com>
> Reviewed-by: Pankaj Dubey<pankaj.dubey@samsung.com>
> ---
> Changelog on V3:
> - Remove the dependency abot PCI_EXYNOS
> - Adds a depends on COMPILE_TEST
> - Use the readl_poll_timeout() instead of while()
> - Fixes const type
> - Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
> - Changes commit message
>
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
>
>   drivers/phy/Kconfig           |   8 ++
>   drivers/phy/Makefile          |   1 +
>   drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 294 insertions(+)
>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..8659f38 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
>   	  This driver provides PHY interface for USB 3.0 DRD controller
>   	  present on Exynos5 SoC series.
>   
> +config PHY_EXYNOS_PCIE
> +	bool "Exynos PCIe PHY driver"
> +	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST

this should be other way round if your driver runs only with OF enabled.
           depends on OF && (ARCH_EXYNOS || COMPILE_TEST)

> +	select GENERIC_PHY
> +	help
> +	  Enable PCIe PHY support for Exynos SoC series.
> +	  This driver provides PHY interface for Exynos PCIe controller.
> +
>   config PHY_PISTACHIO_USB
>   	tristate "IMG Pistachio USB2.0 PHY driver"
>   	depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE)	+= phy-exynos-pcie.o
>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 0000000..9ec1855
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,285 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.

nit: copyright year.

> + * Jaehoon Chung<jh80.chung@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET		0x000
> +#define PCIE_PHY_COMMON_RESET		0x004
> +#define PCIE_PHY_CMN_REG		0x008
> +#define PCIE_PHY_MAC_RESET		0x00c
> +#define PCIE_PHY_PLL_LOCKED		0x010
> +#define PCIE_PHY_TRSVREG_RESET		0x020
> +#define PCIE_PHY_TRSV_RESET		0x024
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE		0x004
> +#define PCIE_PHY_PLL_DIV_0		0x008
> +#define PCIE_PHY_PLL_BIAS		0x00c
> +#define PCIE_PHY_DCC_FEEDBACK		0x014
> +#define PCIE_PHY_PLL_DIV_1		0x05c
> +#define PCIE_PHY_COMMON_POWER		0x064
> +#define PCIE_PHY_COMMON_PD_CMN		BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL		0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL		0x088
> +#define PCIE_PHY_TRSV0_RXCDR		0x0ac
> +#define PCIE_PHY_TRSV0_POWER		0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV0_LVCC		0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL		0x144
> +#define PCIE_PHY_TRSV1_RXCDR		0x16c
> +#define PCIE_PHY_TRSV1_POWER		0x184
> +#define PCIE_PHY_TRSV1_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV1_LVCC		0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL		0x204
> +#define PCIE_PHY_TRSV2_RXCDR		0x22c
> +#define PCIE_PHY_TRSV2_POWER		0x244
> +#define PCIE_PHY_TRSV2_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV2_LVCC		0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL		0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR		0x2ec
> +#define PCIE_PHY_TRSV3_POWER		0x304
> +#define PCIE_PHY_TRSV3_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV3_LVCC		0x31c
> +
> +struct exynos_pcie_phy_data {
> +	const struct phy_ops	*ops;
> +};
> +
> +/* For Exynos pcie phy */
> +struct exynos_pcie_phy {
> +	const struct exynos_pcie_phy_data *drv_data;
> +	void __iomem *phy_base;
> +	void __iomem *blk_base; /* For exynos5440 */
> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> +	writel(val, base + offset);
> +}
> +
> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
> +{
> +	return readl(base + offset);
> +}
> +
> +/* For Exynos5440 specific functions */
> +static int exynos5440_pcie_phy_init(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> +	/* DCC feedback control off */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
> +
> +	/* set TX/RX impedance */
> +	exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
> +
> +	/* set 50Mhz PHY clock */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
> +
> +	/* set TX Differential output for lane 0 */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> +
> +	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> +
> +	/* set RX clock and data recovery bandwidth */
> +	exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
> +
> +	/* change TX Pre-emphasis Level Control for lanes */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> +
> +	/* set LVCC */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
> +
> +	/* pulse for common reset */
> +	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
> +	udelay(500);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +	u32 val;
> +
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> +	val &= ~PCIE_PHY_COMMON_PD_CMN;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> +	val &= ~PCIE_PHY_TRSV0_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> +	val &= ~PCIE_PHY_TRSV1_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> +	val &= ~PCIE_PHY_TRSV2_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> +	val &= ~PCIE_PHY_TRSV3_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +	u32 val;
> +
> +	if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
> +				(val != 0), 1, 500)) {
> +		dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
> +		return -ETIMEDOUT;
> +	}
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> +	val |= PCIE_PHY_COMMON_PD_CMN;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> +	val |= PCIE_PHY_TRSV0_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> +	val |= PCIE_PHY_TRSV1_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> +	val |= PCIE_PHY_TRSV2_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> +	val |= PCIE_PHY_TRSV3_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_reset(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops exynos5440_phy_ops = {
> +	.init		= exynos5440_pcie_phy_init,
> +	.power_on	= exynos5440_pcie_phy_power_on,
> +	.power_off	= exynos5440_pcie_phy_power_off,
> +	.reset		= exynos5440_pcie_phy_reset,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
> +	.ops		= &exynos5440_phy_ops,
> +};
> +
> +static const struct of_device_id exynos_pcie_phy_match[] = {
> +	{
> +		.compatible = "samsung,exynos5440-pcie-phy",
> +		.data = &exynos5440_pcie_phy_data,
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
> +
> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct exynos_pcie_phy *exynos_phy;
> +	struct phy *generic_phy;
> +	struct phy_provider *phy_provider;
> +	struct resource *res;
> +	const struct exynos_pcie_phy_data *drv_data;
> +
> +	drv_data = of_device_get_match_data(dev);
> +	if (!drv_data)
> +		return -ENODEV;
> +
> +	exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
> +	if (!exynos_phy)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	exynos_phy->phy_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(exynos_phy->phy_base))
> +		return PTR_ERR(exynos_phy->phy_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(exynos_phy->phy_base))
> +		return PTR_ERR(exynos_phy->phy_base);
> +
> +	exynos_phy->drv_data = drv_data;
> +
> +	generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
> +	if (IS_ERR(generic_phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(generic_phy);
> +	}
> +
> +	phy_set_drvdata(generic_phy, exynos_phy);
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver exynos_pcie_phy_driver = {
> +	.probe	= exynos_pcie_phy_probe,
> +	.driver = {
> +		.of_match_table	= exynos_pcie_phy_match,
> +		.name		= "exynos_pcie_phy",
> +	}
> +};
> +module_platform_driver(exynos_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
> +MODULE_AUTHOR("Jaehoon Chung<jh80.chung@samsung.com>");
> +MODULE_LICENSE("GPL v2");

rest looks good to me.
Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>

-- 

The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

On 02/13/2017 01:56 PM, Jaehoon Chung wrote:
> This patch adds support for Generic PHY framework about Exynos SoCs.
> Current Exynos PCIe driver doesn't use the PHY framework.
> It's making a difficult to upstream the other Exynos variants because of
> different PHY registers.
>
> Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
> driver.
>
> Signed-off-by: Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Acked-by: Krzysztof Kozlowski<krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Jingoo Han<jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Pankaj Dubey<pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
> Changelog on V3:
> - Remove the dependency abot PCI_EXYNOS
> - Adds a depends on COMPILE_TEST
> - Use the readl_poll_timeout() instead of while()
> - Fixes const type
> - Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
> - Changes commit message
>
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
>
>   drivers/phy/Kconfig           |   8 ++
>   drivers/phy/Makefile          |   1 +
>   drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 294 insertions(+)
>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..8659f38 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
>   	  This driver provides PHY interface for USB 3.0 DRD controller
>   	  present on Exynos5 SoC series.
>   
> +config PHY_EXYNOS_PCIE
> +	bool "Exynos PCIe PHY driver"
> +	depends on (ARCH_EXYNOS && OF) || COMPILE_TEST

this should be other way round if your driver runs only with OF enabled.
           depends on OF && (ARCH_EXYNOS || COMPILE_TEST)

> +	select GENERIC_PHY
> +	help
> +	  Enable PCIe PHY support for Exynos SoC series.
> +	  This driver provides PHY interface for Exynos PCIe controller.
> +
>   config PHY_PISTACHIO_USB
>   	tristate "IMG Pistachio USB2.0 PHY driver"
>   	depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)	+= phy-exynos4x12-usb2.o
>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)	+= phy-exynos5250-usb2.o
>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)	+= phy-s5pv210-usb2.o
>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)	+= phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE)	+= phy-exynos-pcie.o
>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)	+= phy-qcom-apq8064-sata.o
>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)	+= phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 0000000..9ec1855
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,285 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.

nit: copyright year.

> + * Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET		0x000
> +#define PCIE_PHY_COMMON_RESET		0x004
> +#define PCIE_PHY_CMN_REG		0x008
> +#define PCIE_PHY_MAC_RESET		0x00c
> +#define PCIE_PHY_PLL_LOCKED		0x010
> +#define PCIE_PHY_TRSVREG_RESET		0x020
> +#define PCIE_PHY_TRSV_RESET		0x024
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE		0x004
> +#define PCIE_PHY_PLL_DIV_0		0x008
> +#define PCIE_PHY_PLL_BIAS		0x00c
> +#define PCIE_PHY_DCC_FEEDBACK		0x014
> +#define PCIE_PHY_PLL_DIV_1		0x05c
> +#define PCIE_PHY_COMMON_POWER		0x064
> +#define PCIE_PHY_COMMON_PD_CMN		BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL		0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL		0x088
> +#define PCIE_PHY_TRSV0_RXCDR		0x0ac
> +#define PCIE_PHY_TRSV0_POWER		0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV0_LVCC		0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL		0x144
> +#define PCIE_PHY_TRSV1_RXCDR		0x16c
> +#define PCIE_PHY_TRSV1_POWER		0x184
> +#define PCIE_PHY_TRSV1_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV1_LVCC		0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL		0x204
> +#define PCIE_PHY_TRSV2_RXCDR		0x22c
> +#define PCIE_PHY_TRSV2_POWER		0x244
> +#define PCIE_PHY_TRSV2_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV2_LVCC		0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL		0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR		0x2ec
> +#define PCIE_PHY_TRSV3_POWER		0x304
> +#define PCIE_PHY_TRSV3_PD_TSV		BIT(7)
> +#define PCIE_PHY_TRSV3_LVCC		0x31c
> +
> +struct exynos_pcie_phy_data {
> +	const struct phy_ops	*ops;
> +};
> +
> +/* For Exynos pcie phy */
> +struct exynos_pcie_phy {
> +	const struct exynos_pcie_phy_data *drv_data;
> +	void __iomem *phy_base;
> +	void __iomem *blk_base; /* For exynos5440 */
> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> +	writel(val, base + offset);
> +}
> +
> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
> +{
> +	return readl(base + offset);
> +}
> +
> +/* For Exynos5440 specific functions */
> +static int exynos5440_pcie_phy_init(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> +	/* DCC feedback control off */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
> +
> +	/* set TX/RX impedance */
> +	exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
> +
> +	/* set 50Mhz PHY clock */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
> +
> +	/* set TX Differential output for lane 0 */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> +
> +	/* set TX Pre-emphasis Level Control for lane 0 to minimum */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> +
> +	/* set RX clock and data recovery bandwidth */
> +	exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
> +
> +	/* change TX Pre-emphasis Level Control for lanes */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> +	exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> +
> +	/* set LVCC */
> +	exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
> +	exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
> +
> +	/* pulse for common reset */
> +	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
> +	udelay(500);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +	u32 val;
> +
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> +	val &= ~PCIE_PHY_COMMON_PD_CMN;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> +	val &= ~PCIE_PHY_TRSV0_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> +	val &= ~PCIE_PHY_TRSV1_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> +	val &= ~PCIE_PHY_TRSV2_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> +	val &= ~PCIE_PHY_TRSV3_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +	u32 val;
> +
> +	if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
> +				(val != 0), 1, 500)) {
> +		dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
> +		return -ETIMEDOUT;
> +	}
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> +	val |= PCIE_PHY_COMMON_PD_CMN;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> +	val |= PCIE_PHY_TRSV0_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> +	val |= PCIE_PHY_TRSV1_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> +	val |= PCIE_PHY_TRSV2_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> +	val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> +	val |= PCIE_PHY_TRSV3_PD_TSV;
> +	exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> +	return 0;
> +}
> +
> +static int exynos5440_pcie_phy_reset(struct phy *phy)
> +{
> +	struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
> +	exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
> +
> +	return 0;
> +}
> +
> +static const struct phy_ops exynos5440_phy_ops = {
> +	.init		= exynos5440_pcie_phy_init,
> +	.power_on	= exynos5440_pcie_phy_power_on,
> +	.power_off	= exynos5440_pcie_phy_power_off,
> +	.reset		= exynos5440_pcie_phy_reset,
> +	.owner		= THIS_MODULE,
> +};
> +
> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
> +	.ops		= &exynos5440_phy_ops,
> +};
> +
> +static const struct of_device_id exynos_pcie_phy_match[] = {
> +	{
> +		.compatible = "samsung,exynos5440-pcie-phy",
> +		.data = &exynos5440_pcie_phy_data,
> +	},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
> +
> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct exynos_pcie_phy *exynos_phy;
> +	struct phy *generic_phy;
> +	struct phy_provider *phy_provider;
> +	struct resource *res;
> +	const struct exynos_pcie_phy_data *drv_data;
> +
> +	drv_data = of_device_get_match_data(dev);
> +	if (!drv_data)
> +		return -ENODEV;
> +
> +	exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
> +	if (!exynos_phy)
> +		return -ENOMEM;
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	exynos_phy->phy_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(exynos_phy->phy_base))
> +		return PTR_ERR(exynos_phy->phy_base);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +	exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> +	if (IS_ERR(exynos_phy->phy_base))
> +		return PTR_ERR(exynos_phy->phy_base);
> +
> +	exynos_phy->drv_data = drv_data;
> +
> +	generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
> +	if (IS_ERR(generic_phy)) {
> +		dev_err(dev, "failed to create PHY\n");
> +		return PTR_ERR(generic_phy);
> +	}
> +
> +	phy_set_drvdata(generic_phy, exynos_phy);
> +	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> +	return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver exynos_pcie_phy_driver = {
> +	.probe	= exynos_pcie_phy_probe,
> +	.driver = {
> +		.of_match_table	= exynos_pcie_phy_match,
> +		.name		= "exynos_pcie_phy",
> +	}
> +};
> +module_platform_driver(exynos_pcie_phy_driver);
> +
> +MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
> +MODULE_AUTHOR("Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
> +MODULE_LICENSE("GPL v2");

rest looks good to me.
Reviewed-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>

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Re: [PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 02/15/2017 02:24 PM, Vivek Gautam wrote:
> 
> On 02/13/2017 01:56 PM, Jaehoon Chung wrote:
>> This patch adds support for Generic PHY framework about Exynos SoCs.
>> Current Exynos PCIe driver doesn't use the PHY framework.
>> It's making a difficult to upstream the other Exynos variants because of
>> different PHY registers.
>>
>> Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
>> driver.
>>
>> Signed-off-by: Jaehoon Chung<jh80.chung@samsung.com>
>> Acked-by: Krzysztof Kozlowski<krzk@kernel.org>
>> Reviewed-by: Jingoo Han<jingoohan1@gmail.com>
>> Reviewed-by: Pankaj Dubey<pankaj.dubey@samsung.com>
>> ---
>> Changelog on V3:
>> - Remove the dependency abot PCI_EXYNOS
>> - Adds a depends on COMPILE_TEST
>> - Use the readl_poll_timeout() instead of while()
>> - Fixes const type
>> - Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
>> - Changes commit message
>>
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>   drivers/phy/Kconfig           |   8 ++
>>   drivers/phy/Makefile          |   1 +
>>   drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 294 insertions(+)
>>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..8659f38 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
>>         This driver provides PHY interface for USB 3.0 DRD controller
>>         present on Exynos5 SoC series.
>>   +config PHY_EXYNOS_PCIE
>> +    bool "Exynos PCIe PHY driver"
>> +    depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
> 
> this should be other way round if your driver runs only with OF enabled.
>           depends on OF && (ARCH_EXYNOS || COMPILE_TEST)

Will update.

> 
>> +    select GENERIC_PHY
>> +    help
>> +      Enable PCIe PHY support for Exynos SoC series.
>> +      This driver provides PHY interface for Exynos PCIe controller.
>> +
>>   config PHY_PISTACHIO_USB
>>       tristate "IMG Pistachio USB2.0 PHY driver"
>>       depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)    += phy-exynos4x12-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)    += phy-exynos5250-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)    += phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)    += phy-exynos-pcie.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)    += phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 0000000..9ec1855
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,285 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> 
> nit: copyright year.

Will do.

Thanks for reviewing.

Best Regards,
Jaehoon Chung

> 
>> + * Jaehoon Chung<jh80.chung@samsung.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET        0x000
>> +#define PCIE_PHY_COMMON_RESET        0x004
>> +#define PCIE_PHY_CMN_REG        0x008
>> +#define PCIE_PHY_MAC_RESET        0x00c
>> +#define PCIE_PHY_PLL_LOCKED        0x010
>> +#define PCIE_PHY_TRSVREG_RESET        0x020
>> +#define PCIE_PHY_TRSV_RESET        0x024
>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE        0x004
>> +#define PCIE_PHY_PLL_DIV_0        0x008
>> +#define PCIE_PHY_PLL_BIAS        0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK        0x014
>> +#define PCIE_PHY_PLL_DIV_1        0x05c
>> +#define PCIE_PHY_COMMON_POWER        0x064
>> +#define PCIE_PHY_COMMON_PD_CMN        BIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL        0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL        0x088
>> +#define PCIE_PHY_TRSV0_RXCDR        0x0ac
>> +#define PCIE_PHY_TRSV0_POWER        0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC        0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL        0x144
>> +#define PCIE_PHY_TRSV1_RXCDR        0x16c
>> +#define PCIE_PHY_TRSV1_POWER        0x184
>> +#define PCIE_PHY_TRSV1_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC        0x19c
>> +#define PCIE_PHY_TRSV2_EMP_LVL        0x204
>> +#define PCIE_PHY_TRSV2_RXCDR        0x22c
>> +#define PCIE_PHY_TRSV2_POWER        0x244
>> +#define PCIE_PHY_TRSV2_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV2_LVCC        0x25c
>> +#define PCIE_PHY_TRSV3_EMP_LVL        0x2c4
>> +#define PCIE_PHY_TRSV3_RXCDR        0x2ec
>> +#define PCIE_PHY_TRSV3_POWER        0x304
>> +#define PCIE_PHY_TRSV3_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV3_LVCC        0x31c
>> +
>> +struct exynos_pcie_phy_data {
>> +    const struct phy_ops    *ops;
>> +};
>> +
>> +/* For Exynos pcie phy */
>> +struct exynos_pcie_phy {
>> +    const struct exynos_pcie_phy_data *drv_data;
>> +    void __iomem *phy_base;
>> +    void __iomem *blk_base; /* For exynos5440 */
>> +};
>> +
>> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
>> +{
>> +    writel(val, base + offset);
>> +}
>> +
>> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
>> +{
>> +    return readl(base + offset);
>> +}
>> +
>> +/* For Exynos5440 specific functions */
>> +static int exynos5440_pcie_phy_init(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> +    /* DCC feedback control off */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>> +
>> +    /* set TX/RX impedance */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>> +
>> +    /* set 50Mhz PHY clock */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>> +
>> +    /* set TX Differential output for lane 0 */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>> +
>> +    /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>> +
>> +    /* set RX clock and data recovery bandwidth */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>> +
>> +    /* change TX Pre-emphasis Level Control for lanes */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>> +
>> +    /* set LVCC */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>> +
>> +    /* pulse for common reset */
>> +    exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
>> +    udelay(500);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +    u32 val;
>> +
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> +    val &= ~PCIE_PHY_COMMON_PD_CMN;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> +    val &= ~PCIE_PHY_TRSV0_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> +    val &= ~PCIE_PHY_TRSV1_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> +    val &= ~PCIE_PHY_TRSV2_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> +    val &= ~PCIE_PHY_TRSV3_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +    u32 val;
>> +
>> +    if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
>> +                (val != 0), 1, 500)) {
>> +        dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
>> +        return -ETIMEDOUT;
>> +    }
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> +    val |= PCIE_PHY_COMMON_PD_CMN;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> +    val |= PCIE_PHY_TRSV0_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> +    val |= PCIE_PHY_TRSV1_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> +    val |= PCIE_PHY_TRSV2_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> +    val |= PCIE_PHY_TRSV3_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_reset(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
>> +
>> +    return 0;
>> +}
>> +
>> +static const struct phy_ops exynos5440_phy_ops = {
>> +    .init        = exynos5440_pcie_phy_init,
>> +    .power_on    = exynos5440_pcie_phy_power_on,
>> +    .power_off    = exynos5440_pcie_phy_power_off,
>> +    .reset        = exynos5440_pcie_phy_reset,
>> +    .owner        = THIS_MODULE,
>> +};
>> +
>> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
>> +    .ops        = &exynos5440_phy_ops,
>> +};
>> +
>> +static const struct of_device_id exynos_pcie_phy_match[] = {
>> +    {
>> +        .compatible = "samsung,exynos5440-pcie-phy",
>> +        .data = &exynos5440_pcie_phy_data,
>> +    },
>> +    {},
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
>> +
>> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct exynos_pcie_phy *exynos_phy;
>> +    struct phy *generic_phy;
>> +    struct phy_provider *phy_provider;
>> +    struct resource *res;
>> +    const struct exynos_pcie_phy_data *drv_data;
>> +
>> +    drv_data = of_device_get_match_data(dev);
>> +    if (!drv_data)
>> +        return -ENODEV;
>> +
>> +    exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
>> +    if (!exynos_phy)
>> +        return -ENOMEM;
>> +
>> +    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +    exynos_phy->phy_base = devm_ioremap_resource(dev, res);
>> +    if (IS_ERR(exynos_phy->phy_base))
>> +        return PTR_ERR(exynos_phy->phy_base);
>> +
>> +    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +    exynos_phy->blk_base = devm_ioremap_resource(dev, res);
>> +    if (IS_ERR(exynos_phy->phy_base))
>> +        return PTR_ERR(exynos_phy->phy_base);
>> +
>> +    exynos_phy->drv_data = drv_data;
>> +
>> +    generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
>> +    if (IS_ERR(generic_phy)) {
>> +        dev_err(dev, "failed to create PHY\n");
>> +        return PTR_ERR(generic_phy);
>> +    }
>> +
>> +    phy_set_drvdata(generic_phy, exynos_phy);
>> +    phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +    return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static struct platform_driver exynos_pcie_phy_driver = {
>> +    .probe    = exynos_pcie_phy_probe,
>> +    .driver = {
>> +        .of_match_table    = exynos_pcie_phy_match,
>> +        .name        = "exynos_pcie_phy",
>> +    }
>> +};
>> +module_platform_driver(exynos_pcie_phy_driver);
>> +
>> +MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
>> +MODULE_AUTHOR("Jaehoon Chung<jh80.chung@samsung.com>");
>> +MODULE_LICENSE("GPL v2");
> 
> rest looks good to me.
> Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> 

Re: [PATCH V3 2/4] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 02/15/2017 02:24 PM, Vivek Gautam wrote:
> 
> On 02/13/2017 01:56 PM, Jaehoon Chung wrote:
>> This patch adds support for Generic PHY framework about Exynos SoCs.
>> Current Exynos PCIe driver doesn't use the PHY framework.
>> It's making a difficult to upstream the other Exynos variants because of
>> different PHY registers.
>>
>> Move the codes relevant to PHY from Exnyos PCIe driver to PHY Exynos PCIe
>> driver.
>>
>> Signed-off-by: Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> Acked-by: Krzysztof Kozlowski<krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Reviewed-by: Jingoo Han<jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Reviewed-by: Pankaj Dubey<pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> ---
>> Changelog on V3:
>> - Remove the dependency abot PCI_EXYNOS
>> - Adds a depends on COMPILE_TEST
>> - Use the readl_poll_timeout() instead of while()
>> - Fixes const type
>> - Adds MODULE_DESCRIPTION()/LICENCSE()/AUTHOR()
>> - Changes commit message
>>
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>   drivers/phy/Kconfig           |   8 ++
>>   drivers/phy/Makefile          |   1 +
>>   drivers/phy/phy-exynos-pcie.c | 285 ++++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 294 insertions(+)
>>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..8659f38 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,14 @@ config PHY_EXYNOS5_USBDRD
>>         This driver provides PHY interface for USB 3.0 DRD controller
>>         present on Exynos5 SoC series.
>>   +config PHY_EXYNOS_PCIE
>> +    bool "Exynos PCIe PHY driver"
>> +    depends on (ARCH_EXYNOS && OF) || COMPILE_TEST
> 
> this should be other way round if your driver runs only with OF enabled.
>           depends on OF && (ARCH_EXYNOS || COMPILE_TEST)

Will update.

> 
>> +    select GENERIC_PHY
>> +    help
>> +      Enable PCIe PHY support for Exynos SoC series.
>> +      This driver provides PHY interface for Exynos PCIe controller.
>> +
>>   config PHY_PISTACHIO_USB
>>       tristate "IMG Pistachio USB2.0 PHY driver"
>>       depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)    += phy-exynos4x12-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)    += phy-exynos5250-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)    += phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)    += phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)    += phy-exynos-pcie.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)    += phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)    += phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 0000000..9ec1855
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,285 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> 
> nit: copyright year.

Will do.

Thanks for reviewing.

Best Regards,
Jaehoon Chung

> 
>> + * Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET        0x000
>> +#define PCIE_PHY_COMMON_RESET        0x004
>> +#define PCIE_PHY_CMN_REG        0x008
>> +#define PCIE_PHY_MAC_RESET        0x00c
>> +#define PCIE_PHY_PLL_LOCKED        0x010
>> +#define PCIE_PHY_TRSVREG_RESET        0x020
>> +#define PCIE_PHY_TRSV_RESET        0x024
>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE        0x004
>> +#define PCIE_PHY_PLL_DIV_0        0x008
>> +#define PCIE_PHY_PLL_BIAS        0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK        0x014
>> +#define PCIE_PHY_PLL_DIV_1        0x05c
>> +#define PCIE_PHY_COMMON_POWER        0x064
>> +#define PCIE_PHY_COMMON_PD_CMN        BIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL        0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL        0x088
>> +#define PCIE_PHY_TRSV0_RXCDR        0x0ac
>> +#define PCIE_PHY_TRSV0_POWER        0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC        0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL        0x144
>> +#define PCIE_PHY_TRSV1_RXCDR        0x16c
>> +#define PCIE_PHY_TRSV1_POWER        0x184
>> +#define PCIE_PHY_TRSV1_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC        0x19c
>> +#define PCIE_PHY_TRSV2_EMP_LVL        0x204
>> +#define PCIE_PHY_TRSV2_RXCDR        0x22c
>> +#define PCIE_PHY_TRSV2_POWER        0x244
>> +#define PCIE_PHY_TRSV2_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV2_LVCC        0x25c
>> +#define PCIE_PHY_TRSV3_EMP_LVL        0x2c4
>> +#define PCIE_PHY_TRSV3_RXCDR        0x2ec
>> +#define PCIE_PHY_TRSV3_POWER        0x304
>> +#define PCIE_PHY_TRSV3_PD_TSV        BIT(7)
>> +#define PCIE_PHY_TRSV3_LVCC        0x31c
>> +
>> +struct exynos_pcie_phy_data {
>> +    const struct phy_ops    *ops;
>> +};
>> +
>> +/* For Exynos pcie phy */
>> +struct exynos_pcie_phy {
>> +    const struct exynos_pcie_phy_data *drv_data;
>> +    void __iomem *phy_base;
>> +    void __iomem *blk_base; /* For exynos5440 */
>> +};
>> +
>> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
>> +{
>> +    writel(val, base + offset);
>> +}
>> +
>> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
>> +{
>> +    return readl(base + offset);
>> +}
>> +
>> +/* For Exynos5440 specific functions */
>> +static int exynos5440_pcie_phy_init(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> +    /* DCC feedback control off */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
>> +
>> +    /* set TX/RX impedance */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
>> +
>> +    /* set 50Mhz PHY clock */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
>> +
>> +    /* set TX Differential output for lane 0 */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
>> +
>> +    /* set TX Pre-emphasis Level Control for lane 0 to minimum */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
>> +
>> +    /* set RX clock and data recovery bandwidth */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
>> +
>> +    /* change TX Pre-emphasis Level Control for lanes */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
>> +
>> +    /* set LVCC */
>> +    exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
>> +    exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
>> +
>> +    /* pulse for common reset */
>> +    exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
>> +    udelay(500);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +    u32 val;
>> +
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> +    val &= ~PCIE_PHY_COMMON_PD_CMN;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> +    val &= ~PCIE_PHY_TRSV0_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> +    val &= ~PCIE_PHY_TRSV1_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> +    val &= ~PCIE_PHY_TRSV2_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> +    val &= ~PCIE_PHY_TRSV3_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +    u32 val;
>> +
>> +    if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
>> +                (val != 0), 1, 500)) {
>> +        dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
>> +        return -ETIMEDOUT;
>> +    }
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
>> +    val |= PCIE_PHY_COMMON_PD_CMN;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
>> +    val |= PCIE_PHY_TRSV0_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
>> +    val |= PCIE_PHY_TRSV1_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
>> +    val |= PCIE_PHY_TRSV2_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
>> +
>> +    val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
>> +    val |= PCIE_PHY_TRSV3_PD_TSV;
>> +    exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
>> +
>> +    return 0;
>> +}
>> +
>> +static int exynos5440_pcie_phy_reset(struct phy *phy)
>> +{
>> +    struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
>> +
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
>> +    exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
>> +
>> +    return 0;
>> +}
>> +
>> +static const struct phy_ops exynos5440_phy_ops = {
>> +    .init        = exynos5440_pcie_phy_init,
>> +    .power_on    = exynos5440_pcie_phy_power_on,
>> +    .power_off    = exynos5440_pcie_phy_power_off,
>> +    .reset        = exynos5440_pcie_phy_reset,
>> +    .owner        = THIS_MODULE,
>> +};
>> +
>> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
>> +    .ops        = &exynos5440_phy_ops,
>> +};
>> +
>> +static const struct of_device_id exynos_pcie_phy_match[] = {
>> +    {
>> +        .compatible = "samsung,exynos5440-pcie-phy",
>> +        .data = &exynos5440_pcie_phy_data,
>> +    },
>> +    {},
>> +};
>> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
>> +
>> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
>> +{
>> +    struct device *dev = &pdev->dev;
>> +    struct exynos_pcie_phy *exynos_phy;
>> +    struct phy *generic_phy;
>> +    struct phy_provider *phy_provider;
>> +    struct resource *res;
>> +    const struct exynos_pcie_phy_data *drv_data;
>> +
>> +    drv_data = of_device_get_match_data(dev);
>> +    if (!drv_data)
>> +        return -ENODEV;
>> +
>> +    exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
>> +    if (!exynos_phy)
>> +        return -ENOMEM;
>> +
>> +    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +    exynos_phy->phy_base = devm_ioremap_resource(dev, res);
>> +    if (IS_ERR(exynos_phy->phy_base))
>> +        return PTR_ERR(exynos_phy->phy_base);
>> +
>> +    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
>> +    exynos_phy->blk_base = devm_ioremap_resource(dev, res);
>> +    if (IS_ERR(exynos_phy->phy_base))
>> +        return PTR_ERR(exynos_phy->phy_base);
>> +
>> +    exynos_phy->drv_data = drv_data;
>> +
>> +    generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
>> +    if (IS_ERR(generic_phy)) {
>> +        dev_err(dev, "failed to create PHY\n");
>> +        return PTR_ERR(generic_phy);
>> +    }
>> +
>> +    phy_set_drvdata(generic_phy, exynos_phy);
>> +    phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
>> +
>> +    return PTR_ERR_OR_ZERO(phy_provider);
>> +}
>> +
>> +static struct platform_driver exynos_pcie_phy_driver = {
>> +    .probe    = exynos_pcie_phy_probe,
>> +    .driver = {
>> +        .of_match_table    = exynos_pcie_phy_match,
>> +        .name        = "exynos_pcie_phy",
>> +    }
>> +};
>> +module_platform_driver(exynos_pcie_phy_driver);
>> +
>> +MODULE_DESCRIPTION("Samsung S5P/EXYNOS SoC PCIe PHY driver");
>> +MODULE_AUTHOR("Jaehoon Chung<jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>");
>> +MODULE_LICENSE("GPL v2");
> 
> rest looks good to me.
> Reviewed-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> 

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[PATCH V3 3/4] Documetation: binding: modify the exynos5440 pcie binding

[Jaehoon Chung]

According to using PHY framework, updates the exynos5440-pcie binding.
For maintaining backward compatibility, leaves the current dt-binding.
(It should be deprecated.)

Recommends to use the Phy Framework and "config" property to follow
the designware-pcie binding.
If you use the old way, can see "mssing *config* reg space" message.
Because the getting configuration space address from range is old way.

NOTE: When use the "config" property, first name of 'reg-names' must be
set to "elbi". Otherwise driver can't maintain the backward capability.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Changelog on V3:
- Fixes a typo

Changelog on V2:
- Describes more commit message
- Fixes the typos
- Adds the new example for using PHY framework
- Deprecated the old dt-binding description
- Removes 'phy-names'
 .../bindings/pci/samsung,exynos5440-pcie.txt       | 29 ++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d..7d3b094 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -7,8 +7,19 @@ Required properties:
 - compatible: "samsung,exynos5440-pcie"
 - reg: base addresses and lengths of the pcie controller,
 	the phy controller, additional register for the phy controller.
+	(Registers for the phy controller are DEPRECATED.
+	 Use the PHY framework.)
+- reg-names : First name should be set to "elbi".
+	And use the "config" instead of getting the confgiruation address space
+	from "ranges".
+	NOTE: When use the "config" property, reg-names must be set.
 - interrupts: A list of interrupt outputs for level interrupt,
 	pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+	Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+
+Other common properties refer to
+	Documentation/devicetree/binding/pci/designware-pcie.txt
 
 Example:
 
@@ -54,6 +65,24 @@ SoC specific DT Entry:
 		num-lanes = <4>;
 	};
 
+With using PHY framework:
+	pcie_phy0: pcie-phy@270000 {
+		...
+		reg = <0x270000 0x1000>, <0x271000 0x40>;
+		reg-names = "phy", "block";
+		...
+	};
+
+	pcie@290000 {
+		...
+		reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+		reg-names = "elbi", "config";
+		phys = <&pcie_phy0>;
+		ranges = <0x81000000 0 0	  0x60001000 0 0x00010000
+			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
+		...
+	};
+
 Board specific DT Entry:
 
 	pcie@290000 {
-- 
2.10.2

[PATCH V3 4/4] PCI: exynos: support the using PHY generic framework

[Jaehoon Chung]

Switch the pci-exynos driver to generic PHY framework. At the same time
backward compatibility is preserved: Warning will be printed for old
DTB.

Refer to the binding file:
- Documentation/devictree/bindings/pci/samsung,exynos5440-pcie.txt

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
Changelog on V3:
- Changes the commit-message
- Fixes the merge conflict

Changelog on V2:
- This patch is split from previous PATCH[1/4]
- Maintain the backward compatibility
- Adds 'using_phy' for cheching whether phy framework is used or not
- Adds 'DEPRECATED' message for old dt-binding way

 drivers/pci/host/pci-exynos.c | 54 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 50 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index 758906b..f6a8b6e 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -21,6 +21,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/phy/phy.h>
 #include <linux/resource.h>
 #include <linux/signal.h>
 #include <linux/types.h>
@@ -110,6 +111,10 @@ struct exynos_pcie {
 	struct exynos_pcie_clk_res	*clk_res;
 	const struct exynos_pcie_ops	*ops;
 	int				reset_gpio;
+
+	/* For Generic PHY Framework */
+	bool				using_phy;
+	struct phy			*phy;
 };
 
 struct exynos_pcie_ops {
@@ -126,6 +131,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
 	struct resource *res;
 	struct device *dev = ep->pp.dev;
 
+	/* If using the PHY framework, doesn't need to get other resource */
+	if (ep->using_phy)
+		return 0;
+
 	ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
 	if (!ep->mem_res)
 		return -ENOMEM;
@@ -396,10 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
 	}
 
 	exynos_pcie_assert_core_reset(ep);
-	exynos_pcie_assert_phy_reset(ep);
-	exynos_pcie_deassert_phy_reset(ep);
-	exynos_pcie_power_on_phy(ep);
-	exynos_pcie_init_phy(ep);
+
+	if (ep->using_phy) {
+		phy_reset(ep->phy);
+
+		exynos_pcie_writel(ep->mem_res->elbi_base, 1,
+				PCIE_PWR_RESET);
+
+		phy_power_on(ep->phy);
+		phy_init(ep->phy);
+	} else {
+		exynos_pcie_assert_phy_reset(ep);
+		exynos_pcie_deassert_phy_reset(ep);
+		exynos_pcie_power_on_phy(ep);
+		exynos_pcie_init_phy(ep);
+
+		/* pulse for common reset */
+		exynos_pcie_writel(ep->mem_res->block_base, 1,
+					PCIE_PHY_COMMON_RESET);
+		udelay(500);
+		exynos_pcie_writel(ep->mem_res->block_base, 0,
+					PCIE_PHY_COMMON_RESET);
+	}
 
 	/* pulse for common reset */
 	exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET);
@@ -418,6 +445,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
 	if (!dw_pcie_wait_for_link(pp))
 		return 0;
 
+	if (ep->using_phy) {
+		phy_power_off(ep->phy);
+		return -ETIMEDOUT;
+	}
+
 	while (exynos_pcie_readl(ep->mem_res->phy_base,
 				PCIE_PHY_PLL_LOCKED) == 0) {
 		val = exynos_pcie_readl(ep->mem_res->block_base,
@@ -624,6 +656,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 
 	ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 
+	/* Assume that controller doesn't use the PHY framework */
+	ep->using_phy = false;
+
+	ep->phy = devm_of_phy_get(dev, np, NULL);
+	if (IS_ERR(ep->phy)) {
+		if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
+			return PTR_ERR(ep->phy);
+		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
+	} else
+		ep->using_phy = true;
+
 	if (ep->ops && ep->ops->get_mem_resources) {
 		ret = ep->ops->get_mem_resources(pdev, ep);
 		if (ret)
@@ -647,6 +690,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	return 0;
 
 fail_probe:
+	if (ep->using_phy)
+		phy_exit(ep->phy);
+
 	if (ep->ops && ep->ops->deinit_clk_resources)
 		ep->ops->deinit_clk_resources(ep);
 	return ret;
-- 
2.10.2

Re: [PATCH V3 4/4] PCI: exynos: support the using PHY generic framework

[Bjorn Helgaas]

On Mon, Feb 13, 2017 at 05:26:13PM +0900, Jaehoon Chung wrote:
> Switch the pci-exynos driver to generic PHY framework. At the same time
> backward compatibility is preserved: Warning will be printed for old
> DTB.
> 
> Refer to the binding file:
> - Documentation/devictree/bindings/pci/samsung,exynos5440-pcie.txt
> 
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Jingoo Han <jingoohan1@gmail.com>
> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

Acked-by: Bjorn Helgaas <bhelgaas@google.com>

> ---
> Changelog on V3:
> - Changes the commit-message
> - Fixes the merge conflict
> 
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
> 
>  drivers/pci/host/pci-exynos.c | 54 +++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 50 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 758906b..f6a8b6e 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
>  #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
>  	struct exynos_pcie_clk_res	*clk_res;
>  	const struct exynos_pcie_ops	*ops;
>  	int				reset_gpio;
> +
> +	/* For Generic PHY Framework */
> +	bool				using_phy;
> +	struct phy			*phy;
>  };
>  
>  struct exynos_pcie_ops {
> @@ -126,6 +131,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>  	struct resource *res;
>  	struct device *dev = ep->pp.dev;
>  
> +	/* If using the PHY framework, doesn't need to get other resource */
> +	if (ep->using_phy)
> +		return 0;
> +
>  	ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>  	if (!ep->mem_res)
>  		return -ENOMEM;
> @@ -396,10 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
>  	}
>  
>  	exynos_pcie_assert_core_reset(ep);
> -	exynos_pcie_assert_phy_reset(ep);
> -	exynos_pcie_deassert_phy_reset(ep);
> -	exynos_pcie_power_on_phy(ep);
> -	exynos_pcie_init_phy(ep);
> +
> +	if (ep->using_phy) {
> +		phy_reset(ep->phy);
> +
> +		exynos_pcie_writel(ep->mem_res->elbi_base, 1,
> +				PCIE_PWR_RESET);
> +
> +		phy_power_on(ep->phy);
> +		phy_init(ep->phy);
> +	} else {
> +		exynos_pcie_assert_phy_reset(ep);
> +		exynos_pcie_deassert_phy_reset(ep);
> +		exynos_pcie_power_on_phy(ep);
> +		exynos_pcie_init_phy(ep);
> +
> +		/* pulse for common reset */
> +		exynos_pcie_writel(ep->mem_res->block_base, 1,
> +					PCIE_PHY_COMMON_RESET);
> +		udelay(500);
> +		exynos_pcie_writel(ep->mem_res->block_base, 0,
> +					PCIE_PHY_COMMON_RESET);
> +	}
>  
>  	/* pulse for common reset */
>  	exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET);
> @@ -418,6 +445,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
>  	if (!dw_pcie_wait_for_link(pp))
>  		return 0;
>  
> +	if (ep->using_phy) {
> +		phy_power_off(ep->phy);
> +		return -ETIMEDOUT;
> +	}
> +
>  	while (exynos_pcie_readl(ep->mem_res->phy_base,
>  				PCIE_PHY_PLL_LOCKED) == 0) {
>  		val = exynos_pcie_readl(ep->mem_res->block_base,
> @@ -624,6 +656,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  
>  	ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>  
> +	/* Assume that controller doesn't use the PHY framework */
> +	ep->using_phy = false;
> +
> +	ep->phy = devm_of_phy_get(dev, np, NULL);
> +	if (IS_ERR(ep->phy)) {
> +		if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
> +			return PTR_ERR(ep->phy);
> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
> +	} else
> +		ep->using_phy = true;
> +
>  	if (ep->ops && ep->ops->get_mem_resources) {
>  		ret = ep->ops->get_mem_resources(pdev, ep);
>  		if (ret)
> @@ -647,6 +690,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  	return 0;
>  
>  fail_probe:
> +	if (ep->using_phy)
> +		phy_exit(ep->phy);
> +
>  	if (ep->ops && ep->ops->deinit_clk_resources)
>  		ep->ops->deinit_clk_resources(ep);
>  	return ret;
> -- 
> 2.10.2
> 

Re: [PATCH V3 4/4] PCI: exynos: support the using PHY generic framework

[Bjorn Helgaas]

On Mon, Feb 13, 2017 at 05:26:13PM +0900, Jaehoon Chung wrote:
> Switch the pci-exynos driver to generic PHY framework. At the same time
> backward compatibility is preserved: Warning will be printed for old
> DTB.
> 
> Refer to the binding file:
> - Documentation/devictree/bindings/pci/samsung,exynos5440-pcie.txt
> 
> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Acked-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Acked-by: Jingoo Han <jingoohan1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Reviewed-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Alim Akhtar <alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

Acked-by: Bjorn Helgaas <bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>

> ---
> Changelog on V3:
> - Changes the commit-message
> - Fixes the merge conflict
> 
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
> 
>  drivers/pci/host/pci-exynos.c | 54 +++++++++++++++++++++++++++++++++++++++----
>  1 file changed, 50 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index 758906b..f6a8b6e 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
>  #include <linux/of_gpio.h>
>  #include <linux/pci.h>
>  #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
>  #include <linux/resource.h>
>  #include <linux/signal.h>
>  #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
>  	struct exynos_pcie_clk_res	*clk_res;
>  	const struct exynos_pcie_ops	*ops;
>  	int				reset_gpio;
> +
> +	/* For Generic PHY Framework */
> +	bool				using_phy;
> +	struct phy			*phy;
>  };
>  
>  struct exynos_pcie_ops {
> @@ -126,6 +131,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
>  	struct resource *res;
>  	struct device *dev = ep->pp.dev;
>  
> +	/* If using the PHY framework, doesn't need to get other resource */
> +	if (ep->using_phy)
> +		return 0;
> +
>  	ep->mem_res = devm_kzalloc(dev, sizeof(*ep->mem_res), GFP_KERNEL);
>  	if (!ep->mem_res)
>  		return -ENOMEM;
> @@ -396,10 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
>  	}
>  
>  	exynos_pcie_assert_core_reset(ep);
> -	exynos_pcie_assert_phy_reset(ep);
> -	exynos_pcie_deassert_phy_reset(ep);
> -	exynos_pcie_power_on_phy(ep);
> -	exynos_pcie_init_phy(ep);
> +
> +	if (ep->using_phy) {
> +		phy_reset(ep->phy);
> +
> +		exynos_pcie_writel(ep->mem_res->elbi_base, 1,
> +				PCIE_PWR_RESET);
> +
> +		phy_power_on(ep->phy);
> +		phy_init(ep->phy);
> +	} else {
> +		exynos_pcie_assert_phy_reset(ep);
> +		exynos_pcie_deassert_phy_reset(ep);
> +		exynos_pcie_power_on_phy(ep);
> +		exynos_pcie_init_phy(ep);
> +
> +		/* pulse for common reset */
> +		exynos_pcie_writel(ep->mem_res->block_base, 1,
> +					PCIE_PHY_COMMON_RESET);
> +		udelay(500);
> +		exynos_pcie_writel(ep->mem_res->block_base, 0,
> +					PCIE_PHY_COMMON_RESET);
> +	}
>  
>  	/* pulse for common reset */
>  	exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_COMMON_RESET);
> @@ -418,6 +445,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *ep)
>  	if (!dw_pcie_wait_for_link(pp))
>  		return 0;
>  
> +	if (ep->using_phy) {
> +		phy_power_off(ep->phy);
> +		return -ETIMEDOUT;
> +	}
> +
>  	while (exynos_pcie_readl(ep->mem_res->phy_base,
>  				PCIE_PHY_PLL_LOCKED) == 0) {
>  		val = exynos_pcie_readl(ep->mem_res->block_base,
> @@ -624,6 +656,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  
>  	ep->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>  
> +	/* Assume that controller doesn't use the PHY framework */
> +	ep->using_phy = false;
> +
> +	ep->phy = devm_of_phy_get(dev, np, NULL);
> +	if (IS_ERR(ep->phy)) {
> +		if (PTR_ERR(ep->phy) == -EPROBE_DEFER)
> +			return PTR_ERR(ep->phy);
> +		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
> +	} else
> +		ep->using_phy = true;
> +
>  	if (ep->ops && ep->ops->get_mem_resources) {
>  		ret = ep->ops->get_mem_resources(pdev, ep);
>  		if (ret)
> @@ -647,6 +690,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>  	return 0;
>  
>  fail_probe:
> +	if (ep->using_phy)
> +		phy_exit(ep->phy);
> +
>  	if (ep->ops && ep->ops->deinit_clk_resources)
>  		ep->ops->deinit_clk_resources(ep);
>  	return ret;
> -- 
> 2.10.2
> 
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Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Bjorn Helgaas]

On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
> This patcheset is for using PHY generic framework.
> Current pci-exyns doesn't use the phy framework since there haven't been on
> PHY subsystem when Exynos5440 had bean upstreamed.
> It's making a difficult to upstream the other Exynos variants because of different
> PHY registers.
> 
> This patcheset has the below modifications:
> 1) Introduces the phy-exynos-pcie
> 2) Handles PHY register from PHY framework for pci-exynos
> 3) Modifies the dt-binding of pci-exynos
> 4) Maintains the backward compatibility
> 
> Changelog on V3:
> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
>   : Will send this patch after applying this patchset.
> - Fixes typo
> - Based on latest PCI git repository (host-exynos branch)
> - Changes commit message
> - Removes the dependency
> 
> Changelog on V2:
> - Keep current codes for backward compatibility
> - Fixes some typos
> - Split the patches for removing the dependency
> - Removes the unnecessary codes
> - Change the patch's sequence
> - Based on latest PCI git repository.(next branch)
> 
> Jaehoon Chung (4):
>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>   Documetation: binding: modify the exynos5440 pcie binding
>   PCI: exynos: support the using PHY generic framework
> 
>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>  drivers/pci/host/pci-exynos.c                      |  54 +++-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
>  6 files changed, 390 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c

Kishon, how do you want to handle this series?  The bulk of the
changes are in drivers/phy.  I acked the drivers/pci patch, so you can
add that and apply the whole series if you want.  Otherwise, if you
ack the PHY part, I can apply the whole thing.  Either is fine with
me; just let me know.

Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Bjorn Helgaas]

On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
> This patcheset is for using PHY generic framework.
> Current pci-exyns doesn't use the phy framework since there haven't been on
> PHY subsystem when Exynos5440 had bean upstreamed.
> It's making a difficult to upstream the other Exynos variants because of different
> PHY registers.
> 
> This patcheset has the below modifications:
> 1) Introduces the phy-exynos-pcie
> 2) Handles PHY register from PHY framework for pci-exynos
> 3) Modifies the dt-binding of pci-exynos
> 4) Maintains the backward compatibility
> 
> Changelog on V3:
> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
>   : Will send this patch after applying this patchset.
> - Fixes typo
> - Based on latest PCI git repository (host-exynos branch)
> - Changes commit message
> - Removes the dependency
> 
> Changelog on V2:
> - Keep current codes for backward compatibility
> - Fixes some typos
> - Split the patches for removing the dependency
> - Removes the unnecessary codes
> - Change the patch's sequence
> - Based on latest PCI git repository.(next branch)
> 
> Jaehoon Chung (4):
>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>   Documetation: binding: modify the exynos5440 pcie binding
>   PCI: exynos: support the using PHY generic framework
> 
>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>  drivers/pci/host/pci-exynos.c                      |  54 +++-
>  drivers/phy/Kconfig                                |   8 +
>  drivers/phy/Makefile                               |   1 +
>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
>  6 files changed, 390 insertions(+), 4 deletions(-)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c

I made the updates Vivek suggested and provisionally added these to my
pci/host-exynos branch to get some build testing.

Kishon, I guess it probably makes more sense for me to apply this
because even though the drivers/pci changes are small, I think they
depend on other pci-exynos.c changes that are on my branch but not in
Linus' tree yet.

Bjorn

Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Jaehoon Chung]

Dear Bjorn,

On 02/16/2017 06:11 AM, Bjorn Helgaas wrote:
> On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
>> This patcheset is for using PHY generic framework.
>> Current pci-exyns doesn't use the phy framework since there haven't been on
>> PHY subsystem when Exynos5440 had bean upstreamed.
>> It's making a difficult to upstream the other Exynos variants because of different
>> PHY registers.
>>
>> This patcheset has the below modifications:
>> 1) Introduces the phy-exynos-pcie
>> 2) Handles PHY register from PHY framework for pci-exynos
>> 3) Modifies the dt-binding of pci-exynos
>> 4) Maintains the backward compatibility
>>
>> Changelog on V3:
>> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
>>   : Will send this patch after applying this patchset.
>> - Fixes typo
>> - Based on latest PCI git repository (host-exynos branch)
>> - Changes commit message
>> - Removes the dependency
>>
>> Changelog on V2:
>> - Keep current codes for backward compatibility
>> - Fixes some typos
>> - Split the patches for removing the dependency
>> - Removes the unnecessary codes
>> - Change the patch's sequence
>> - Based on latest PCI git repository.(next branch)
>>
>> Jaehoon Chung (4):
>>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>>   Documetation: binding: modify the exynos5440 pcie binding
>>   PCI: exynos: support the using PHY generic framework
>>
>>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>>  drivers/pci/host/pci-exynos.c                      |  54 +++-
>>  drivers/phy/Kconfig                                |   8 +
>>  drivers/phy/Makefile                               |   1 +
>>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
>>  6 files changed, 390 insertions(+), 4 deletions(-)
>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 
> I made the updates Vivek suggested and provisionally added these to my
> pci/host-exynos branch to get some build testing.

Thanks!

> 
> Kishon, I guess it probably makes more sense for me to apply this
> because even though the drivers/pci changes are small, I think they
> depend on other pci-exynos.c changes that are on my branch but not in
> Linus' tree yet.

I will send the patches relevant to Exynos5433(TM2) soon..
Thanks a lot.

Best Regards,
Jaehoon Chung

> 
> Bjorn
> 
> 
> 

Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Bjorn Helgaas]

On Thu, Feb 16, 2017 at 07:33:15AM +0900, Jaehoon Chung wrote:
> Dear Bjorn,
> 
> On 02/16/2017 06:11 AM, Bjorn Helgaas wrote:
> > On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
> >> This patcheset is for using PHY generic framework.
> >> Current pci-exyns doesn't use the phy framework since there haven't been on
> >> PHY subsystem when Exynos5440 had bean upstreamed.
> >> It's making a difficult to upstream the other Exynos variants because of different
> >> PHY registers.
> >>
> >> This patcheset has the below modifications:
> >> 1) Introduces the phy-exynos-pcie
> >> 2) Handles PHY register from PHY framework for pci-exynos
> >> 3) Modifies the dt-binding of pci-exynos
> >> 4) Maintains the backward compatibility
> >>
> >> Changelog on V3:
> >> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
> >>   : Will send this patch after applying this patchset.
> >> - Fixes typo
> >> - Based on latest PCI git repository (host-exynos branch)
> >> - Changes commit message
> >> - Removes the dependency
> >>
> >> Changelog on V2:
> >> - Keep current codes for backward compatibility
> >> - Fixes some typos
> >> - Split the patches for removing the dependency
> >> - Removes the unnecessary codes
> >> - Change the patch's sequence
> >> - Based on latest PCI git repository.(next branch)
> >>
> >> Jaehoon Chung (4):
> >>   Documetation: samsung-phy: add the exynos-pcie-phy binding
> >>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
> >>   Documetation: binding: modify the exynos5440 pcie binding
> >>   PCI: exynos: support the using PHY generic framework
> >>
> >>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
> >>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
> >>  drivers/pci/host/pci-exynos.c                      |  54 +++-
> >>  drivers/phy/Kconfig                                |   8 +
> >>  drivers/phy/Makefile                               |   1 +
> >>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
> >>  6 files changed, 390 insertions(+), 4 deletions(-)
> >>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> > 
> > I made the updates Vivek suggested and provisionally added these to my
> > pci/host-exynos branch to get some build testing.
> 
> Thanks!
> 
> > 
> > Kishon, I guess it probably makes more sense for me to apply this
> > because even though the drivers/pci changes are small, I think they
> > depend on other pci-exynos.c changes that are on my branch but not in
> > Linus' tree yet.

I haven't heard from Kishon, but I merged these to my -next branch for
v4.11.

Bjorn

Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Bjorn Helgaas]

On Thu, Feb 16, 2017 at 07:33:15AM +0900, Jaehoon Chung wrote:
> Dear Bjorn,
> 
> On 02/16/2017 06:11 AM, Bjorn Helgaas wrote:
> > On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
> >> This patcheset is for using PHY generic framework.
> >> Current pci-exyns doesn't use the phy framework since there haven't been on
> >> PHY subsystem when Exynos5440 had bean upstreamed.
> >> It's making a difficult to upstream the other Exynos variants because of different
> >> PHY registers.
> >>
> >> This patcheset has the below modifications:
> >> 1) Introduces the phy-exynos-pcie
> >> 2) Handles PHY register from PHY framework for pci-exynos
> >> 3) Modifies the dt-binding of pci-exynos
> >> 4) Maintains the backward compatibility
> >>
> >> Changelog on V3:
> >> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
> >>   : Will send this patch after applying this patchset.
> >> - Fixes typo
> >> - Based on latest PCI git repository (host-exynos branch)
> >> - Changes commit message
> >> - Removes the dependency
> >>
> >> Changelog on V2:
> >> - Keep current codes for backward compatibility
> >> - Fixes some typos
> >> - Split the patches for removing the dependency
> >> - Removes the unnecessary codes
> >> - Change the patch's sequence
> >> - Based on latest PCI git repository.(next branch)
> >>
> >> Jaehoon Chung (4):
> >>   Documetation: samsung-phy: add the exynos-pcie-phy binding
> >>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
> >>   Documetation: binding: modify the exynos5440 pcie binding
> >>   PCI: exynos: support the using PHY generic framework
> >>
> >>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
> >>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
> >>  drivers/pci/host/pci-exynos.c                      |  54 +++-
> >>  drivers/phy/Kconfig                                |   8 +
> >>  drivers/phy/Makefile                               |   1 +
> >>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
> >>  6 files changed, 390 insertions(+), 4 deletions(-)
> >>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> > 
> > I made the updates Vivek suggested and provisionally added these to my
> > pci/host-exynos branch to get some build testing.
> 
> Thanks!
> 
> > 
> > Kishon, I guess it probably makes more sense for me to apply this
> > because even though the drivers/pci changes are small, I think they
> > depend on other pci-exynos.c changes that are on my branch but not in
> > Linus' tree yet.

I haven't heard from Kishon, but I merged these to my -next branch for
v4.11.

Bjorn
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Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Kishon Vijay Abraham I]

Hi Bjorn,

On Saturday 18 February 2017 01:21 AM, Bjorn Helgaas wrote:
> On Thu, Feb 16, 2017 at 07:33:15AM +0900, Jaehoon Chung wrote:
>> Dear Bjorn,
>>
>> On 02/16/2017 06:11 AM, Bjorn Helgaas wrote:
>>> On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
>>>> This patcheset is for using PHY generic framework.
>>>> Current pci-exyns doesn't use the phy framework since there haven't been on
>>>> PHY subsystem when Exynos5440 had bean upstreamed.
>>>> It's making a difficult to upstream the other Exynos variants because of different
>>>> PHY registers.
>>>>
>>>> This patcheset has the below modifications:
>>>> 1) Introduces the phy-exynos-pcie
>>>> 2) Handles PHY register from PHY framework for pci-exynos
>>>> 3) Modifies the dt-binding of pci-exynos
>>>> 4) Maintains the backward compatibility
>>>>
>>>> Changelog on V3:
>>>> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
>>>>   : Will send this patch after applying this patchset.
>>>> - Fixes typo
>>>> - Based on latest PCI git repository (host-exynos branch)
>>>> - Changes commit message
>>>> - Removes the dependency
>>>>
>>>> Changelog on V2:
>>>> - Keep current codes for backward compatibility
>>>> - Fixes some typos
>>>> - Split the patches for removing the dependency
>>>> - Removes the unnecessary codes
>>>> - Change the patch's sequence
>>>> - Based on latest PCI git repository.(next branch)
>>>>
>>>> Jaehoon Chung (4):
>>>>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>>>>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>>>>   Documetation: binding: modify the exynos5440 pcie binding
>>>>   PCI: exynos: support the using PHY generic framework
>>>>
>>>>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>>>>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>>>>  drivers/pci/host/pci-exynos.c                      |  54 +++-
>>>>  drivers/phy/Kconfig                                |   8 +
>>>>  drivers/phy/Makefile                               |   1 +
>>>>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
>>>>  6 files changed, 390 insertions(+), 4 deletions(-)
>>>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> I made the updates Vivek suggested and provisionally added these to my
>>> pci/host-exynos branch to get some build testing.
>>
>> Thanks!
>>
>>>
>>> Kishon, I guess it probably makes more sense for me to apply this
>>> because even though the drivers/pci changes are small, I think they
>>> depend on other pci-exynos.c changes that are on my branch but not in
>>> Linus' tree yet.
> 
> I haven't heard from Kishon, but I merged these to my -next branch for
> v4.11.

I might have missed this one. Thanks for taking the patches.

Thanks
Kishon

Re: [PATCH V3 0/4] PCI: exynos: use the PHY generic framework

[Kishon Vijay Abraham I]

Hi Bjorn,

On Saturday 18 February 2017 01:21 AM, Bjorn Helgaas wrote:
> On Thu, Feb 16, 2017 at 07:33:15AM +0900, Jaehoon Chung wrote:
>> Dear Bjorn,
>>
>> On 02/16/2017 06:11 AM, Bjorn Helgaas wrote:
>>> On Mon, Feb 13, 2017 at 05:26:09PM +0900, Jaehoon Chung wrote:
>>>> This patcheset is for using PHY generic framework.
>>>> Current pci-exyns doesn't use the phy framework since there haven't been on
>>>> PHY subsystem when Exynos5440 had bean upstreamed.
>>>> It's making a difficult to upstream the other Exynos variants because of different
>>>> PHY registers.
>>>>
>>>> This patcheset has the below modifications:
>>>> 1) Introduces the phy-exynos-pcie
>>>> 2) Handles PHY register from PHY framework for pci-exynos
>>>> 3) Modifies the dt-binding of pci-exynos
>>>> 4) Maintains the backward compatibility
>>>>
>>>> Changelog on V3:
>>>> - Drops "ARM: dts: exynos5440: support the phy-pcie node of pcie"
>>>>   : Will send this patch after applying this patchset.
>>>> - Fixes typo
>>>> - Based on latest PCI git repository (host-exynos branch)
>>>> - Changes commit message
>>>> - Removes the dependency
>>>>
>>>> Changelog on V2:
>>>> - Keep current codes for backward compatibility
>>>> - Fixes some typos
>>>> - Split the patches for removing the dependency
>>>> - Removes the unnecessary codes
>>>> - Change the patch's sequence
>>>> - Based on latest PCI git repository.(next branch)
>>>>
>>>> Jaehoon Chung (4):
>>>>   Documetation: samsung-phy: add the exynos-pcie-phy binding
>>>>   phy: phy-exynos-pcie: Add support for Exynos PCIe phy
>>>>   Documetation: binding: modify the exynos5440 pcie binding
>>>>   PCI: exynos: support the using PHY generic framework
>>>>
>>>>  .../bindings/pci/samsung,exynos5440-pcie.txt       |  29 +++
>>>>  .../devicetree/bindings/phy/samsung-phy.txt        |  17 ++
>>>>  drivers/pci/host/pci-exynos.c                      |  54 +++-
>>>>  drivers/phy/Kconfig                                |   8 +
>>>>  drivers/phy/Makefile                               |   1 +
>>>>  drivers/phy/phy-exynos-pcie.c                      | 285 +++++++++++++++++++++
>>>>  6 files changed, 390 insertions(+), 4 deletions(-)
>>>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> I made the updates Vivek suggested and provisionally added these to my
>>> pci/host-exynos branch to get some build testing.
>>
>> Thanks!
>>
>>>
>>> Kishon, I guess it probably makes more sense for me to apply this
>>> because even though the drivers/pci changes are small, I think they
>>> depend on other pci-exynos.c changes that are on my branch but not in
>>> Linus' tree yet.
> 
> I haven't heard from Kishon, but I merged these to my -next branch for
> v4.11.

I might have missed this one. Thanks for taking the patches.

Thanks
Kishon