From: anurupvasu@gmail.com (Anurup M)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow
Date: Mon, 27 Mar 2017 12:03:24 +0530 [thread overview]
Message-ID: <58D8B234.3020004@gmail.com> (raw)
In-Reply-To: <20170324114325.GC22771@leverpostej>
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
>>> How do we ensure that we don't take the interrupt in the middle of a
>>> > >sequence of accesses to the HW?
>> >
>> >The L3 cache and MN PMU does not use the overflow IRQ and it does
>> >not occur here
>> >as the interrupt Mask register is by default masked in hardware.
> I was referring to the timer interrupt which backs the hrtimer.
>
> i.e. how do we guarantee that hisi_hrtimer_callback() is not called
> while we are in the middle of a RMW sequence? Are interrupts disabled
> for all of those seqeunces?
The HW access via djtag read and write are protected by spin_lock_irqsave.
Thanks,
Anurup
> Thanks,
> Mark.
WARNING: multiple messages have this Message-ID (diff)
From: Anurup M <anurupvasu@gmail.com>
To: Mark Rutland <mark.rutland@arm.com>
Cc: will.deacon@arm.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com,
zhangshaokun@hisilicon.com, tanxiaojun@huawei.com,
xuwei5@hisilicon.com, sanil.kumar@hisilicon.com,
john.garry@huawei.com, gabriele.paoloni@huawei.com,
shiju.jose@huawei.com, huangdaode@hisilicon.com,
linuxarm@huawei.com, dikshit.n@huawei.com, shyju.pv@huawei.com
Subject: Re: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow
Date: Mon, 27 Mar 2017 12:03:24 +0530 [thread overview]
Message-ID: <58D8B234.3020004@gmail.com> (raw)
In-Reply-To: <20170324114325.GC22771@leverpostej>
On Friday 24 March 2017 05:13 PM, Mark Rutland wrote:
>>> How do we ensure that we don't take the interrupt in the middle of a
>>> > >sequence of accesses to the HW?
>> >
>> >The L3 cache and MN PMU does not use the overflow IRQ and it does
>> >not occur here
>> >as the interrupt Mask register is by default masked in hardware.
> I was referring to the timer interrupt which backs the hrtimer.
>
> i.e. how do we guarantee that hisi_hrtimer_callback() is not called
> while we are in the middle of a RMW sequence? Are interrupts disabled
> for all of those seqeunces?
The HW access via djtag read and write are protected by spin_lock_irqsave.
Thanks,
Anurup
> Thanks,
> Mark.
next prev parent reply other threads:[~2017-03-27 6:33 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-10 6:28 [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow Anurup M
2017-03-10 6:28 ` Anurup M
2017-03-21 17:16 ` Mark Rutland
2017-03-21 17:16 ` Mark Rutland
2017-03-24 6:43 ` Anurup M
2017-03-24 6:43 ` Anurup M
2017-03-24 11:43 ` Mark Rutland
2017-03-24 11:43 ` Mark Rutland
2017-03-27 6:33 ` Anurup M [this message]
2017-03-27 6:33 ` Anurup M
2017-03-28 11:09 ` Mark Rutland
2017-03-28 11:09 ` Mark Rutland
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