From: "Zhang, Jerry (Junwei)" <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
To: Chunming Zhou <David1.Zhou-5C7GfCeVMHo@public.gmane.org>,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
Christian.Koenig-5C7GfCeVMHo@public.gmane.org,
Alexander.Deucher-5C7GfCeVMHo@public.gmane.org
Subject: Re: [PATCH 05/15] drm/amdgpu: handle multi level PD size calculation
Date: Tue, 28 Mar 2017 10:41:13 +0800 [thread overview]
Message-ID: <58D9CD49.1040809@amd.com> (raw)
In-Reply-To: <1490594005-14553-6-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
On 03/27/2017 01:53 PM, Chunming Zhou wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Allows us to get the size for all levels as well.
>
> Change-Id: Iaf2f9b2bf19c3623018a2215f8cf01a61bdbe8ea
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 ++++++++++++++++++++++------------
> 1 file changed, 22 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 9172954..90494ce 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -76,27 +76,37 @@ struct amdgpu_pte_update_params {
> };
>
> /**
> - * amdgpu_vm_num_pde - return the number of page directory entries
> + * amdgpu_vm_num_entries - return the number of entries in a PD/PT
> *
> * @adev: amdgpu_device pointer
> *
> - * Calculate the number of page directory entries.
> + * Calculate the number of entries in a page directory or page table.
> */
> -static unsigned amdgpu_vm_num_pdes(struct amdgpu_device *adev)
> +static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> + unsigned level)
> {
> - return adev->vm_manager.max_pfn >> amdgpu_vm_block_size;
> + if (level == 0)
> + /* For the root directory */
> + return adev->vm_manager.max_pfn >>
> + (amdgpu_vm_block_size * adev->vm_manager.num_level);
> + else if (level == adev->vm_manager.num_level)
> + /* For the page tables on the leaves */
> + return AMDGPU_VM_PTE_COUNT;
> + else
> + /* Everything in between */
> + return 1 << amdgpu_vm_block_size;
We may use AMDGPU_VM_PTE_COUNT directly.
BTW, each PT size is same as amdgpu_vm_block_size.
Jerry
> }
>
> /**
> - * amdgpu_vm_directory_size - returns the size of the page directory in bytes
> + * amdgpu_vm_bo_size - returns the size of the BOs in bytes
> *
> * @adev: amdgpu_device pointer
> *
> - * Calculate the size of the page directory in bytes.
> + * Calculate the size of the BO for a page directory or page table in bytes.
> */
> -static unsigned amdgpu_vm_directory_size(struct amdgpu_device *adev)
> +static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
> {
> - return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_pdes(adev) * 8);
> + return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
> }
>
> /**
> @@ -1393,7 +1403,7 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
> saddr >>= amdgpu_vm_block_size;
> eaddr >>= amdgpu_vm_block_size;
>
> - BUG_ON(eaddr >= amdgpu_vm_num_pdes(adev));
> + BUG_ON(eaddr >= amdgpu_vm_num_entries(adev, 0));
>
> if (eaddr > vm->root.last_entry_used)
> vm->root.last_entry_used = eaddr;
> @@ -1576,8 +1586,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm)
> INIT_LIST_HEAD(&vm->cleared);
> INIT_LIST_HEAD(&vm->freed);
>
> - pd_size = amdgpu_vm_directory_size(adev);
> - pd_entries = amdgpu_vm_num_pdes(adev);
> + pd_size = amdgpu_vm_bo_size(adev, 0);
> + pd_entries = amdgpu_vm_num_entries(adev, 0);
>
> /* allocate page table array */
> vm->root.entries = drm_calloc_large(pd_entries,
> @@ -1662,7 +1672,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
> kfree(mapping);
> }
>
> - for (i = 0; i < amdgpu_vm_num_pdes(adev); i++) {
> + for (i = 0; i < amdgpu_vm_num_entries(adev, 0); i++) {
> struct amdgpu_bo *pt = vm->root.entries[i].bo;
>
> if (!pt)
>
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next prev parent reply other threads:[~2017-03-28 2:41 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-27 5:53 [PATCH 00/15] *** Multiple level VMPT enablement *** Chunming Zhou
[not found] ` <1490594005-14553-1-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-27 5:53 ` [PATCH 01/15] drm/amdgpu: rename page_directory_fence to last_dir_update Chunming Zhou
2017-03-27 5:53 ` [PATCH 02/15] drm/amdgpu: add the VM pointer to the amdgpu_pte_update_params as well Chunming Zhou
2017-03-27 5:53 ` [PATCH 03/15] drm/amdgpu: add num_level to the VM manager Chunming Zhou
[not found] ` <1490594005-14553-4-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-27 17:05 ` William Lewis
2017-03-27 5:53 ` [PATCH 04/15] drm/amdgpu: generalize page table level Chunming Zhou
2017-03-27 5:53 ` [PATCH 05/15] drm/amdgpu: handle multi level PD size calculation Chunming Zhou
[not found] ` <1490594005-14553-6-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28 2:41 ` Zhang, Jerry (Junwei) [this message]
2017-03-27 5:53 ` [PATCH 06/15] drm/amdgpu: handle multi level PD during validation Chunming Zhou
2017-03-27 5:53 ` [PATCH 07/15] drm/amdgpu: handle multi level PD in the LRU Chunming Zhou
2017-03-27 5:53 ` [PATCH 08/15] drm/amdgpu: handle multi level PD updates V2 Chunming Zhou
2017-03-27 5:53 ` [PATCH 09/15] drm/amdgpu: handle multi level PD during PT updates Chunming Zhou
2017-03-27 5:53 ` [PATCH 10/15] drm/amdgpu: add alloc/free for multi level PDs V2 Chunming Zhou
2017-03-27 5:53 ` [PATCH 11/15] drm/amdgpu: abstract block size to one function Chunming Zhou
2017-03-27 5:53 ` [PATCH 12/15] drm/amdgpu: limit block size to one page Chunming Zhou
[not found] ` <1490594005-14553-13-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28 3:07 ` Zhang, Jerry (Junwei)
2017-03-27 5:53 ` [PATCH 13/15] drm/amdgpu: adapt vm size for multi vmpt Chunming Zhou
[not found] ` <1490594005-14553-14-git-send-email-David1.Zhou-5C7GfCeVMHo@public.gmane.org>
2017-03-28 3:19 ` Zhang, Jerry (Junwei)
[not found] ` <58D9D656.7090107-5C7GfCeVMHo@public.gmane.org>
2017-03-28 3:43 ` zhoucm1
2017-03-28 8:38 ` Christian König
2017-03-27 5:53 ` [PATCH 14/15] drm/amdgpu: set page table depth by num_level Chunming Zhou
2017-03-27 5:53 ` [PATCH 15/15] drm/amdgpu: enable four level VMPT for gmc9 Chunming Zhou
2017-03-27 9:37 ` [PATCH 00/15] *** Multiple level VMPT enablement *** Christian König
[not found] ` <eef2fbb5-8318-4ec3-c91f-b2cb7f9fee86-5C7GfCeVMHo@public.gmane.org>
2017-03-27 16:05 ` Deucher, Alexander
[not found] ` <BN6PR12MB1652FBDB212BC00E7461DB84F7330-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-03-28 3:21 ` Zhang, Jerry (Junwei)
2017-03-28 20:14 ` Multilevel page tables broken for high addresses Felix Kuehling
[not found] ` <31bd63c4-5ab6-d6f8-8b7c-3411e45c1c57-5C7GfCeVMHo@public.gmane.org>
2017-03-28 20:25 ` Deucher, Alexander
[not found] ` <BN6PR12MB16523E15828BC0C8ED26EF04F7320-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-03-28 20:31 ` Felix Kuehling
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