From: Laxman Dewangan <ldewangan@nvidia.com>
To: Olliver Schinagl <oliver@schinagl.nl>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>
Cc: linux-serial@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org,
Shardar Mohammed <smohammed@nvidia.com>
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
Date: Thu, 30 Mar 2017 15:47:56 +0530 [thread overview]
Message-ID: <58DCDB54.5040005@nvidia.com> (raw)
In-Reply-To: <20170329184806.6577-1-oliver@schinagl.nl>
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
WARNING: multiple messages have this Message-ID (diff)
From: Laxman Dewangan <ldewangan@nvidia.com>
To: Olliver Schinagl <oliver@schinagl.nl>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Jiri Slaby <jslaby@suse.com>,
Stephen Warren <swarren@wwwdotorg.org>,
Thierry Reding <thierry.reding@gmail.com>,
"Alexandre Courbot" <gnurou@gmail.com>
Cc: <linux-serial@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
Shardar Mohammed <smohammed@nvidia.com>
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
Date: Thu, 30 Mar 2017 15:47:56 +0530 [thread overview]
Message-ID: <58DCDB54.5040005@nvidia.com> (raw)
In-Reply-To: <20170329184806.6577-1-oliver@schinagl.nl>
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
next prev parent reply other threads:[~2017-03-30 10:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-29 18:48 [PATCH] serial: tegra: Map the iir register to default defines Olliver Schinagl
2017-03-30 10:17 ` Laxman Dewangan [this message]
2017-03-30 10:17 ` Laxman Dewangan
[not found] ` <58DCDB54.5040005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-03-31 10:07 ` Shardar Mohammed
2017-03-31 10:07 ` Shardar Mohammed
2017-03-31 10:28 ` Jon Hunter
[not found] ` <c904007d-af59-c1fa-d11f-a69c4609ff84-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-03-31 10:42 ` Shardar Mohammed
2017-03-31 10:42 ` Shardar Mohammed
2017-03-31 11:32 ` Olliver Schinagl
2017-03-30 13:42 ` Jon Hunter
2017-03-30 13:42 ` Jon Hunter
2017-03-30 15:37 ` Olliver Schinagl
2017-03-31 13:21 ` Greg Kroah-Hartman
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