* [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default
@ 2017-04-05 6:43 Junwei Zhang
[not found] ` <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 7+ messages in thread
From: Junwei Zhang @ 2017-04-05 6:43 UTC (permalink / raw)
To: alexander.deucher-5C7GfCeVMHo
Cc: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
By default, the value is set by individual gmc.
if a specific value is input, it overrides the global value for all
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++++++++++++++++++------------
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++--
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++--
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++--
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------
7 files changed, 74 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 65021df..d7f75ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);
+uint32_t amdgpu_get_block_size(int vm_size);
+
/*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 1d0c742..2f91c2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg)
return (arg & (arg - 1)) == 0;
}
-static void amdgpu_get_block_size(struct amdgpu_device *adev)
+uint32_t amdgpu_get_block_size(int vm_size)
+{
+ /* Total bits covered by PD + PTs */
+ unsigned bits = ilog2(vm_size) + 18;
+
+ /* Make sure the PD is 4K in size up to 8GB address space.
+ Above that split equal between PD and PTs */
+ if (vm_size <= 8)
+ return (bits - 9);
+ else
+ return ((bits + 3) / 2);
+}
+
+static void amdgpu_check_block_size(struct amdgpu_device *adev)
{
/* defines number of bits in page table versus page directory,
* a page is 4KB so we have 12 bits offset, minimum 9 bits in the
* page table and the remaining bits are in the page directory */
- if (amdgpu_vm_block_size == -1) {
-
- /* Total bits covered by PD + PTs */
- unsigned bits = ilog2(amdgpu_vm_size) + 18;
-
- /* Make sure the PD is 4K in size up to 8GB address space.
- Above that split equal between PD and PTs */
- if (amdgpu_vm_size <= 8)
- amdgpu_vm_block_size = bits - 9;
- else
- amdgpu_vm_block_size = (bits + 3) / 2;
+ if (amdgpu_vm_block_size == -1)
+ return;
- } else if (amdgpu_vm_block_size < 9) {
+ if (amdgpu_vm_block_size < 9) {
dev_warn(adev->dev, "VM page table size (%d) too small\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
if (amdgpu_vm_block_size > 24 ||
(amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
dev_warn(adev->dev, "VM page table size (%d) too large\n",
amdgpu_vm_block_size);
- amdgpu_vm_block_size = 9;
+ goto def_value;
}
+
+ return;
+
+def_value:
+ amdgpu_vm_block_size = -1;
}
static void amdgpu_check_vm_size(struct amdgpu_device *adev)
@@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
return;
def_value:
- amdgpu_vm_size = 8;
- dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size);
+ amdgpu_vm_size = -1;;
}
/**
@@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
amdgpu_check_vm_size(adev);
- amdgpu_get_block_size(adev);
+ amdgpu_check_block_size(adev);
if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
!amdgpu_check_pot_argument(amdgpu_vram_page_split))) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index bfd945b..6238e2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -86,7 +86,7 @@
unsigned amdgpu_ip_block_mask = 0xffffffff;
int amdgpu_bapm = -1;
int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 64;
+int amdgpu_vm_size = -1;
int amdgpu_vm_block_size = -1;
int amdgpu_vm_fault_stop = 0;
int amdgpu_vm_debug = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 30d5c42..f46c52c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle)
if (r)
return r;
- adev->vm_manager.vm_size = amdgpu_vm_size;
- adev->vm_manager.block_size = amdgpu_vm_block_size;
+ if (amdgpu_vm_size == -1) {
+ adev->vm_manager.vm_size = 64;
+ adev->vm_manager.block_size =
+ amdgpu_get_block_size(adev->vm_manager.vm_size);
+ } else {
+ adev->vm_manager.vm_size = amdgpu_vm_size;
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
+ }
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
DRM_INFO("vm size is %d GB, block size is %d-bit\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 7113765..80b31f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- adev->vm_manager.vm_size = amdgpu_vm_size;
- adev->vm_manager.block_size = amdgpu_vm_block_size;
+ if (amdgpu_vm_size == -1) {
+ adev->vm_manager.vm_size = 64;
+ adev->vm_manager.block_size =
+ amdgpu_get_block_size(adev->vm_manager.vm_size);
+ } else {
+ adev->vm_manager.vm_size = amdgpu_vm_size;
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
+ }
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
DRM_INFO("vm size is %d GB, block size is %d-bit\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index b3d1f1b..f1f135a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle)
* Currently set to 4GB ((1 << 20) 4k pages).
* Max GPUVM size for cayman and SI is 40 bits.
*/
- adev->vm_manager.vm_size = amdgpu_vm_size;
- adev->vm_manager.block_size = amdgpu_vm_block_size;
+ if (amdgpu_vm_size == -1) {
+ adev->vm_manager.vm_size = 64;
+ adev->vm_manager.block_size =
+ amdgpu_get_block_size(adev->vm_manager.vm_size);
+ } else {
+ adev->vm_manager.vm_size = amdgpu_vm_size;
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
+ }
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
DRM_INFO("vm size is %d GB, block size is %d-bit\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 0cae7f0..8e12ff3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle)
if (adev->flags & AMD_IS_APU) {
adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
- adev->vm_manager.vm_size = amdgpu_vm_size;
- adev->vm_manager.block_size = amdgpu_vm_block_size;
} else {
/* XXX Don't know how to get VRAM type yet. */
adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM;
- /*
- * To fulfill 4-level page support,
- * vm size is 256TB (48bit), maximum size of Vega10,
- * block size 512 (9bit)
- */
- adev->vm_manager.vm_size = 1U << 18;
- adev->vm_manager.block_size = 9;
}
DRM_INFO("vm size is %d GB, block size is %d-bit\n",
@@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle)
if (r)
return r;
+ if (amdgpu_vm_size == -1) {
+ if (adev->flags & AMD_IS_APU) {
+ adev->vm_manager.vm_size = 64;
+ adev->vm_manager.block_size =
+ amdgpu_get_block_size(adev->vm_manager.vm_size);
+ } else {
+ /*
+ * To fulfill 4-level page support,
+ * vm size is 256TB (48bit), maximum size of Vega10,
+ * block size 512 (9bit)
+ */
+ adev->vm_manager.vm_size = 1U << 18;
+ adev->vm_manager.block_size = 9;
+ }
+ } else {
+ adev->vm_manager.vm_size = amdgpu_vm_size;
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
+ }
+
+ adev->vm_manager.vm_size = amdgpu_vm_size;
+ adev->vm_manager.block_size = amdgpu_vm_block_size;
adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18;
/* Set the internal MC address mask
--
1.9.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread[parent not found: <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> @ 2017-04-05 9:01 ` Christian König [not found] ` <d8712d6a-3a06-456c-68fb-7edc93261c17-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 2017-04-05 13:30 ` Alex Deucher 2017-04-05 15:46 ` William Lewis 2 siblings, 1 reply; 7+ messages in thread From: Christian König @ 2017-04-05 9:01 UTC (permalink / raw) To: Junwei Zhang, alexander.deucher-5C7GfCeVMHo Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW Am 05.04.2017 um 08:43 schrieb Junwei Zhang: > By default, the value is set by individual gmc. > if a specific value is input, it overrides the global value for all > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++++++++++++++++++------------ > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ > 7 files changed, 74 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 65021df..d7f75ce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, > bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); > bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); > > +uint32_t amdgpu_get_block_size(int vm_size); > + > /* > * Registers read & write functions. > */ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 1d0c742..2f91c2f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) > return (arg & (arg - 1)) == 0; > } > > -static void amdgpu_get_block_size(struct amdgpu_device *adev) > +uint32_t amdgpu_get_block_size(int vm_size) > +{ > + /* Total bits covered by PD + PTs */ > + unsigned bits = ilog2(vm_size) + 18; > + > + /* Make sure the PD is 4K in size up to 8GB address space. > + Above that split equal between PD and PTs */ > + if (vm_size <= 8) > + return (bits - 9); > + else > + return ((bits + 3) / 2); > +} Please move that helper into amdgpu_vmc.c. > + > +static void amdgpu_check_block_size(struct amdgpu_device *adev) > { > /* defines number of bits in page table versus page directory, > * a page is 4KB so we have 12 bits offset, minimum 9 bits in the > * page table and the remaining bits are in the page directory */ > - if (amdgpu_vm_block_size == -1) { > - > - /* Total bits covered by PD + PTs */ > - unsigned bits = ilog2(amdgpu_vm_size) + 18; > - > - /* Make sure the PD is 4K in size up to 8GB address space. > - Above that split equal between PD and PTs */ > - if (amdgpu_vm_size <= 8) > - amdgpu_vm_block_size = bits - 9; > - else > - amdgpu_vm_block_size = (bits + 3) / 2; > + if (amdgpu_vm_block_size == -1) > + return; > > - } else if (amdgpu_vm_block_size < 9) { > + if (amdgpu_vm_block_size < 9) { > dev_warn(adev->dev, "VM page table size (%d) too small\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > > if (amdgpu_vm_block_size > 24 || > (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { > dev_warn(adev->dev, "VM page table size (%d) too large\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > + > + return; > + > +def_value: > + amdgpu_vm_block_size = -1; > } > > static void amdgpu_check_vm_size(struct amdgpu_device *adev) > @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) > return; > > def_value: > - amdgpu_vm_size = 8; > - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); > + amdgpu_vm_size = -1;; > } > > /** > @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) > > amdgpu_check_vm_size(adev); > > - amdgpu_get_block_size(adev); > + amdgpu_check_block_size(adev); > > if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || > !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index bfd945b..6238e2e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -86,7 +86,7 @@ > unsigned amdgpu_ip_block_mask = 0xffffffff; > int amdgpu_bapm = -1; > int amdgpu_deep_color = 0; > -int amdgpu_vm_size = 64; > +int amdgpu_vm_size = -1; > int amdgpu_vm_block_size = -1; > int amdgpu_vm_fault_stop = 0; > int amdgpu_vm_debug = 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > index 30d5c42..f46c52c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) > if (r) > return r; > > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index 7113765..80b31f4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } That's a bit to simple. The logic should probably rather be: if (amdgpu_vm_size == -1) adev->vm_manager.vm_size = 64; else adev->vm_manager.vm_size = amdgpu_vm_size; if (amdgpu_vm_block_size == -1) adev->vm_manager.block_size = amdgpu_get_block_size(adev->vm_manager.vm_size); else adev->vm_manager.block_size = amdgpu_vm_block_size; Since the logic is the same for GFX6,7 and 8 we might put that into a helper as well. > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index b3d1f1b..f1f135a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 0cae7f0..8e12ff3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) > > if (adev->flags & AMD_IS_APU) { > adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > } else { > /* XXX Don't know how to get VRAM type yet. */ > adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; > - /* > - * To fulfill 4-level page support, > - * vm size is 256TB (48bit), maximum size of Vega10, > - * block size 512 (9bit) > - */ > - adev->vm_manager.vm_size = 1U << 18; > - adev->vm_manager.block_size = 9; > } > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > + if (amdgpu_vm_size == -1) { > + if (adev->flags & AMD_IS_APU) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + /* > + * To fulfill 4-level page support, > + * vm size is 256TB (48bit), maximum size of Vega10, > + * block size 512 (9bit) > + */ > + adev->vm_manager.vm_size = 1U << 18; > + adev->vm_manager.block_size = 9; > + } > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > + > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; NAK. On GFX9 vm_size and block_size should be hard coded to 256TB and 9. Christian. > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > /* Set the internal MC address mask _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <d8712d6a-3a06-456c-68fb-7edc93261c17-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <d8712d6a-3a06-456c-68fb-7edc93261c17-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2017-04-05 13:32 ` Alex Deucher [not found] ` <CADnq5_OGqExgZ-qN9FJyOAhBsDykweBh5gfn_T1YE0HJDfs8NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 7+ messages in thread From: Alex Deucher @ 2017-04-05 13:32 UTC (permalink / raw) To: Christian König; +Cc: Junwei Zhang, Deucher, Alexander, amd-gfx list On Wed, Apr 5, 2017 at 5:01 AM, Christian König <deathsimple@vodafone.de> wrote: > Am 05.04.2017 um 08:43 schrieb Junwei Zhang: >> >> By default, the value is set by individual gmc. >> if a specific value is input, it overrides the global value for all >> >> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ >> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 >> ++++++++++++++++++------------ >> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- >> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- >> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- >> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- >> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ >> 7 files changed, 74 insertions(+), 34 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> index 65021df..d7f75ce 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, >> uint32_t reg, uint32_t v, >> bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); >> bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); >> +uint32_t amdgpu_get_block_size(int vm_size); >> + >> /* >> * Registers read & write functions. >> */ >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> index 1d0c742..2f91c2f 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) >> return (arg & (arg - 1)) == 0; >> } >> -static void amdgpu_get_block_size(struct amdgpu_device *adev) >> +uint32_t amdgpu_get_block_size(int vm_size) >> +{ >> + /* Total bits covered by PD + PTs */ >> + unsigned bits = ilog2(vm_size) + 18; >> + >> + /* Make sure the PD is 4K in size up to 8GB address space. >> + Above that split equal between PD and PTs */ >> + if (vm_size <= 8) >> + return (bits - 9); >> + else >> + return ((bits + 3) / 2); >> +} > > > Please move that helper into amdgpu_vmc.c. > > >> + >> +static void amdgpu_check_block_size(struct amdgpu_device *adev) >> { >> /* defines number of bits in page table versus page directory, >> * a page is 4KB so we have 12 bits offset, minimum 9 bits in the >> * page table and the remaining bits are in the page directory */ >> - if (amdgpu_vm_block_size == -1) { >> - >> - /* Total bits covered by PD + PTs */ >> - unsigned bits = ilog2(amdgpu_vm_size) + 18; >> - >> - /* Make sure the PD is 4K in size up to 8GB address space. >> - Above that split equal between PD and PTs */ >> - if (amdgpu_vm_size <= 8) >> - amdgpu_vm_block_size = bits - 9; >> - else >> - amdgpu_vm_block_size = (bits + 3) / 2; >> + if (amdgpu_vm_block_size == -1) >> + return; >> - } else if (amdgpu_vm_block_size < 9) { >> + if (amdgpu_vm_block_size < 9) { >> dev_warn(adev->dev, "VM page table size (%d) too small\n", >> amdgpu_vm_block_size); >> - amdgpu_vm_block_size = 9; >> + goto def_value; >> } >> if (amdgpu_vm_block_size > 24 || >> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { >> dev_warn(adev->dev, "VM page table size (%d) too large\n", >> amdgpu_vm_block_size); >> - amdgpu_vm_block_size = 9; >> + goto def_value; >> } >> + >> + return; >> + >> +def_value: >> + amdgpu_vm_block_size = -1; >> } >> static void amdgpu_check_vm_size(struct amdgpu_device *adev) >> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct >> amdgpu_device *adev) >> return; >> def_value: >> - amdgpu_vm_size = 8; >> - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); >> + amdgpu_vm_size = -1;; >> } >> /** >> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct >> amdgpu_device *adev) >> amdgpu_check_vm_size(adev); >> - amdgpu_get_block_size(adev); >> + amdgpu_check_block_size(adev); >> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 >> || >> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >> index bfd945b..6238e2e 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >> @@ -86,7 +86,7 @@ >> unsigned amdgpu_ip_block_mask = 0xffffffff; >> int amdgpu_bapm = -1; >> int amdgpu_deep_color = 0; >> -int amdgpu_vm_size = 64; >> +int amdgpu_vm_size = -1; >> int amdgpu_vm_block_size = -1; >> int amdgpu_vm_fault_stop = 0; >> int amdgpu_vm_debug = 0; >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >> index 30d5c42..f46c52c 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >> @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) >> if (r) >> return r; >> - adev->vm_manager.vm_size = amdgpu_vm_size; >> - adev->vm_manager.block_size = amdgpu_vm_block_size; >> + if (amdgpu_vm_size == -1) { >> + adev->vm_manager.vm_size = 64; >> + adev->vm_manager.block_size = >> + amdgpu_get_block_size(adev->vm_manager.vm_size); >> + } else { >> + adev->vm_manager.vm_size = amdgpu_vm_size; >> + adev->vm_manager.block_size = amdgpu_vm_block_size; >> + } >> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >> index 7113765..80b31f4 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >> @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) >> * Currently set to 4GB ((1 << 20) 4k pages). >> * Max GPUVM size for cayman and SI is 40 bits. >> */ >> - adev->vm_manager.vm_size = amdgpu_vm_size; >> - adev->vm_manager.block_size = amdgpu_vm_block_size; >> + if (amdgpu_vm_size == -1) { >> + adev->vm_manager.vm_size = 64; >> + adev->vm_manager.block_size = >> + amdgpu_get_block_size(adev->vm_manager.vm_size); >> + } else { >> + adev->vm_manager.vm_size = amdgpu_vm_size; >> + adev->vm_manager.block_size = amdgpu_vm_block_size; >> + } > > > That's a bit to simple. The logic should probably rather be: > > if (amdgpu_vm_size == -1) > adev->vm_manager.vm_size = 64; > else > adev->vm_manager.vm_size = amdgpu_vm_size; > > if (amdgpu_vm_block_size == -1) > adev->vm_manager.block_size = > amdgpu_get_block_size(adev->vm_manager.vm_size); > else > adev->vm_manager.block_size = amdgpu_vm_block_size; > > > Since the logic is the same for GFX6,7 and 8 we might put that into a helper > as well. > > >> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >> index b3d1f1b..f1f135a 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >> @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) >> * Currently set to 4GB ((1 << 20) 4k pages). >> * Max GPUVM size for cayman and SI is 40 bits. >> */ >> - adev->vm_manager.vm_size = amdgpu_vm_size; >> - adev->vm_manager.block_size = amdgpu_vm_block_size; >> + if (amdgpu_vm_size == -1) { >> + adev->vm_manager.vm_size = 64; >> + adev->vm_manager.block_size = >> + amdgpu_get_block_size(adev->vm_manager.vm_size); >> + } else { >> + adev->vm_manager.vm_size = amdgpu_vm_size; >> + adev->vm_manager.block_size = amdgpu_vm_block_size; >> + } >> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> index 0cae7f0..8e12ff3 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) >> if (adev->flags & AMD_IS_APU) { >> adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; >> - adev->vm_manager.vm_size = amdgpu_vm_size; >> - adev->vm_manager.block_size = amdgpu_vm_block_size; >> } else { >> /* XXX Don't know how to get VRAM type yet. */ >> adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; >> - /* >> - * To fulfill 4-level page support, >> - * vm size is 256TB (48bit), maximum size of Vega10, >> - * block size 512 (9bit) >> - */ >> - adev->vm_manager.vm_size = 1U << 18; >> - adev->vm_manager.block_size = 9; >> } >> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >> @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) >> if (r) >> return r; >> + if (amdgpu_vm_size == -1) { >> + if (adev->flags & AMD_IS_APU) { >> + adev->vm_manager.vm_size = 64; >> + adev->vm_manager.block_size = >> + >> amdgpu_get_block_size(adev->vm_manager.vm_size); >> + } else { >> + /* >> + * To fulfill 4-level page support, >> + * vm size is 256TB (48bit), maximum size of >> Vega10, >> + * block size 512 (9bit) >> + */ >> + adev->vm_manager.vm_size = 1U << 18; >> + adev->vm_manager.block_size = 9; >> + } >> + } else { >> + adev->vm_manager.vm_size = amdgpu_vm_size; >> + adev->vm_manager.block_size = amdgpu_vm_block_size; >> + } >> + >> + adev->vm_manager.vm_size = amdgpu_vm_size; >> + adev->vm_manager.block_size = amdgpu_vm_block_size; > > > NAK. On GFX9 vm_size and block_size should be hard coded to 256TB and 9. I think there is still value in being able to override for testing/debugging. Alex > > Christian. > >> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >> /* Set the internal MC address mask > > > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <CADnq5_OGqExgZ-qN9FJyOAhBsDykweBh5gfn_T1YE0HJDfs8NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <CADnq5_OGqExgZ-qN9FJyOAhBsDykweBh5gfn_T1YE0HJDfs8NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2017-04-05 13:39 ` Christian König [not found] ` <c77cf2d4-6509-fb9b-0cc1-ff01224ad5bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> 0 siblings, 1 reply; 7+ messages in thread From: Christian König @ 2017-04-05 13:39 UTC (permalink / raw) To: Alex Deucher; +Cc: Junwei Zhang, Deucher, Alexander, amd-gfx list Am 05.04.2017 um 15:32 schrieb Alex Deucher: > On Wed, Apr 5, 2017 at 5:01 AM, Christian König <deathsimple@vodafone.de> wrote: >> Am 05.04.2017 um 08:43 schrieb Junwei Zhang: >>> By default, the value is set by individual gmc. >>> if a specific value is input, it overrides the global value for all >>> >>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 >>> ++++++++++++++++++------------ >>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- >>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- >>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- >>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- >>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ >>> 7 files changed, 74 insertions(+), 34 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> index 65021df..d7f75ce 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, >>> uint32_t reg, uint32_t v, >>> bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); >>> bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); >>> +uint32_t amdgpu_get_block_size(int vm_size); >>> + >>> /* >>> * Registers read & write functions. >>> */ >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> index 1d0c742..2f91c2f 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) >>> return (arg & (arg - 1)) == 0; >>> } >>> -static void amdgpu_get_block_size(struct amdgpu_device *adev) >>> +uint32_t amdgpu_get_block_size(int vm_size) >>> +{ >>> + /* Total bits covered by PD + PTs */ >>> + unsigned bits = ilog2(vm_size) + 18; >>> + >>> + /* Make sure the PD is 4K in size up to 8GB address space. >>> + Above that split equal between PD and PTs */ >>> + if (vm_size <= 8) >>> + return (bits - 9); >>> + else >>> + return ((bits + 3) / 2); >>> +} >> >> Please move that helper into amdgpu_vmc.c. >> >> >>> + >>> +static void amdgpu_check_block_size(struct amdgpu_device *adev) >>> { >>> /* defines number of bits in page table versus page directory, >>> * a page is 4KB so we have 12 bits offset, minimum 9 bits in the >>> * page table and the remaining bits are in the page directory */ >>> - if (amdgpu_vm_block_size == -1) { >>> - >>> - /* Total bits covered by PD + PTs */ >>> - unsigned bits = ilog2(amdgpu_vm_size) + 18; >>> - >>> - /* Make sure the PD is 4K in size up to 8GB address space. >>> - Above that split equal between PD and PTs */ >>> - if (amdgpu_vm_size <= 8) >>> - amdgpu_vm_block_size = bits - 9; >>> - else >>> - amdgpu_vm_block_size = (bits + 3) / 2; >>> + if (amdgpu_vm_block_size == -1) >>> + return; >>> - } else if (amdgpu_vm_block_size < 9) { >>> + if (amdgpu_vm_block_size < 9) { >>> dev_warn(adev->dev, "VM page table size (%d) too small\n", >>> amdgpu_vm_block_size); >>> - amdgpu_vm_block_size = 9; >>> + goto def_value; >>> } >>> if (amdgpu_vm_block_size > 24 || >>> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { >>> dev_warn(adev->dev, "VM page table size (%d) too large\n", >>> amdgpu_vm_block_size); >>> - amdgpu_vm_block_size = 9; >>> + goto def_value; >>> } >>> + >>> + return; >>> + >>> +def_value: >>> + amdgpu_vm_block_size = -1; >>> } >>> static void amdgpu_check_vm_size(struct amdgpu_device *adev) >>> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct >>> amdgpu_device *adev) >>> return; >>> def_value: >>> - amdgpu_vm_size = 8; >>> - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); >>> + amdgpu_vm_size = -1;; >>> } >>> /** >>> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct >>> amdgpu_device *adev) >>> amdgpu_check_vm_size(adev); >>> - amdgpu_get_block_size(adev); >>> + amdgpu_check_block_size(adev); >>> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 >>> || >>> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> index bfd945b..6238e2e 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>> @@ -86,7 +86,7 @@ >>> unsigned amdgpu_ip_block_mask = 0xffffffff; >>> int amdgpu_bapm = -1; >>> int amdgpu_deep_color = 0; >>> -int amdgpu_vm_size = 64; >>> +int amdgpu_vm_size = -1; >>> int amdgpu_vm_block_size = -1; >>> int amdgpu_vm_fault_stop = 0; >>> int amdgpu_vm_debug = 0; >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> index 30d5c42..f46c52c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) >>> if (r) >>> return r; >>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + if (amdgpu_vm_size == -1) { >>> + adev->vm_manager.vm_size = 64; >>> + adev->vm_manager.block_size = >>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>> + } else { >>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + } >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> index 7113765..80b31f4 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) >>> * Currently set to 4GB ((1 << 20) 4k pages). >>> * Max GPUVM size for cayman and SI is 40 bits. >>> */ >>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + if (amdgpu_vm_size == -1) { >>> + adev->vm_manager.vm_size = 64; >>> + adev->vm_manager.block_size = >>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>> + } else { >>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + } >> >> That's a bit to simple. The logic should probably rather be: >> >> if (amdgpu_vm_size == -1) >> adev->vm_manager.vm_size = 64; >> else >> adev->vm_manager.vm_size = amdgpu_vm_size; >> >> if (amdgpu_vm_block_size == -1) >> adev->vm_manager.block_size = >> amdgpu_get_block_size(adev->vm_manager.vm_size); >> else >> adev->vm_manager.block_size = amdgpu_vm_block_size; >> >> >> Since the logic is the same for GFX6,7 and 8 we might put that into a helper >> as well. >> >> >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> index b3d1f1b..f1f135a 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) >>> * Currently set to 4GB ((1 << 20) 4k pages). >>> * Max GPUVM size for cayman and SI is 40 bits. >>> */ >>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + if (amdgpu_vm_size == -1) { >>> + adev->vm_manager.vm_size = 64; >>> + adev->vm_manager.block_size = >>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>> + } else { >>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + } >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> index 0cae7f0..8e12ff3 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) >>> if (adev->flags & AMD_IS_APU) { >>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; >>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>> } else { >>> /* XXX Don't know how to get VRAM type yet. */ >>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; >>> - /* >>> - * To fulfill 4-level page support, >>> - * vm size is 256TB (48bit), maximum size of Vega10, >>> - * block size 512 (9bit) >>> - */ >>> - adev->vm_manager.vm_size = 1U << 18; >>> - adev->vm_manager.block_size = 9; >>> } >>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>> @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) >>> if (r) >>> return r; >>> + if (amdgpu_vm_size == -1) { >>> + if (adev->flags & AMD_IS_APU) { >>> + adev->vm_manager.vm_size = 64; >>> + adev->vm_manager.block_size = >>> + >>> amdgpu_get_block_size(adev->vm_manager.vm_size); >>> + } else { >>> + /* >>> + * To fulfill 4-level page support, >>> + * vm size is 256TB (48bit), maximum size of >>> Vega10, >>> + * block size 512 (9bit) >>> + */ >>> + adev->vm_manager.vm_size = 1U << 18; >>> + adev->vm_manager.block_size = 9; >>> + } >>> + } else { >>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>> + } >>> + >>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >> >> NAK. On GFX9 vm_size and block_size should be hard coded to 256TB and 9. > I think there is still value in being able to override for testing/debugging. The problem is that this won't work. When you want to override the size you need to work with 1 level page tables again. We could of course try to determine how many levels we want from the VM size/block size, but I don't really want to test all those options all the time. Christian. > > Alex > >> Christian. >> >>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>> /* Set the internal MC address mask >> >> >> _______________________________________________ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
[parent not found: <c77cf2d4-6509-fb9b-0cc1-ff01224ad5bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>]
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <c77cf2d4-6509-fb9b-0cc1-ff01224ad5bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org> @ 2017-04-06 10:01 ` Zhang, Jerry (Junwei) 0 siblings, 0 replies; 7+ messages in thread From: Zhang, Jerry (Junwei) @ 2017-04-06 10:01 UTC (permalink / raw) To: Christian König, Alex Deucher; +Cc: Deucher, Alexander, amd-gfx list Thanks you all for the comments Updated the v2, please help review On 04/05/2017 09:39 PM, Christian König wrote: > Am 05.04.2017 um 15:32 schrieb Alex Deucher: >> On Wed, Apr 5, 2017 at 5:01 AM, Christian König <deathsimple@vodafone.de> wrote: >>> Am 05.04.2017 um 08:43 schrieb Junwei Zhang: >>>> By default, the value is set by individual gmc. >>>> if a specific value is input, it overrides the global value for all >>>> >>>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> >>>> --- >>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 >>>> ++++++++++++++++++------------ >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- >>>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- >>>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- >>>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- >>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ >>>> 7 files changed, 74 insertions(+), 34 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>> index 65021df..d7f75ce 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>> @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, >>>> uint32_t reg, uint32_t v, >>>> bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); >>>> bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); >>>> +uint32_t amdgpu_get_block_size(int vm_size); >>>> + >>>> /* >>>> * Registers read & write functions. >>>> */ >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>> index 1d0c742..2f91c2f 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c >>>> @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) >>>> return (arg & (arg - 1)) == 0; >>>> } >>>> -static void amdgpu_get_block_size(struct amdgpu_device *adev) >>>> +uint32_t amdgpu_get_block_size(int vm_size) >>>> +{ >>>> + /* Total bits covered by PD + PTs */ >>>> + unsigned bits = ilog2(vm_size) + 18; >>>> + >>>> + /* Make sure the PD is 4K in size up to 8GB address space. >>>> + Above that split equal between PD and PTs */ >>>> + if (vm_size <= 8) >>>> + return (bits - 9); >>>> + else >>>> + return ((bits + 3) / 2); >>>> +} >>> >>> Please move that helper into amdgpu_vmc.c. >>> >>> >>>> + >>>> +static void amdgpu_check_block_size(struct amdgpu_device *adev) >>>> { >>>> /* defines number of bits in page table versus page directory, >>>> * a page is 4KB so we have 12 bits offset, minimum 9 bits in the >>>> * page table and the remaining bits are in the page directory */ >>>> - if (amdgpu_vm_block_size == -1) { >>>> - >>>> - /* Total bits covered by PD + PTs */ >>>> - unsigned bits = ilog2(amdgpu_vm_size) + 18; >>>> - >>>> - /* Make sure the PD is 4K in size up to 8GB address space. >>>> - Above that split equal between PD and PTs */ >>>> - if (amdgpu_vm_size <= 8) >>>> - amdgpu_vm_block_size = bits - 9; >>>> - else >>>> - amdgpu_vm_block_size = (bits + 3) / 2; >>>> + if (amdgpu_vm_block_size == -1) >>>> + return; >>>> - } else if (amdgpu_vm_block_size < 9) { >>>> + if (amdgpu_vm_block_size < 9) { >>>> dev_warn(adev->dev, "VM page table size (%d) too small\n", >>>> amdgpu_vm_block_size); >>>> - amdgpu_vm_block_size = 9; >>>> + goto def_value; >>>> } >>>> if (amdgpu_vm_block_size > 24 || >>>> (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { >>>> dev_warn(adev->dev, "VM page table size (%d) too large\n", >>>> amdgpu_vm_block_size); >>>> - amdgpu_vm_block_size = 9; >>>> + goto def_value; >>>> } >>>> + >>>> + return; >>>> + >>>> +def_value: >>>> + amdgpu_vm_block_size = -1; >>>> } >>>> static void amdgpu_check_vm_size(struct amdgpu_device *adev) >>>> @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct >>>> amdgpu_device *adev) >>>> return; >>>> def_value: >>>> - amdgpu_vm_size = 8; >>>> - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); >>>> + amdgpu_vm_size = -1;; >>>> } >>>> /** >>>> @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct >>>> amdgpu_device *adev) >>>> amdgpu_check_vm_size(adev); >>>> - amdgpu_get_block_size(adev); >>>> + amdgpu_check_block_size(adev); >>>> if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 >>>> || >>>> !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>>> index bfd945b..6238e2e 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c >>>> @@ -86,7 +86,7 @@ >>>> unsigned amdgpu_ip_block_mask = 0xffffffff; >>>> int amdgpu_bapm = -1; >>>> int amdgpu_deep_color = 0; >>>> -int amdgpu_vm_size = 64; >>>> +int amdgpu_vm_size = -1; >>>> int amdgpu_vm_block_size = -1; >>>> int amdgpu_vm_fault_stop = 0; >>>> int amdgpu_vm_debug = 0; >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>>> index 30d5c42..f46c52c 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>>> @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) >>>> if (r) >>>> return r; >>>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + if (amdgpu_vm_size == -1) { >>>> + adev->vm_manager.vm_size = 64; >>>> + adev->vm_manager.block_size = >>>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>>> + } else { >>>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + } >>>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>>> index 7113765..80b31f4 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>>> @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) >>>> * Currently set to 4GB ((1 << 20) 4k pages). >>>> * Max GPUVM size for cayman and SI is 40 bits. >>>> */ >>>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + if (amdgpu_vm_size == -1) { >>>> + adev->vm_manager.vm_size = 64; >>>> + adev->vm_manager.block_size = >>>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>>> + } else { >>>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + } >>> >>> That's a bit to simple. The logic should probably rather be: >>> >>> if (amdgpu_vm_size == -1) >>> adev->vm_manager.vm_size = 64; >>> else >>> adev->vm_manager.vm_size = amdgpu_vm_size; >>> >>> if (amdgpu_vm_block_size == -1) >>> adev->vm_manager.block_size = >>> amdgpu_get_block_size(adev->vm_manager.vm_size); >>> else >>> adev->vm_manager.block_size = amdgpu_vm_block_size; >>> >>> >>> Since the logic is the same for GFX6,7 and 8 we might put that into a helper >>> as well. >>> >>> >>>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>>> index b3d1f1b..f1f135a 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>>> @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) >>>> * Currently set to 4GB ((1 << 20) 4k pages). >>>> * Max GPUVM size for cayman and SI is 40 bits. >>>> */ >>>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + if (amdgpu_vm_size == -1) { >>>> + adev->vm_manager.vm_size = 64; >>>> + adev->vm_manager.block_size = >>>> + amdgpu_get_block_size(adev->vm_manager.vm_size); >>>> + } else { >>>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + } >>>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> index 0cae7f0..8e12ff3 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) >>>> if (adev->flags & AMD_IS_APU) { >>>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; >>>> - adev->vm_manager.vm_size = amdgpu_vm_size; >>>> - adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> } else { >>>> /* XXX Don't know how to get VRAM type yet. */ >>>> adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; >>>> - /* >>>> - * To fulfill 4-level page support, >>>> - * vm size is 256TB (48bit), maximum size of Vega10, >>>> - * block size 512 (9bit) >>>> - */ >>>> - adev->vm_manager.vm_size = 1U << 18; >>>> - adev->vm_manager.block_size = 9; >>>> } >>>> DRM_INFO("vm size is %d GB, block size is %d-bit\n", >>>> @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) >>>> if (r) >>>> return r; >>>> + if (amdgpu_vm_size == -1) { >>>> + if (adev->flags & AMD_IS_APU) { >>>> + adev->vm_manager.vm_size = 64; >>>> + adev->vm_manager.block_size = >>>> + >>>> amdgpu_get_block_size(adev->vm_manager.vm_size); >>>> + } else { >>>> + /* >>>> + * To fulfill 4-level page support, >>>> + * vm size is 256TB (48bit), maximum size of >>>> Vega10, >>>> + * block size 512 (9bit) >>>> + */ >>>> + adev->vm_manager.vm_size = 1U << 18; >>>> + adev->vm_manager.block_size = 9; >>>> + } >>>> + } else { >>>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>>> + } >>>> + >>>> + adev->vm_manager.vm_size = amdgpu_vm_size; >>>> + adev->vm_manager.block_size = amdgpu_vm_block_size; >>> >>> NAK. On GFX9 vm_size and block_size should be hard coded to 256TB and 9. >> I think there is still value in being able to override for testing/debugging. > > The problem is that this won't work. When you want to override the size you > need to work with 1 level page tables again. > > We could of course try to determine how many levels we want from the VM > size/block size, but I don't really want to test all those options all the time. > > Christian. > >> >> Alex >> >>> Christian. >>> >>>> adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; >>>> /* Set the internal MC address mask >>> >>> >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 2017-04-05 9:01 ` Christian König @ 2017-04-05 13:30 ` Alex Deucher 2017-04-05 15:46 ` William Lewis 2 siblings, 0 replies; 7+ messages in thread From: Alex Deucher @ 2017-04-05 13:30 UTC (permalink / raw) To: Junwei Zhang; +Cc: Deucher, Alexander, amd-gfx list On Wed, Apr 5, 2017 at 2:43 AM, Junwei Zhang <Jerry.Zhang@amd.com> wrote: > By default, the value is set by individual gmc. > if a specific value is input, it overrides the global value for all > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++++++++++++++++++------------ > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ > 7 files changed, 74 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 65021df..d7f75ce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, > bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); > bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); > > +uint32_t amdgpu_get_block_size(int vm_size); > + > /* > * Registers read & write functions. > */ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 1d0c742..2f91c2f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) > return (arg & (arg - 1)) == 0; > } > > -static void amdgpu_get_block_size(struct amdgpu_device *adev) > +uint32_t amdgpu_get_block_size(int vm_size) > +{ > + /* Total bits covered by PD + PTs */ > + unsigned bits = ilog2(vm_size) + 18; > + > + /* Make sure the PD is 4K in size up to 8GB address space. > + Above that split equal between PD and PTs */ > + if (vm_size <= 8) > + return (bits - 9); > + else > + return ((bits + 3) / 2); > +} > + > +static void amdgpu_check_block_size(struct amdgpu_device *adev) > { > /* defines number of bits in page table versus page directory, > * a page is 4KB so we have 12 bits offset, minimum 9 bits in the > * page table and the remaining bits are in the page directory */ > - if (amdgpu_vm_block_size == -1) { > - > - /* Total bits covered by PD + PTs */ > - unsigned bits = ilog2(amdgpu_vm_size) + 18; > - > - /* Make sure the PD is 4K in size up to 8GB address space. > - Above that split equal between PD and PTs */ > - if (amdgpu_vm_size <= 8) > - amdgpu_vm_block_size = bits - 9; > - else > - amdgpu_vm_block_size = (bits + 3) / 2; > + if (amdgpu_vm_block_size == -1) > + return; > > - } else if (amdgpu_vm_block_size < 9) { > + if (amdgpu_vm_block_size < 9) { > dev_warn(adev->dev, "VM page table size (%d) too small\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > > if (amdgpu_vm_block_size > 24 || > (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { > dev_warn(adev->dev, "VM page table size (%d) too large\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > + > + return; > + > +def_value: > + amdgpu_vm_block_size = -1; > } > > static void amdgpu_check_vm_size(struct amdgpu_device *adev) > @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) > return; > > def_value: > - amdgpu_vm_size = 8; > - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); > + amdgpu_vm_size = -1;; > } > > /** > @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) > > amdgpu_check_vm_size(adev); > > - amdgpu_get_block_size(adev); > + amdgpu_check_block_size(adev); > > if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || > !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index bfd945b..6238e2e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -86,7 +86,7 @@ > unsigned amdgpu_ip_block_mask = 0xffffffff; > int amdgpu_bapm = -1; > int amdgpu_deep_color = 0; > -int amdgpu_vm_size = 64; > +int amdgpu_vm_size = -1; > int amdgpu_vm_block_size = -1; > int amdgpu_vm_fault_stop = 0; > int amdgpu_vm_debug = 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > index 30d5c42..f46c52c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) > if (r) > return r; > > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index 7113765..80b31f4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index b3d1f1b..f1f135a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 0cae7f0..8e12ff3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) > > if (adev->flags & AMD_IS_APU) { > adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > } else { > /* XXX Don't know how to get VRAM type yet. */ > adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; > - /* > - * To fulfill 4-level page support, > - * vm size is 256TB (48bit), maximum size of Vega10, > - * block size 512 (9bit) > - */ > - adev->vm_manager.vm_size = 1U << 18; > - adev->vm_manager.block_size = 9; > } > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > + if (amdgpu_vm_size == -1) { > + if (adev->flags & AMD_IS_APU) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + /* > + * To fulfill 4-level page support, > + * vm size is 256TB (48bit), maximum size of Vega10, > + * block size 512 (9bit) > + */ > + adev->vm_manager.vm_size = 1U << 18; > + adev->vm_manager.block_size = 9; > + } > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > + > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; I think you forgot the drop the lines above. Otherwise, you'll just overwrite what you just set. Alex > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > /* Set the internal MC address mask > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default [not found] ` <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org> 2017-04-05 9:01 ` Christian König 2017-04-05 13:30 ` Alex Deucher @ 2017-04-05 15:46 ` William Lewis 2 siblings, 0 replies; 7+ messages in thread From: William Lewis @ 2017-04-05 15:46 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org On 04/05/2017 01:43 AM, Junwei Zhang wrote: > By default, the value is set by individual gmc. > if a specific value is input, it overrides the global value for all > > Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 44 ++++++++++++++++++------------ > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- > drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 10 +++++-- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 ++++++++++++++------ > 7 files changed, 74 insertions(+), 34 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > index 65021df..d7f75ce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h > @@ -1647,6 +1647,8 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, > bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); > bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); > > +uint32_t amdgpu_get_block_size(int vm_size); > + > /* > * Registers read & write functions. > */ > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 1d0c742..2f91c2f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -1039,35 +1039,44 @@ static bool amdgpu_check_pot_argument(int arg) > return (arg & (arg - 1)) == 0; > } > > -static void amdgpu_get_block_size(struct amdgpu_device *adev) > +uint32_t amdgpu_get_block_size(int vm_size) > +{ > + /* Total bits covered by PD + PTs */ > + unsigned bits = ilog2(vm_size) + 18; > + > + /* Make sure the PD is 4K in size up to 8GB address space. > + Above that split equal between PD and PTs */ > + if (vm_size <= 8) > + return (bits - 9); > + else > + return ((bits + 3) / 2); > +} > + > +static void amdgpu_check_block_size(struct amdgpu_device *adev) > { > /* defines number of bits in page table versus page directory, > * a page is 4KB so we have 12 bits offset, minimum 9 bits in the > * page table and the remaining bits are in the page directory */ > - if (amdgpu_vm_block_size == -1) { > - > - /* Total bits covered by PD + PTs */ > - unsigned bits = ilog2(amdgpu_vm_size) + 18; > - > - /* Make sure the PD is 4K in size up to 8GB address space. > - Above that split equal between PD and PTs */ > - if (amdgpu_vm_size <= 8) > - amdgpu_vm_block_size = bits - 9; > - else > - amdgpu_vm_block_size = (bits + 3) / 2; > + if (amdgpu_vm_block_size == -1) > + return; > > - } else if (amdgpu_vm_block_size < 9) { > + if (amdgpu_vm_block_size < 9) { > dev_warn(adev->dev, "VM page table size (%d) too small\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > > if (amdgpu_vm_block_size > 24 || > (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) { > dev_warn(adev->dev, "VM page table size (%d) too large\n", > amdgpu_vm_block_size); > - amdgpu_vm_block_size = 9; > + goto def_value; > } > + > + return; > + > +def_value: > + amdgpu_vm_block_size = -1; > } > > static void amdgpu_check_vm_size(struct amdgpu_device *adev) > @@ -1096,8 +1105,7 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev) > return; > > def_value: > - amdgpu_vm_size = 8; > - dev_info(adev->dev, "set default VM size %dGB\n", amdgpu_vm_size); > + amdgpu_vm_size = -1;; There's an extraneous semicolon here. > } > > /** > @@ -1131,7 +1139,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev) > > amdgpu_check_vm_size(adev); > > - amdgpu_get_block_size(adev); > + amdgpu_check_block_size(adev); > > if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 || > !amdgpu_check_pot_argument(amdgpu_vram_page_split))) { > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index bfd945b..6238e2e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -86,7 +86,7 @@ > unsigned amdgpu_ip_block_mask = 0xffffffff; > int amdgpu_bapm = -1; > int amdgpu_deep_color = 0; > -int amdgpu_vm_size = 64; > +int amdgpu_vm_size = -1; > int amdgpu_vm_block_size = -1; > int amdgpu_vm_fault_stop = 0; > int amdgpu_vm_debug = 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > index 30d5c42..f46c52c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c > @@ -849,8 +849,14 @@ static int gmc_v6_0_sw_init(void *handle) > if (r) > return r; > > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > index 7113765..80b31f4 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c > @@ -1003,8 +1003,14 @@ static int gmc_v7_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > index b3d1f1b..f1f135a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c > @@ -1087,8 +1087,14 @@ static int gmc_v8_0_sw_init(void *handle) > * Currently set to 4GB ((1 << 20) 4k pages). > * Max GPUVM size for cayman and SI is 40 bits. > */ > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > + if (amdgpu_vm_size == -1) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 0cae7f0..8e12ff3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -532,18 +532,9 @@ static int gmc_v9_0_sw_init(void *handle) > > if (adev->flags & AMD_IS_APU) { > adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; > - adev->vm_manager.vm_size = amdgpu_vm_size; > - adev->vm_manager.block_size = amdgpu_vm_block_size; > } else { > /* XXX Don't know how to get VRAM type yet. */ > adev->mc.vram_type = AMDGPU_VRAM_TYPE_HBM; > - /* > - * To fulfill 4-level page support, > - * vm size is 256TB (48bit), maximum size of Vega10, > - * block size 512 (9bit) > - */ > - adev->vm_manager.vm_size = 1U << 18; > - adev->vm_manager.block_size = 9; > } > > DRM_INFO("vm size is %d GB, block size is %d-bit\n", > @@ -558,6 +549,27 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > + if (amdgpu_vm_size == -1) { > + if (adev->flags & AMD_IS_APU) { > + adev->vm_manager.vm_size = 64; > + adev->vm_manager.block_size = > + amdgpu_get_block_size(adev->vm_manager.vm_size); > + } else { > + /* > + * To fulfill 4-level page support, > + * vm size is 256TB (48bit), maximum size of Vega10, > + * block size 512 (9bit) > + */ > + adev->vm_manager.vm_size = 1U << 18; > + adev->vm_manager.block_size = 9; > + } > + } else { > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > + } > + > + adev->vm_manager.vm_size = amdgpu_vm_size; > + adev->vm_manager.block_size = amdgpu_vm_block_size; > adev->vm_manager.max_pfn = adev->vm_manager.vm_size << 18; > > /* Set the internal MC address mask _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-04-06 10:01 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2017-04-05 6:43 [PATCH] drm/amdgpu: set vm size and block size by individual gmc by default Junwei Zhang
[not found] ` <1491374607-10475-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2017-04-05 9:01 ` Christian König
[not found] ` <d8712d6a-3a06-456c-68fb-7edc93261c17-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-05 13:32 ` Alex Deucher
[not found] ` <CADnq5_OGqExgZ-qN9FJyOAhBsDykweBh5gfn_T1YE0HJDfs8NA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-04-05 13:39 ` Christian König
[not found] ` <c77cf2d4-6509-fb9b-0cc1-ff01224ad5bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-06 10:01 ` Zhang, Jerry (Junwei)
2017-04-05 13:30 ` Alex Deucher
2017-04-05 15:46 ` William Lewis
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