From: James Morse <james.morse@arm.com>
To: gengdongjiu <gengdj.1984@gmail.com>
Cc: Punit Agrawal <punit.agrawal@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Tyler Baicar <tbaicar@codeaurora.org>,
gengdongjiu <gengdongjiu@huawei.com>,
wuquanming@huawei.com, linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH] KVM: arm/arm64: Signal SIGBUS when stage2 discovers hwpoison memory
Date: Fri, 07 Apr 2017 17:12:32 +0100 [thread overview]
Message-ID: <58E7BA70.4040004@arm.com> (raw)
In-Reply-To: <CAMj-D2AKzp-J97ZZGYdtgMvUR7o=sDw5n-Ygy7amvRk6k1p9aQ@mail.gmail.com>
Hi gengdongjiu,
On 06/04/17 16:06, gengdongjiu wrote:
> Below is my previous idea:
> When signalling Qemu, Qemu generate GHES ,then Qemu/kvmtool inject
> the SEA/SEI to guest OS. For different reason, Qemu/.KVMtool injects
> diferent notification type. if inject SEA/SEI/IRQ, guest OS handle the
> guest SEA/SEI/IRQ. handling guest OS SEA/SEI and IRQ guest OS software
> logical is different.
> for example, guest OS call API "ghes_notify_sea" when happening SEA;
> call API "ghes_notify_sei" when happening SEI.
Sounds reasonable. Qemu shouldn't have to care what the guest OS is so the
injecting notifications should stick to KVM APIs.
> so what is your suggested way to notify guest OS after Qemu generating the CPER?
[...]
> so for the notification guest OS, I think Qemu uses IOCTL to let KVM
> inject error may be better.
I agree.
Synchronous External Abort is something that can always be delivered, Qemu can
make it look like SEA was taken on a vcpu by modifying the registers using KVM's
KVM_SET_ONE_REG ioctl(). The pseudo code for what is required is in the
ARM-ARM's 'AArch64.TakeException'.
SError Interrupt is more complicated as it can be masked. Fortunately the
architecture has a way to inject SError into a guest using HCR_EL2.VSE, I think
KVM should allow users-space to inject SError with this. Marc and Christoffer
will have the best idea about how such an API should work. To be useful for
injecting SEI we need to be able to set VSESR_EL2 along with the HCR_EL2.VSE bit.
KVM will need to know about the RAS extensions to save/restore some of the new
registers listed in A1.7.5 of the new ARM-ARM.
Thanks,
James
WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] KVM: arm/arm64: Signal SIGBUS when stage2 discovers hwpoison memory
Date: Fri, 07 Apr 2017 17:12:32 +0100 [thread overview]
Message-ID: <58E7BA70.4040004@arm.com> (raw)
In-Reply-To: <CAMj-D2AKzp-J97ZZGYdtgMvUR7o=sDw5n-Ygy7amvRk6k1p9aQ@mail.gmail.com>
Hi gengdongjiu,
On 06/04/17 16:06, gengdongjiu wrote:
> Below is my previous idea:
> When signalling Qemu, Qemu generate GHES ,then Qemu/kvmtool inject
> the SEA/SEI to guest OS. For different reason, Qemu/.KVMtool injects
> diferent notification type. if inject SEA/SEI/IRQ, guest OS handle the
> guest SEA/SEI/IRQ. handling guest OS SEA/SEI and IRQ guest OS software
> logical is different.
> for example, guest OS call API "ghes_notify_sea" when happening SEA;
> call API "ghes_notify_sei" when happening SEI.
Sounds reasonable. Qemu shouldn't have to care what the guest OS is so the
injecting notifications should stick to KVM APIs.
> so what is your suggested way to notify guest OS after Qemu generating the CPER?
[...]
> so for the notification guest OS, I think Qemu uses IOCTL to let KVM
> inject error may be better.
I agree.
Synchronous External Abort is something that can always be delivered, Qemu can
make it look like SEA was taken on a vcpu by modifying the registers using KVM's
KVM_SET_ONE_REG ioctl(). The pseudo code for what is required is in the
ARM-ARM's 'AArch64.TakeException'.
SError Interrupt is more complicated as it can be masked. Fortunately the
architecture has a way to inject SError into a guest using HCR_EL2.VSE, I think
KVM should allow users-space to inject SError with this. Marc and Christoffer
will have the best idea about how such an API should work. To be useful for
injecting SEI we need to be able to set VSESR_EL2 along with the HCR_EL2.VSE bit.
KVM will need to know about the RAS extensions to save/restore some of the new
registers listed in A1.7.5 of the new ARM-ARM.
Thanks,
James
next prev parent reply other threads:[~2017-04-07 16:10 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-15 16:07 [PATCH] KVM: arm/arm64: Signal SIGBUS when stage2 discovers hwpoison memory James Morse
2017-03-15 16:07 ` James Morse
2017-03-17 15:06 ` Punit Agrawal
2017-03-17 15:06 ` Punit Agrawal
2017-03-17 15:48 ` James Morse
2017-03-17 15:48 ` James Morse
2017-03-24 18:30 ` Christoffer Dall
2017-03-24 18:30 ` Christoffer Dall
2017-03-27 11:20 ` Punit Agrawal
2017-03-27 11:20 ` Punit Agrawal
2017-03-27 12:00 ` James Morse
2017-03-27 12:00 ` James Morse
2017-03-27 12:44 ` Christoffer Dall
2017-03-27 12:44 ` Christoffer Dall
2017-03-27 13:31 ` Punit Agrawal
2017-03-27 13:31 ` Punit Agrawal
2017-03-27 13:38 ` Marc Zyngier
2017-03-27 13:38 ` Marc Zyngier
2017-03-27 14:04 ` Punit Agrawal
2017-03-27 14:04 ` Punit Agrawal
2017-03-27 14:47 ` Christoffer Dall
2017-03-27 14:47 ` Christoffer Dall
2017-03-28 14:50 ` Punit Agrawal
2017-03-28 14:50 ` Punit Agrawal
2017-03-28 15:12 ` Christoffer Dall
2017-03-28 15:12 ` Christoffer Dall
2017-04-04 23:05 ` gengdongjiu
2017-04-04 23:05 ` gengdongjiu
2017-04-06 9:25 ` James Morse
2017-04-06 9:25 ` James Morse
2017-04-06 15:06 ` gengdongjiu
2017-04-06 15:06 ` gengdongjiu
2017-04-07 16:12 ` James Morse [this message]
2017-04-07 16:12 ` James Morse
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