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From: xuwei5@hisilicon.com (Wei Xu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC
Date: Sat, 8 Apr 2017 14:42:32 +0800	[thread overview]
Message-ID: <58E88658.20805@hisilicon.com> (raw)
In-Reply-To: <20170330064803.18648-1-hw.wangxiaoyin@hisilicon.com>

Hi Xiaoyin,

On 2017/3/30 14:48, Wang Xiaoyin wrote:
> Add drive-strength levels of pin for Hi3660 Soc.
>
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>

Thanks!
Applied both to the hisilicon arm64 dt tree.

Best Regards,
Wei
> ---
>   include/dt-bindings/pinctrl/hisi.h | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
> index 38f1ea879ea1..0359bfdc9119 100644
> --- a/include/dt-bindings/pinctrl/hisi.h
> +++ b/include/dt-bindings/pinctrl/hisi.h
> @@ -56,4 +56,19 @@
>   #define DRIVE4_08MA	(4 << 4)
>   #define DRIVE4_10MA	(6 << 4)
>   
> +/* drive strength definition for hi3660 */
> +#define DRIVE6_MASK	(15 << 4)
> +#define DRIVE6_04MA	(0 << 4)
> +#define DRIVE6_12MA	(4 << 4)
> +#define DRIVE6_19MA	(8 << 4)
> +#define DRIVE6_27MA	(10 << 4)
> +#define DRIVE6_32MA	(15 << 4)
> +#define DRIVE7_02MA	(0 << 4)
> +#define DRIVE7_04MA	(1 << 4)
> +#define DRIVE7_06MA	(2 << 4)
> +#define DRIVE7_08MA	(3 << 4)
> +#define DRIVE7_10MA	(4 << 4)
> +#define DRIVE7_12MA	(5 << 4)
> +#define DRIVE7_14MA	(6 << 4)
> +#define DRIVE7_16MA	(7 << 4)
>   #endif

WARNING: multiple messages have this Message-ID (diff)
From: Wei Xu <xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
To: Wang Xiaoyin
	<hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
	mark.rutland-5wv7dgnIgG8@public.gmane.org,
	catalin.marinas-5wv7dgnIgG8@public.gmane.org,
	will.deacon-5wv7dgnIgG8@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: chenya99-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org
Subject: Re: [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC
Date: Sat, 8 Apr 2017 14:42:32 +0800	[thread overview]
Message-ID: <58E88658.20805@hisilicon.com> (raw)
In-Reply-To: <20170330064803.18648-1-hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>

Hi Xiaoyin,

On 2017/3/30 14:48, Wang Xiaoyin wrote:
> Add drive-strength levels of pin for Hi3660 Soc.
>
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>

Thanks!
Applied both to the hisilicon arm64 dt tree.

Best Regards,
Wei
> ---
>   include/dt-bindings/pinctrl/hisi.h | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
> index 38f1ea879ea1..0359bfdc9119 100644
> --- a/include/dt-bindings/pinctrl/hisi.h
> +++ b/include/dt-bindings/pinctrl/hisi.h
> @@ -56,4 +56,19 @@
>   #define DRIVE4_08MA	(4 << 4)
>   #define DRIVE4_10MA	(6 << 4)
>   
> +/* drive strength definition for hi3660 */
> +#define DRIVE6_MASK	(15 << 4)
> +#define DRIVE6_04MA	(0 << 4)
> +#define DRIVE6_12MA	(4 << 4)
> +#define DRIVE6_19MA	(8 << 4)
> +#define DRIVE6_27MA	(10 << 4)
> +#define DRIVE6_32MA	(15 << 4)
> +#define DRIVE7_02MA	(0 << 4)
> +#define DRIVE7_04MA	(1 << 4)
> +#define DRIVE7_06MA	(2 << 4)
> +#define DRIVE7_08MA	(3 << 4)
> +#define DRIVE7_10MA	(4 << 4)
> +#define DRIVE7_12MA	(5 << 4)
> +#define DRIVE7_14MA	(6 << 4)
> +#define DRIVE7_16MA	(7 << 4)
>   #endif


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WARNING: multiple messages have this Message-ID (diff)
From: Wei Xu <xuwei5@hisilicon.com>
To: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>, <robh+dt@kernel.org>,
	<mark.rutland@arm.com>, <catalin.marinas@arm.com>,
	<will.deacon@arm.com>, <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Cc: <chenya99@hisilicon.com>
Subject: Re: [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC
Date: Sat, 8 Apr 2017 14:42:32 +0800	[thread overview]
Message-ID: <58E88658.20805@hisilicon.com> (raw)
In-Reply-To: <20170330064803.18648-1-hw.wangxiaoyin@hisilicon.com>

Hi Xiaoyin,

On 2017/3/30 14:48, Wang Xiaoyin wrote:
> Add drive-strength levels of pin for Hi3660 Soc.
>
> Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com>

Thanks!
Applied both to the hisilicon arm64 dt tree.

Best Regards,
Wei
> ---
>   include/dt-bindings/pinctrl/hisi.h | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
>
> diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h
> index 38f1ea879ea1..0359bfdc9119 100644
> --- a/include/dt-bindings/pinctrl/hisi.h
> +++ b/include/dt-bindings/pinctrl/hisi.h
> @@ -56,4 +56,19 @@
>   #define DRIVE4_08MA	(4 << 4)
>   #define DRIVE4_10MA	(6 << 4)
>   
> +/* drive strength definition for hi3660 */
> +#define DRIVE6_MASK	(15 << 4)
> +#define DRIVE6_04MA	(0 << 4)
> +#define DRIVE6_12MA	(4 << 4)
> +#define DRIVE6_19MA	(8 << 4)
> +#define DRIVE6_27MA	(10 << 4)
> +#define DRIVE6_32MA	(15 << 4)
> +#define DRIVE7_02MA	(0 << 4)
> +#define DRIVE7_04MA	(1 << 4)
> +#define DRIVE7_06MA	(2 << 4)
> +#define DRIVE7_08MA	(3 << 4)
> +#define DRIVE7_10MA	(4 << 4)
> +#define DRIVE7_12MA	(5 << 4)
> +#define DRIVE7_14MA	(6 << 4)
> +#define DRIVE7_16MA	(7 << 4)
>   #endif

  parent reply	other threads:[~2017-04-08  6:42 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-30  6:48 [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC Wang Xiaoyin
2017-03-30  6:48 ` Wang Xiaoyin
2017-03-30  6:48 ` Wang Xiaoyin
2017-03-30  6:48 ` [PATCH 2/2] arm64: dts: add pinctrl dtsi file for HiKey960 development board Wang Xiaoyin
2017-03-30  6:48   ` Wang Xiaoyin
2017-03-30  6:48   ` Wang Xiaoyin
2017-04-08  6:42 ` Wei Xu [this message]
2017-04-08  6:42   ` [PATCH 1/2] arm64: dts: add drive-strength levels of pin for Hi3660 SoC Wei Xu
2017-04-08  6:42   ` Wei Xu

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