From: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
To: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
Date: Tue, 2 May 2017 23:13:49 +0530 [thread overview]
Message-ID: <5908C555.7090204@nvidia.com> (raw)
In-Reply-To: <908ed0dc-2a75-4348-357c-191fa7348974-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
> On 02/05/17 15:05, Laxman Dewangan wrote:
>> The PWM hardware IP is taped-out with different maximum frequency
>> on different SoCs.
>>
>> From HW team:
>> Before Tegra186, it is 38.4MHz.
>> In Tegra186, it is 102MHz.
>>
>> Add support to limit the clock source frequency to the maximum IP
>> supported frequency. Provide these values via SoC chipdata.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> ---
>> Changes from V1:
>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> I think that your changelog needs to be updated, because it still says
> 38.4MHz and not 48MHz.
>
Oops, thanks for pointing.
Thierry,
Do I need to recycle the patch or can be corrected when applying?
If there is any further review comment in code then I will recycle and
correct it.
WARNING: multiple messages have this Message-ID (diff)
From: Laxman Dewangan <ldewangan@nvidia.com>
To: Jon Hunter <jonathanh@nvidia.com>, <thierry.reding@gmail.com>
Cc: <linux-pwm@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
Date: Tue, 2 May 2017 23:13:49 +0530 [thread overview]
Message-ID: <5908C555.7090204@nvidia.com> (raw)
In-Reply-To: <908ed0dc-2a75-4348-357c-191fa7348974@nvidia.com>
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
> On 02/05/17 15:05, Laxman Dewangan wrote:
>> The PWM hardware IP is taped-out with different maximum frequency
>> on different SoCs.
>>
>> From HW team:
>> Before Tegra186, it is 38.4MHz.
>> In Tegra186, it is 102MHz.
>>
>> Add support to limit the clock source frequency to the maximum IP
>> supported frequency. Provide these values via SoC chipdata.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>
>> ---
>> Changes from V1:
>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> I think that your changelog needs to be updated, because it still says
> 38.4MHz and not 48MHz.
>
Oops, thanks for pointing.
Thierry,
Do I need to recycle the patch or can be corrected when applying?
If there is any further review comment in code then I will recycle and
correct it.
next prev parent reply other threads:[~2017-05-02 17:43 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-02 14:05 [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout Laxman Dewangan
2017-05-02 14:05 ` Laxman Dewangan
[not found] ` <1493733937-15822-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 15:23 ` Jon Hunter
2017-05-02 15:23 ` Jon Hunter
[not found] ` <908ed0dc-2a75-4348-357c-191fa7348974-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 17:43 ` Laxman Dewangan [this message]
2017-05-02 17:43 ` Laxman Dewangan
[not found] ` <5908C555.7090204-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 20:10 ` Jon Hunter
2017-05-02 20:10 ` Jon Hunter
2017-05-15 15:17 ` Laxman Dewangan
2017-05-15 15:17 ` Laxman Dewangan
2017-06-13 12:32 ` Thierry Reding
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