[PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

[PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

[Monk Liu]

Change-Id: I5207135ce1356317efd43b65d9edb172a92f6374
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++++++++++------------------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 006049e..6857581 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1271,7 +1271,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
 
 	sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
 			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
-			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT; 
+			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
 
 	mutex_lock(&adev->srbm_mutex);
 	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
@@ -1424,7 +1424,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
 		 * default is 0x9C4 to create a 100us interval */
 		WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
 		/* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
-		 * to disable the page fault retry interrupts, default is 
+		 * to disable the page fault retry interrupts, default is
 		 * 0x100 (256) */
 		WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
 	}
@@ -1763,7 +1763,7 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
 		adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
 	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
 		upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
- 
+
 	/* MEC1 */
 	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
 			 mec_hdr->jt_offset);
@@ -2873,27 +2873,27 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                       struct amdgpu_ib *ib,
                                       unsigned vm_id, bool ctx_switch)
 {
-        u32 header, control = 0;
+	u32 header, control = 0;
 
-        if (ib->flags & AMDGPU_IB_FLAG_CE)
-                header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
-        else
-                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
+	if (ib->flags & AMDGPU_IB_FLAG_CE)
+		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
+	else
+		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-        control |= ib->length_dw | (vm_id << 24);
+	control |= ib->length_dw | (vm_id << 24);
 
-		if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
-			control |= INDIRECT_BUFFER_PRE_ENB(1);
+	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
+		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
-        amdgpu_ring_write(ring, header);
-	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
-        amdgpu_ring_write(ring,
+	amdgpu_ring_write(ring, header);
+BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
+	amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
-                          (2 << 0) |
+		(2 << 0) |
 #endif
-                          lower_32_bits(ib->gpu_addr));
-        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
-        amdgpu_ring_write(ring, control);
+		lower_32_bits(ib->gpu_addr));
+	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
+	amdgpu_ring_write(ring, control);
 }
 
 #define	INDIRECT_BUFFER_VALID                   (1 << 23)
-- 
2.7.4

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[PATCH 2/6] drm/amdgpu:unify gfx8/9 ce/de meta_data

[Monk Liu]

Change-Id: I9c9677b2931fa5f6ced8b4842fa336874483e02a
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 337f077..e547df4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -657,8 +657,8 @@ static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
 static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
 static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
 static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
-static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t addr);
-static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t addr);
+static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
+static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev);
 static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev);
 
@@ -6592,8 +6592,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 	uint32_t dw2 = 0;
 
 	if (amdgpu_sriov_vf(ring->adev))
-		gfx_v8_0_ring_emit_ce_meta_init(ring,
-			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
+		gfx_v8_0_ring_emit_ce_meta(ring);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
@@ -6621,8 +6620,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 	amdgpu_ring_write(ring, 0);
 
 	if (amdgpu_sriov_vf(ring->adev))
-		gfx_v8_0_ring_emit_de_meta_init(ring,
-			(flags & AMDGPU_VM_DOMAIN) ? AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
+		gfx_v8_0_ring_emit_de_meta(ring);
 }
 
 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
@@ -7162,7 +7160,7 @@ const struct amdgpu_ip_block_version gfx_v8_1_ip_block =
 	.funcs = &gfx_v8_0_ip_funcs,
 };
 
-static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t csa_addr)
+static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
 {
 	uint64_t ce_payload_addr;
 	int cnt_ce;
@@ -7172,10 +7170,12 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c
 	} ce_payload = {};
 
 	if (ring->adev->virt.chained_ib_support) {
-		ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
+		ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 +
+						  offsetof(struct vi_gfx_meta_data_chained_ib, ce_payload);
 		cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
 	} else {
-		ce_payload_addr = csa_addr + offsetof(struct vi_gfx_meta_data, ce_payload);
+		ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096 +
+						  offsetof(struct vi_gfx_meta_data, ce_payload);
 		cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
 	}
 
@@ -7189,15 +7189,16 @@ static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c
 	amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
 }
 
-static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring, uint64_t csa_addr)
+static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
 {
-	uint64_t de_payload_addr, gds_addr;
+	uint64_t de_payload_addr, gds_addr, csa_addr;
 	int cnt_de;
 	static union {
 		struct vi_de_ib_state regular;
 		struct vi_de_ib_state_chained_ib chained;
 	} de_payload = {};
 
+	csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
 	gds_addr = csa_addr + 4096;
 	if (ring->adev->virt.chained_ib_support) {
 		de_payload.chained.gds_backup_addrlo = lower_32_bits(gds_addr);
-- 
2.7.4

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[PATCH 3/6] drm/amdgpu:change SR-IOV DMAframe scheme

[Monk Liu]

According to CP/hw team requirment, to support PAL/CHAINED-IB
MCBP, kernel driver must guarantee DE_META must be inserted
right prior to the work_load DE IB (with PREEMPT flag), there
cannot be any non-work_load DE IB between-in DE_META and
work_load DE IB.

Change-Id: Ie060f1a39effa1edd5e3bf10c08624ffc82dfa44
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  9 +++++----
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++----
 2 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index e547df4..eed5745 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6407,9 +6407,13 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vm_id << 24);
 
-	if (amdgpu_sriov_vf(ring->adev) && ib->flags & AMDGPU_IB_FLAG_PREEMPT)
+	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
+		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
+			gfx_v8_0_ring_emit_de_meta(ring);
+	}
+
 	amdgpu_ring_write(ring, header);
 	amdgpu_ring_write(ring,
 #ifdef __BIG_ENDIAN
@@ -6618,9 +6622,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 	amdgpu_ring_write(ring, dw2);
 	amdgpu_ring_write(ring, 0);
-
-	if (amdgpu_sriov_vf(ring->adev))
-		gfx_v8_0_ring_emit_de_meta(ring);
 }
 
 static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6857581..f192297 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -119,6 +119,7 @@ static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
                                  struct amdgpu_cu_info *cu_info);
 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
+static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 
 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 {
@@ -2882,9 +2883,13 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vm_id << 24);
 
-	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
+	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
+		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
+			gfx_v9_0_ring_emit_de_meta(ring);
+	}
+
 	amdgpu_ring_write(ring, header);
 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 	amdgpu_ring_write(ring,
@@ -3124,9 +3129,6 @@ static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 	amdgpu_ring_write(ring, dw2);
 	amdgpu_ring_write(ring, 0);
-
-	if (amdgpu_sriov_vf(ring->adev))
-		gfx_v9_0_ring_emit_de_meta(ring);
 }
 
 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
-- 
2.7.4

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[PATCH 4/6] drm/amdgpu:new PM4 entry for VI/AI

[Monk Liu]

TMZ package will be used for VULKAN/CHAINED-IB MCBP

Change-Id: I25b82e753d078a2e3eed53a36a40798cb74d71f9
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/soc15d.h | 7 +++++++
 drivers/gpu/drm/amd/amdgpu/vid.h    | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h
index 75403c7..0733e7d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
@@ -259,6 +259,13 @@
 #define	PACKET3_WAIT_ON_CE_COUNTER			0x86
 #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
 #define	PACKET3_SWITCH_BUFFER				0x8B
+#define PACKET3_FRAME_CONTROL				0x90
+#			define FRAME_CMD(x) ((x) << 28)
+			/*
+			 * x=0: tmz_begin
+			 * x=1: tmz_end
+			 */
+
 #define PACKET3_SET_RESOURCES				0xA0
 #define PACKET3_MAP_QUEUES				0xA2
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index 5f2ab9c..a648525 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -361,6 +361,12 @@
 #define	PACKET3_WAIT_ON_CE_COUNTER			0x86
 #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF			0x88
 #define	PACKET3_SWITCH_BUFFER				0x8B
+#define PACKET3_FRAME_CONTROL				0x90
+#			define FRAME_CMD(x) ((x) << 28)
+			/*
+			 * x=0: tmz_begin
+			 * x=1: tmz_end
+			 */
 #define	PACKET3_SET_RESOURCES				0xA0
 /* 1. header
  * 2. CONTROL
-- 
2.7.4

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[PATCH 5/6] drm/amdgpu:use FRAME_CNTL for new GFX ucode

[Monk Liu]

VI/AI affected:

CP/HW team requires KMD insert FRAME_CONTROL(end) after
the last IB and before the fence of this DMAframe.

this is to make sure the cache are flushed, and it's a must
change no matter MCBP/SR-IOV or bare-metal case because new
CP hw won't do the cache flush for each IB anymore, it just
leaves it to KMD now.

with this patch, certain MCBP hang issue when rendering
vulkan/chained-ib are resolved.

Change-Id: I34ee7528aa32e704b2850bc6d50774b24c29b840
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 11 +++++++++++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 11 +++++++++++
 include/uapi/drm/amdgpu_drm.h            |  2 ++
 5 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 4480e01..df49709 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -201,6 +201,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
 			continue;
 
+		if (i == num_ibs - 1)
+			ib->flags |= AMDGPU_IB_FLAG_LAST;
+
 		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
 				    need_ctx_switch);
 		need_ctx_switch = false;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 2acaac6..03e88c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -143,6 +143,7 @@ struct amdgpu_ring_funcs {
 	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
 	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
 	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
+	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
 };
 
 struct amdgpu_ring {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index eed5745..f4aeba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6422,6 +6422,10 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 			  (ib->gpu_addr & 0xFFFFFFFC));
 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
 	amdgpu_ring_write(ring, control);
+
+	/* insert FRAME_CONTROL (end) after the last IB */
+	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
+		ring->funcs->emit_tmz(ring, false);
 }
 
 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
@@ -6651,6 +6655,12 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
 		ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
 }
 
+static void gfx_v8_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+{
+	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
+	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+}
+
 
 static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 {
@@ -6932,6 +6942,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
 	.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
 	.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
 	.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
+	.emit_tmz = gfx_v8_0_ring_emit_tmz,
 };
 
 static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f192297..745e2f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2899,6 +2899,10 @@ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 		lower_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 	amdgpu_ring_write(ring, control);
+
+	/* insert FRAME_CONTROL (end) after the last IB */
+	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
+		ring->funcs->emit_tmz(ring, false);
 }
 
 #define	INDIRECT_BUFFER_VALID                   (1 << 23)
@@ -3156,6 +3160,12 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
 		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
 }
 
+static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
+{
+	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
+	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
+}
+
 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
 {
 	struct amdgpu_device *adev = ring->adev;
@@ -3490,6 +3500,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
 	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
 	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
 	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
+	.emit_tmz = gfx_v9_0_ring_emit_tmz,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 20ea895..e979285 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -478,6 +478,8 @@ union drm_amdgpu_cs {
 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
 
+#define AMDGPU_IB_FLAG_LAST (1<<3)
+
 struct drm_amdgpu_cs_chunk_ib {
 	__u32 _pad;
 	/** AMDGPU_IB_FLAG_* */
-- 
2.7.4

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[PATCH 6/6] drm/amdgpu:cleanup flag not used

[Monk Liu]

Change-Id: I0f1727595983f144cae2d3e6d860635371c125f0
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 --
 2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f3c3c36..ec15c88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1124,7 +1124,6 @@ struct amdgpu_cs_parser {
 #define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means command submit involves a preamble IB */
 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means preamble IB is first presented in belonging context */
 #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means context switch occured */
-#define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in virtual memory context */
 
 struct amdgpu_job {
 	struct amd_sched_job    base;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index df49709..378261a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -186,8 +186,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
 			status |= AMDGPU_HAVE_CTX_SWITCH;
 		status |= job->preamble_status;
 
-		if (vm)
-			status |= AMDGPU_VM_DOMAIN;
 		amdgpu_ring_emit_cntxcntl(ring, status);
 	}
 
-- 
2.7.4

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Re: [PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

[Christian König]

Am 04.05.2017 um 12:04 schrieb Monk Liu:
> Change-Id: I5207135ce1356317efd43b65d9edb172a92f6374
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Patches #1 - #4 and #6 are Reviewed-by: Christian König 
<christian.koenig@amd.com>

For patch #5: better call this directly from amdgpu_ib_schedule.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++++++++++------------------
>   1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 006049e..6857581 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1271,7 +1271,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
>   
>   	sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
>   			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
> -			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> +			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
>   
>   	mutex_lock(&adev->srbm_mutex);
>   	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> @@ -1424,7 +1424,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
>   		 * default is 0x9C4 to create a 100us interval */
>   		WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
>   		/* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
> -		 * to disable the page fault retry interrupts, default is
> +		 * to disable the page fault retry interrupts, default is
>   		 * 0x100 (256) */
>   		WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
>   	}
> @@ -1763,7 +1763,7 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
>   		adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
>   	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
>   		upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
> -
> +
>   	/* MEC1 */
>   	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
>   			 mec_hdr->jt_offset);
> @@ -2873,27 +2873,27 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>                                         struct amdgpu_ib *ib,
>                                         unsigned vm_id, bool ctx_switch)
>   {
> -        u32 header, control = 0;
> +	u32 header, control = 0;
>   
> -        if (ib->flags & AMDGPU_IB_FLAG_CE)
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> -        else
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> +	if (ib->flags & AMDGPU_IB_FLAG_CE)
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> +	else
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
>   
> -        control |= ib->length_dw | (vm_id << 24);
> +	control |= ib->length_dw | (vm_id << 24);
>   
> -		if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
> -			control |= INDIRECT_BUFFER_PRE_ENB(1);
> +	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
> +		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
> -        amdgpu_ring_write(ring, header);
> -	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> -        amdgpu_ring_write(ring,
> +	amdgpu_ring_write(ring, header);
> +BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> +	amdgpu_ring_write(ring,
>   #ifdef __BIG_ENDIAN
> -                          (2 << 0) |
> +		(2 << 0) |
>   #endif
> -                          lower_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, control);
> +		lower_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, control);
>   }
>   
>   #define	INDIRECT_BUFFER_VALID                   (1 << 23)


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Re: [PATCH 5/6] drm/amdgpu:use FRAME_CNTL for new GFX ucode

[zhoucm1]

On 2017年05月04日 18:04, Monk Liu wrote:
> VI/AI affected:
>
> CP/HW team requires KMD insert FRAME_CONTROL(end) after
> the last IB and before the fence of this DMAframe.
>
> this is to make sure the cache are flushed, and it's a must
> change no matter MCBP/SR-IOV or bare-metal case because new
> CP hw won't do the cache flush for each IB anymore, it just
> leaves it to KMD now.
>
> with this patch, certain MCBP hang issue when rendering
> vulkan/chained-ib are resolved.
>
> Change-Id: I34ee7528aa32e704b2850bc6d50774b24c29b840
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  3 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 11 +++++++++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 11 +++++++++++
>   include/uapi/drm/amdgpu_drm.h            |  2 ++
>   5 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 4480e01..df49709 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -201,6 +201,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
>   			continue;
>   
> +		if (i == num_ibs - 1)
> +			ib->flags |= AMDGPU_IB_FLAG_LAST;
We can wrap the ring func like amdgpu_ring_emit_tmz(), and add it before 
emit fence. Or how about to insert it to gfx emit fence?

Regards,
David Zhou
> +
>   		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
>   				    need_ctx_switch);
>   		need_ctx_switch = false;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 2acaac6..03e88c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -143,6 +143,7 @@ struct amdgpu_ring_funcs {
>   	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
>   	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
>   	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
> +	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
>   };
>   
>   struct amdgpu_ring {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index eed5745..f4aeba6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6422,6 +6422,10 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   			  (ib->gpu_addr & 0xFFFFFFFC));
>   	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
>   	amdgpu_ring_write(ring, control);
> +
> +	/* insert FRAME_CONTROL (end) after the last IB */
> +	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
> +		ring->funcs->emit_tmz(ring, false);
>   }
>   
>   static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
> @@ -6651,6 +6655,12 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
>   		ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
>   }
>   
> +static void gfx_v8_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
> +	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
> +}
> +
>   
>   static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
>   {
> @@ -6932,6 +6942,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
>   	.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
>   	.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
>   	.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
> +	.emit_tmz = gfx_v8_0_ring_emit_tmz,
>   };
>   
>   static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f192297..745e2f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2899,6 +2899,10 @@ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
>   		lower_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, control);
> +
> +	/* insert FRAME_CONTROL (end) after the last IB */
> +	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
> +		ring->funcs->emit_tmz(ring, false);
>   }
>   
>   #define	INDIRECT_BUFFER_VALID                   (1 << 23)
> @@ -3156,6 +3160,12 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
>   		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
>   }
>   
> +static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
> +	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
> +}
> +
>   static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> @@ -3490,6 +3500,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>   	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
>   	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
>   	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
> +	.emit_tmz = gfx_v9_0_ring_emit_tmz,
>   };
>   
>   static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 20ea895..e979285 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -478,6 +478,8 @@ union drm_amdgpu_cs {
>   /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
>   #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
>   
> +#define AMDGPU_IB_FLAG_LAST (1<<3)
> +
>   struct drm_amdgpu_cs_chunk_ib {
>   	__u32 _pad;
>   	/** AMDGPU_IB_FLAG_* */

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Re: [PATCH 5/6] drm/amdgpu:use FRAME_CNTL for new GFX ucode

[zhoucm1]

On 2017年05月04日 18:04, Monk Liu wrote:
> VI/AI affected:
>
> CP/HW team requires KMD insert FRAME_CONTROL(end) after
> the last IB and before the fence of this DMAframe.
>
> this is to make sure the cache are flushed, and it's a must
> change no matter MCBP/SR-IOV or bare-metal case because new
> CP hw won't do the cache flush for each IB anymore, it just
> leaves it to KMD now.
>
> with this patch, certain MCBP hang issue when rendering
> vulkan/chained-ib are resolved.
>
> Change-Id: I34ee7528aa32e704b2850bc6d50774b24c29b840
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  3 +++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 11 +++++++++++
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c    | 11 +++++++++++
>   include/uapi/drm/amdgpu_drm.h            |  2 ++
>   5 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index 4480e01..df49709 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -201,6 +201,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>   			!amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
>   			continue;
>   
> +		if (i == num_ibs - 1)
> +			ib->flags |= AMDGPU_IB_FLAG_LAST;
We can wrap the ring func like amdgpu_ring_emit_tmz(), and add it before 
emit fence.

Regards,
David Zhou
> +
>   		amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
>   				    need_ctx_switch);
>   		need_ctx_switch = false;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 2acaac6..03e88c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -143,6 +143,7 @@ struct amdgpu_ring_funcs {
>   	void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
>   	void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
>   	void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
> +	void (*emit_tmz)(struct amdgpu_ring *ring, bool start);
>   };
>   
>   struct amdgpu_ring {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index eed5745..f4aeba6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6422,6 +6422,10 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   			  (ib->gpu_addr & 0xFFFFFFFC));
>   	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
>   	amdgpu_ring_write(ring, control);
> +
> +	/* insert FRAME_CONTROL (end) after the last IB */
> +	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
> +		ring->funcs->emit_tmz(ring, false);
>   }
>   
>   static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
> @@ -6651,6 +6655,12 @@ static void gfx_v8_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
>   		ring->ring[offset] = (ring->ring_size >> 2) - offset + cur;
>   }
>   
> +static void gfx_v8_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
> +	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
> +}
> +
>   
>   static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
>   {
> @@ -6932,6 +6942,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
>   	.emit_cntxcntl = gfx_v8_ring_emit_cntxcntl,
>   	.init_cond_exec = gfx_v8_0_ring_emit_init_cond_exec,
>   	.patch_cond_exec = gfx_v8_0_ring_emit_patch_cond_exec,
> +	.emit_tmz = gfx_v8_0_ring_emit_tmz,
>   };
>   
>   static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f192297..745e2f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2899,6 +2899,10 @@ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
>   		lower_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
>   	amdgpu_ring_write(ring, control);
> +
> +	/* insert FRAME_CONTROL (end) after the last IB */
> +	if (ib->flags & AMDGPU_IB_FLAG_LAST && ring->funcs->emit_tmz)
> +		ring->funcs->emit_tmz(ring, false);
>   }
>   
>   #define	INDIRECT_BUFFER_VALID                   (1 << 23)
> @@ -3156,6 +3160,12 @@ static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigne
>   		ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
>   }
>   
> +static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
> +{
> +	amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
> +	amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
> +}
> +
>   static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
>   {
>   	struct amdgpu_device *adev = ring->adev;
> @@ -3490,6 +3500,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
>   	.emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
>   	.init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
>   	.patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
> +	.emit_tmz = gfx_v9_0_ring_emit_tmz,
>   };
>   
>   static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 20ea895..e979285 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -478,6 +478,8 @@ union drm_amdgpu_cs {
>   /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
>   #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
>   
> +#define AMDGPU_IB_FLAG_LAST (1<<3)
> +
>   struct drm_amdgpu_cs_chunk_ib {
>   	__u32 _pad;
>   	/** AMDGPU_IB_FLAG_* */

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RE: [PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

[Liu, Monk]

Okay, changed as you and David suggest 

-----Original Message-----
From: Christian König [mailto:deathsimple@vodafone.de] 
Sent: Thursday, May 04, 2017 6:17 PM
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

Am 04.05.2017 um 12:04 schrieb Monk Liu:
> Change-Id: I5207135ce1356317efd43b65d9edb172a92f6374
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Patches #1 - #4 and #6 are Reviewed-by: Christian König <christian.koenig@amd.com>

For patch #5: better call this directly from amdgpu_ib_schedule.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++++++++++------------------
>   1 file changed, 18 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 006049e..6857581 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1271,7 +1271,7 @@ static void gfx_v9_0_init_compute_vmid(struct 
> amdgpu_device *adev)
>   
>   	sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
>   			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
> -			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> +			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
>   
>   	mutex_lock(&adev->srbm_mutex);
>   	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) { @@ 
> -1424,7 +1424,7 @@ static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
>   		 * default is 0x9C4 to create a 100us interval */
>   		WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
>   		/* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
> -		 * to disable the page fault retry interrupts, default is
> +		 * to disable the page fault retry interrupts, default is
>   		 * 0x100 (256) */
>   		WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
>   	}
> @@ -1763,7 +1763,7 @@ static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
>   		adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
>   	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
>   		upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
> -
> +
>   	/* MEC1 */
>   	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
>   			 mec_hdr->jt_offset);
> @@ -2873,27 +2873,27 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>                                         struct amdgpu_ib *ib,
>                                         unsigned vm_id, bool ctx_switch)
>   {
> -        u32 header, control = 0;
> +	u32 header, control = 0;
>   
> -        if (ib->flags & AMDGPU_IB_FLAG_CE)
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> -        else
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> +	if (ib->flags & AMDGPU_IB_FLAG_CE)
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> +	else
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
>   
> -        control |= ib->length_dw | (vm_id << 24);
> +	control |= ib->length_dw | (vm_id << 24);
>   
> -		if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
> -			control |= INDIRECT_BUFFER_PRE_ENB(1);
> +	if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT))
> +		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
> -        amdgpu_ring_write(ring, header);
> -	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> -        amdgpu_ring_write(ring,
> +	amdgpu_ring_write(ring, header);
> +BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> +	amdgpu_ring_write(ring,
>   #ifdef __BIG_ENDIAN
> -                          (2 << 0) |
> +		(2 << 0) |
>   #endif
> -                          lower_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, control);
> +		lower_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, control);
>   }
>   
>   #define	INDIRECT_BUFFER_VALID                   (1 << 23)


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RE: [PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, May 04, 2017 6:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 1/6] drm/amdgpu:cleanup intent/format for gfx_v9_0.c
> 
> Change-Id: I5207135ce1356317efd43b65d9edb172a92f6374
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++++++++++-------
> -----------
>  1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 006049e..6857581 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1271,7 +1271,7 @@ static void gfx_v9_0_init_compute_vmid(struct
> amdgpu_device *adev)
> 
>  	sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
>  			SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
> -			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> +			SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
> 
>  	mutex_lock(&adev->srbm_mutex);
>  	for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
> @@ -1424,7 +1424,7 @@ static void gfx_v9_0_rlc_start(struct
> amdgpu_device *adev)
>  		 * default is 0x9C4 to create a 100us interval */
>  		WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
>  		/* RLC_GPM_GENERAL_12 : Minimum gap between wptr
> and rptr
> -		 * to disable the page fault retry interrupts, default is
> +		 * to disable the page fault retry interrupts, default is
>  		 * 0x100 (256) */
>  		WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
>  	}
> @@ -1763,7 +1763,7 @@ static int
> gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
>  		adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
>  	WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
>  		upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
> -
> +
>  	/* MEC1 */
>  	WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
>  			 mec_hdr->jt_offset);
> @@ -2873,27 +2873,27 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
>                                        struct amdgpu_ib *ib,
>                                        unsigned vm_id, bool ctx_switch)
>  {
> -        u32 header, control = 0;
> +	u32 header, control = 0;
> 
> -        if (ib->flags & AMDGPU_IB_FLAG_CE)
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> -        else
> -                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> +	if (ib->flags & AMDGPU_IB_FLAG_CE)
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
> +	else
> +		header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
> 
> -        control |= ib->length_dw | (vm_id << 24);
> +	control |= ib->length_dw | (vm_id << 24);
> 
> -		if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
> AMDGPU_IB_FLAG_PREEMPT))
> -			control |= INDIRECT_BUFFER_PRE_ENB(1);
> +	if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
> AMDGPU_IB_FLAG_PREEMPT))
> +		control |= INDIRECT_BUFFER_PRE_ENB(1);
> 
> -        amdgpu_ring_write(ring, header);
> -	BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> -        amdgpu_ring_write(ring,
> +	amdgpu_ring_write(ring, header);
> +BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
> +	amdgpu_ring_write(ring,
>  #ifdef __BIG_ENDIAN
> -                          (2 << 0) |
> +		(2 << 0) |
>  #endif
> -                          lower_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> -        amdgpu_ring_write(ring, control);
> +		lower_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
> +	amdgpu_ring_write(ring, control);
>  }
> 
>  #define	INDIRECT_BUFFER_VALID                   (1 << 23)
> --
> 2.7.4
> 
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 2/6] drm/amdgpu:unify gfx8/9 ce/de meta_data

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, May 04, 2017 6:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 2/6] drm/amdgpu:unify gfx8/9 ce/de meta_data
> 
> Change-Id: I9c9677b2931fa5f6ced8b4842fa336874483e02a
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 ++++++++++++-----------
>  1 file changed, 12 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 337f077..e547df4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -657,8 +657,8 @@ static void gfx_v8_0_set_gds_init(struct
> amdgpu_device *adev);
>  static void gfx_v8_0_set_rlc_funcs(struct amdgpu_device *adev);
>  static u32 gfx_v8_0_get_csb_size(struct amdgpu_device *adev);
>  static void gfx_v8_0_get_cu_info(struct amdgpu_device *adev);
> -static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring,
> uint64_t addr);
> -static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring,
> uint64_t addr);
> +static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring);
> +static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring);
>  static int gfx_v8_0_compute_mqd_sw_init(struct amdgpu_device *adev);
>  static void gfx_v8_0_compute_mqd_sw_fini(struct amdgpu_device *adev);
> 
> @@ -6592,8 +6592,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct
> amdgpu_ring *ring, uint32_t flags)
>  	uint32_t dw2 = 0;
> 
>  	if (amdgpu_sriov_vf(ring->adev))
> -		gfx_v8_0_ring_emit_ce_meta_init(ring,
> -			(flags & AMDGPU_VM_DOMAIN) ?
> AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
> +		gfx_v8_0_ring_emit_ce_meta(ring);
> 
>  	dw2 |= 0x80000000; /* set load_enable otherwise this package is just
> NOPs */
>  	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> @@ -6621,8 +6620,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct
> amdgpu_ring *ring, uint32_t flags)
>  	amdgpu_ring_write(ring, 0);
> 
>  	if (amdgpu_sriov_vf(ring->adev))
> -		gfx_v8_0_ring_emit_de_meta_init(ring,
> -			(flags & AMDGPU_VM_DOMAIN) ?
> AMDGPU_CSA_VADDR : ring->adev->virt.csa_vmid0_addr);
> +		gfx_v8_0_ring_emit_de_meta(ring);
>  }
> 
>  static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring
> *ring)
> @@ -7162,7 +7160,7 @@ const struct amdgpu_ip_block_version
> gfx_v8_1_ip_block =
>  	.funcs = &gfx_v8_0_ip_funcs,
>  };
> 
> -static void gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring,
> uint64_t csa_addr)
> +static void gfx_v8_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
>  {
>  	uint64_t ce_payload_addr;
>  	int cnt_ce;
> @@ -7172,10 +7170,12 @@ static void
> gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c
>  	} ce_payload = {};
> 
>  	if (ring->adev->virt.chained_ib_support) {
> -		ce_payload_addr = csa_addr + offsetof(struct
> vi_gfx_meta_data_chained_ib, ce_payload);
> +		ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096
> +
> +						  offsetof(struct
> vi_gfx_meta_data_chained_ib, ce_payload);
>  		cnt_ce = (sizeof(ce_payload.chained) >> 2) + 4 - 2;
>  	} else {
> -		ce_payload_addr = csa_addr + offsetof(struct
> vi_gfx_meta_data, ce_payload);
> +		ce_payload_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096
> +
> +						  offsetof(struct
> vi_gfx_meta_data, ce_payload);
>  		cnt_ce = (sizeof(ce_payload.regular) >> 2) + 4 - 2;
>  	}
> 
> @@ -7189,15 +7189,16 @@ static void
> gfx_v8_0_ring_emit_ce_meta_init(struct amdgpu_ring *ring, uint64_t c
>  	amdgpu_ring_write_multiple(ring, (void *)&ce_payload, cnt_ce - 2);
>  }
> 
> -static void gfx_v8_0_ring_emit_de_meta_init(struct amdgpu_ring *ring,
> uint64_t csa_addr)
> +static void gfx_v8_0_ring_emit_de_meta(struct amdgpu_ring *ring)
>  {
> -	uint64_t de_payload_addr, gds_addr;
> +	uint64_t de_payload_addr, gds_addr, csa_addr;
>  	int cnt_de;
>  	static union {
>  		struct vi_de_ib_state regular;
>  		struct vi_de_ib_state_chained_ib chained;
>  	} de_payload = {};
> 
> +	csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
>  	gds_addr = csa_addr + 4096;
>  	if (ring->adev->virt.chained_ib_support) {
>  		de_payload.chained.gds_backup_addrlo =
> lower_32_bits(gds_addr);
> --
> 2.7.4
> 
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RE: [PATCH 3/6] drm/amdgpu:change SR-IOV DMAframe scheme

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, May 04, 2017 6:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 3/6] drm/amdgpu:change SR-IOV DMAframe scheme
> 
> According to CP/hw team requirment, to support PAL/CHAINED-IB
> MCBP, kernel driver must guarantee DE_META must be inserted
> right prior to the work_load DE IB (with PREEMPT flag), there
> cannot be any non-work_load DE IB between-in DE_META and
> work_load DE IB.
> 
> Change-Id: Ie060f1a39effa1edd5e3bf10c08624ffc82dfa44
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c |  9 +++++----
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++----
>  2 files changed, 11 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index e547df4..eed5745 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -6407,9 +6407,13 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
> 
>  	control |= ib->length_dw | (vm_id << 24);
> 
> -	if (amdgpu_sriov_vf(ring->adev) && ib->flags &
> AMDGPU_IB_FLAG_PREEMPT)
> +	if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
> AMDGPU_IB_FLAG_PREEMPT)) {
>  		control |= INDIRECT_BUFFER_PRE_ENB(1);
> 
> +		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
> +			gfx_v8_0_ring_emit_de_meta(ring);
> +	}
> +
>  	amdgpu_ring_write(ring, header);
>  	amdgpu_ring_write(ring,
>  #ifdef __BIG_ENDIAN
> @@ -6618,9 +6622,6 @@ static void gfx_v8_ring_emit_cntxcntl(struct
> amdgpu_ring *ring, uint32_t flags)
>  	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL,
> 1));
>  	amdgpu_ring_write(ring, dw2);
>  	amdgpu_ring_write(ring, 0);
> -
> -	if (amdgpu_sriov_vf(ring->adev))
> -		gfx_v8_0_ring_emit_de_meta(ring);
>  }
> 
>  static unsigned gfx_v8_0_ring_emit_init_cond_exec(struct amdgpu_ring
> *ring)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 6857581..f192297 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -119,6 +119,7 @@ static int gfx_v9_0_get_cu_info(struct
> amdgpu_device *adev,
>                                   struct amdgpu_cu_info *cu_info);
>  static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
> *adev);
>  static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32
> se_num, u32 sh_num, u32 instance);
> +static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
> 
>  static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
>  {
> @@ -2882,9 +2883,13 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct
> amdgpu_ring *ring,
> 
>  	control |= ib->length_dw | (vm_id << 24);
> 
> -	if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
> AMDGPU_IB_FLAG_PREEMPT))
> +	if (amdgpu_sriov_vf(ring->adev) && (ib->flags &
> AMDGPU_IB_FLAG_PREEMPT)) {
>  		control |= INDIRECT_BUFFER_PRE_ENB(1);
> 
> +		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
> +			gfx_v9_0_ring_emit_de_meta(ring);
> +	}
> +
>  	amdgpu_ring_write(ring, header);
>  BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
>  	amdgpu_ring_write(ring,
> @@ -3124,9 +3129,6 @@ static void gfx_v9_ring_emit_cntxcntl(struct
> amdgpu_ring *ring, uint32_t flags)
>  	amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL,
> 1));
>  	amdgpu_ring_write(ring, dw2);
>  	amdgpu_ring_write(ring, 0);
> -
> -	if (amdgpu_sriov_vf(ring->adev))
> -		gfx_v9_0_ring_emit_de_meta(ring);
>  }
> 
>  static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring
> *ring)
> --
> 2.7.4
> 
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 4/6] drm/amdgpu:new PM4 entry for VI/AI

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, May 04, 2017 6:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 4/6] drm/amdgpu:new PM4 entry for VI/AI
> 
> TMZ package will be used for VULKAN/CHAINED-IB MCBP
> 
> Change-Id: I25b82e753d078a2e3eed53a36a40798cb74d71f9
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/soc15d.h | 7 +++++++
>  drivers/gpu/drm/amd/amdgpu/vid.h    | 6 ++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> index 75403c7..0733e7d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h
> @@ -259,6 +259,13 @@
>  #define	PACKET3_WAIT_ON_CE_COUNTER			0x86
>  #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF
> 	0x88
>  #define	PACKET3_SWITCH_BUFFER				0x8B
> +#define PACKET3_FRAME_CONTROL				0x90
> +#			define FRAME_CMD(x) ((x) << 28)
> +			/*
> +			 * x=0: tmz_begin
> +			 * x=1: tmz_end
> +			 */
> +
>  #define PACKET3_SET_RESOURCES				0xA0
>  #define PACKET3_MAP_QUEUES				0xA2
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h
> b/drivers/gpu/drm/amd/amdgpu/vid.h
> index 5f2ab9c..a648525 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vid.h
> @@ -361,6 +361,12 @@
>  #define	PACKET3_WAIT_ON_CE_COUNTER			0x86
>  #define	PACKET3_WAIT_ON_DE_COUNTER_DIFF
> 	0x88
>  #define	PACKET3_SWITCH_BUFFER				0x8B
> +#define PACKET3_FRAME_CONTROL				0x90
> +#			define FRAME_CMD(x) ((x) << 28)
> +			/*
> +			 * x=0: tmz_begin
> +			 * x=1: tmz_end
> +			 */
>  #define	PACKET3_SET_RESOURCES				0xA0
>  /* 1. header
>   * 2. CONTROL
> --
> 2.7.4
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH 6/6] drm/amdgpu:cleanup flag not used

[Deucher, Alexander]

> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Monk Liu
> Sent: Thursday, May 04, 2017 6:05 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk
> Subject: [PATCH 6/6] drm/amdgpu:cleanup flag not used
> 
> Change-Id: I0f1727595983f144cae2d3e6d860635371c125f0
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h    | 1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 --
>  2 files changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index f3c3c36..ec15c88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1124,7 +1124,6 @@ struct amdgpu_cs_parser {
>  #define AMDGPU_PREAMBLE_IB_PRESENT          (1 << 0) /* bit set means
> command submit involves a preamble IB */
>  #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST    (1 << 1) /* bit set means
> preamble IB is first presented in belonging context */
>  #define AMDGPU_HAVE_CTX_SWITCH              (1 << 2) /* bit set means
> context switch occured */
> -#define AMDGPU_VM_DOMAIN                    (1 << 3) /* bit set means in
> virtual memory context */
> 
>  struct amdgpu_job {
>  	struct amd_sched_job    base;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index df49709..378261a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -186,8 +186,6 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring,
> unsigned num_ibs,
>  			status |= AMDGPU_HAVE_CTX_SWITCH;
>  		status |= job->preamble_status;
> 
> -		if (vm)
> -			status |= AMDGPU_VM_DOMAIN;
>  		amdgpu_ring_emit_cntxcntl(ring, status);
>  	}
> 
> --
> 2.7.4
> 
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