Re: [PATCH] arm64: dts: rockchip: Fix wrong register range of rk3576 gpu

From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
To: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Chaoyi Chen <chaoyi.chen@rock-chips.com>,
	Kever Yang <kever.yang@rock-chips.com>,
	Sebastian Reichel <sebastian.reichel@collabora.com>,
	Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
	Frank Wang <frank.wang@rock-chips.com>,
	Alexey Charkov <alchark@gmail.com>,
	Liang Chen <cl@rock-chips.com>,
	Finley Xiao <finley.xiao@rock-chips.com>,
	Elaine Zhang <zhangqing@rock-chips.com>,
	Yifeng Zhao <yifeng.zhao@rock-chips.com>,
	Chaoyi Chen <kernel@airkyi.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: rockchip: Fix wrong register range of rk3576 gpu
Date: Mon, 05 Jan 2026 08:55:17 +0100	[thread overview]
Message-ID: <5954009.DvuYhMxLoT@workhorse> (raw)
In-Reply-To: <20251230090246.46-1-kernel@airkyi.com>

On Tuesday, 30 December 2025 10:02:46 Central European Standard Time Chaoyi Chen wrote:
> From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> 
> According to RK3576 TRM part1 page13, the size of the GPU registers
> is 128 KB.
> 
> Fixes: 57b1ce903966 ("arm64: dts: rockchip: Add rk3576 SoC base DT")
> Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> index 6284e7bdc442..b375015f0662 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
> @@ -1271,7 +1271,7 @@ power-domain@RK3576_PD_VO1 {
>  
>  		gpu: gpu@27800000 {
>  			compatible = "rockchip,rk3576-mali", "arm,mali-bifrost";
> -			reg = <0x0 0x27800000 0x0 0x200000>;
> +			reg = <0x0 0x27800000 0x0 0x20000>;
>  			assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
>  			assigned-clock-rates = <198000000>;
>  			clocks = <&cru CLK_GPU>;
> 

This is only true if you only consider the GPU_CONTROL and
JOB_CONTROL register ranges, and leave out the MMU_STAGE1
and MMU_STAGE2 ranges. I don't know if those need to be
mapped, since the MMU control registers are < 0x2000.

What do other bifrost devices do?

Kind regards,
Nicolas Frattaroli