[PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[Allen Pais]

From: Vijay Kumar <vijay.ac.kumar@oracle.com>

On M8 chips, use a max_phys_bits value of 51 and also fix the VA hole.

Signed-off-by: Vijay Kumar <vijay.ac.kumar@oracle.com>
Reviewed-by: Bob Picco <bob.picco@oracle.com>
Signed-off-by: Allen Pais <allen.pais@oracle.com>
---
 arch/sparc/mm/init_64.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index a111625..04c9ea3 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -1921,12 +1921,18 @@ static void __init setup_page_offset(void)
 			break;
 		case SUN4V_CHIP_SPARC_M7:
 		case SUN4V_CHIP_SPARC_SN:
-		default:
 			/* M7 and later support 52-bit virtual addresses.  */
 			sparc64_va_hole_top =    0xfff8000000000000UL;
 			sparc64_va_hole_bottom = 0x0008000000000000UL;
 			max_phys_bits = 49;
 			break;
+		case SUN4V_CHIP_SPARC_M8:
+		default:
+			/* M8 and later support 54-bit virtual addresses.  */
+			sparc64_va_hole_top =    0xffe0000000000000UL;
+			sparc64_va_hole_bottom = 0x0020000000000000UL;
+			max_phys_bits = 51;
+			break;
 		}
 	}
 
-- 
1.9.1

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[Vijay Kumar]

Hi Allen,

On 7/24/2017 1:14 AM, Allen Pais wrote:
 > From: Vijay Kumar <vijay.ac.kumar@oracle.com>
 >
 > On M8 chips, use a max_phys_bits value of 51 and also fix the VA hole.
 >
 > Signed-off-by: Vijay Kumar <vijay.ac.kumar@oracle.com>
 > Reviewed-by: Bob Picco <bob.picco@oracle.com>
 > Signed-off-by: Allen Pais <allen.pais@oracle.com>
 > ---

This patch needs to go with sparc-5-Level-paging  patch. I am still 
working on adding boot time selection option, so please ignore this 
patch for now. I will post this patch separately with sparc-5-level patch.

Thanks,
Vijay

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[John Paul Adrian Glaubitz]

Hi!

On Mon, Jul 24, 2017 at 11:44:19AM +0530, Allen Pais wrote:
> On M8 chips, use a max_phys_bits value of 51 and also fix the VA
> hole.

Are there any plans to add the possibility to limit the VA space per
process to 48 bits?  I'm asking since some applications, in particular
JavaScript engines are using the upper bits for tagging pointers.

This has the result that on sparc64, software like NodeJS or QtScript
doesn't build at the moment. See this discussion for more [1].

As five-level page tables were added for x86 as well to extend the VA
space to 52 bits [2], I asked the kernel maintainers behind these
patches and they told me they have the possibility to limit the
address space per process on x86 to avoid these issues.

Would it be possible to add this feature on sparc64 as well?

Thanks,
Adrian

> [1] https://bugreports.qt.io/browse/QTBUG-56264
> [2] https://lwn.net/Articles/717293/

-- 
 .''`.  John Paul Adrian Glaubitz
: :' :  Debian Developer - glaubitz@debian.org
`. `'   Freie Universitaet Berlin - glaubitz@physik.fu-berlin.de
  `-    GPG: 62FF 8A75 84E0 2956 9546  0006 7426 3B37 F5B5 F913

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[Allen]

>
> This patch needs to go with sparc-5-Level-paging  patch. I am still
> working on adding boot time selection option, so please ignore this
> patch for now. I will post this patch separately with sparc-5-level patch.

  My bad. David, could you please ignore this patch for the moment.

- Allen

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[David Miller]

From: Allen <allen.pais@oracle.com>
Date: Mon, 24 Jul 2017 19:33:27 +0530

>> This patch needs to go with sparc-5-Level-paging  patch. I am still
>> working on adding boot time selection option, so please ignore this
>> patch for now. I will post this patch separately with sparc-5-level
>> patch.
> 
>  My bad. David, could you please ignore this patch for the moment.

Wait, why do you need 5 level page tables for this?

The existing 4 level code supports up to 53-bits and you need only 51
for M8.

There is even a check for this limit in asm/pgtable_64.h:

#if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)
#error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support
#endif

#if (PGDIR_SHIFT + PGDIR_BITS) != 53
#error Page table parameters do not cover virtual address space properly.
#endif

We've supported up to 53-bits forever, from page_64.h:

#define MAX_PHYS_ADDRESS_BITS	53

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[Vijay Kumar]

On 7/26/2017 1:11 AM, David Miller wrote:
> From: Allen <allen.pais@oracle.com>
> Date: Mon, 24 Jul 2017 19:33:27 +0530
>
>>> This patch needs to go with sparc-5-Level-paging  patch. I am still
>>> working on adding boot time selection option, so please ignore this
>>> patch for now. I will post this patch separately with sparc-5-level
>>> patch.
>>   My bad. David, could you please ignore this patch for the moment.
> Wait, why do you need 5 level page tables for this?
>
> The existing 4 level code supports up to 53-bits and you need only 51
> for M8.
>
> There is even a check for this limit in asm/pgtable_64.h:
>
> #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)
> #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support
> #endif
>
> #if (PGDIR_SHIFT + PGDIR_BITS) != 53
> #error Page table parameters do not cover virtual address space properly.
> #endif
>
> We've supported up to 53-bits forever, from page_64.h:
>
> #define MAX_PHYS_ADDRESS_BITS	53
Issue is not with Physical-address-bits but with virtual-address-bits. 
With this patch, virtual address bits for M8 is increased to 54 whereas 
current  pagetable supports up to 53 bits only.

PGDIR_BITS + PUD_BITS + PMD_BITS + PAGE_SHIFT + PAGE_OFFSET = 10 + 10 + 
10 + 10 + 13 = 53 bits

Just to verify, I applied this patch and M8 does not boot up.

Did I miss anything?

- Vijay

Re: [PATCH v2 3/3] sparc64: Increase max_phys_bits to 51 for M8.

[David Miller]

From: Vijay Kumar <vijay.ac.kumar@oracle.com>
Date: Wed, 26 Jul 2017 14:57:01 -0500

> 
> On 7/26/2017 1:11 AM, David Miller wrote:
>> From: Allen <allen.pais@oracle.com>
>> Date: Mon, 24 Jul 2017 19:33:27 +0530
>>
>>>> This patch needs to go with sparc-5-Level-paging  patch. I am still
>>>> working on adding boot time selection option, so please ignore this
>>>> patch for now. I will post this patch separately with sparc-5-level
>>>> patch.
>>>   My bad. David, could you please ignore this patch for the moment.
>> Wait, why do you need 5 level page tables for this?
>>
>> The existing 4 level code supports up to 53-bits and you need only 51
>> for M8.
>>
>> There is even a check for this limit in asm/pgtable_64.h:
>>
>> #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)
>> #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can
>> #support
>> #endif
>>
>> #if (PGDIR_SHIFT + PGDIR_BITS) != 53
>> #error Page table parameters do not cover virtual address space
>> #properly.
>> #endif
>>
>> We've supported up to 53-bits forever, from page_64.h:
>>
>> #define MAX_PHYS_ADDRESS_BITS	53
> Issue is not with Physical-address-bits but with
> virtual-address-bits. With this patch, virtual address bits for M8 is
> increased to 54 whereas current pagetable supports up to 53 bits only.
> 
> PGDIR_BITS + PUD_BITS + PMD_BITS + PAGE_SHIFT + PAGE_OFFSET = 10 + 10
> + 10 + 10 + 13 = 53 bits
> 
> Just to verify, I applied this patch and M8 does not boot up.
> 
> Did I miss anything?

Ok, the chip can do 54 bits.

Can you guys just live with 53 bits for now?  Thanks.

Please resubmit the M8 support patches, using 53 virtual address
bits.  You can add a comment there stating that the chip supports
54 but the 4-level page tables currently cannot support that.

Maybe we can meanwhile figure out some trick to grab an extra virtual
address bit from the page table layout without going to 5-levels.