All of lore.kernel.org
 help / color / mirror / Atom feed
From: xuwei5@hisilicon.com (Wei Xu)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] arm64: dts: hisi: add PCIe host controller node for hip07 SoC
Date: Fri, 4 Aug 2017 14:01:46 +0100	[thread overview]
Message-ID: <5984703A.4060302@hisilicon.com> (raw)
In-Reply-To: <1500366820-58555-1-git-send-email-wangzhou1@hisilicon.com>

Hi Zhou,

On 2017/7/18 9:33, Zhou Wang wrote:
> Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in
> D05 board.
> 
> Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
> ---
>  arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  4 ++++
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 21 +++++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> index f5d7f08..fe7c16c 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> @@ -84,3 +84,7 @@
>  &sas1 {
>  	status = "ok";
>  };
> +
> +&p0_pcie2_a {
> +	status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> index 283d7b5..077b2d7b 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -1534,5 +1534,26 @@
>  				     <637 1>,<638 1>,<639 1>;
>  			status = "disabled";
>  		};
> +
> +		p0_pcie2_a: pcie at a00a0000 {
> +			compatible = "hisilicon,pcie-almost-ecam";

The compatible string should be "hisilicon,hip07-pcie-ecam".

> +			reg = <0 0xa8000000 0 0x800000>,<0 0xa00a0000 0 0x10000>;
> +			bus-range = <0x80 0x87>;
> +			msi-map = <0x8000 &p0_its_dsa_a 0x8000 0x800>;
> +			msi-map-mask = <0xffff>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			device_type = "pci";
> +			dma-coherent;
> +			ranges = <0x02000000 0 0xa8800000 0 0xa8800000 0 0x77f0000
> +				  0x01000000 0 0 0 0xafff0000 0 0x10000>;

Can you also check whether the ranges are working or not with current UEFI?
Thanks!

Best Regards,
Wei

> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0xf800 0 0 7>;
> +			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 2 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 3 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
> +			status = "disabled";
> +		};
>  	};
>  };
> 

WARNING: multiple messages have this Message-ID (diff)
From: Wei Xu <xuwei5-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
To: Zhou Wang <wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>,
	Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
	Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
	Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: Re: [PATCH] arm64: dts: hisi: add PCIe host controller node for hip07 SoC
Date: Fri, 4 Aug 2017 14:01:46 +0100	[thread overview]
Message-ID: <5984703A.4060302@hisilicon.com> (raw)
In-Reply-To: <1500366820-58555-1-git-send-email-wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>

Hi Zhou,

On 2017/7/18 9:33, Zhou Wang wrote:
> Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in
> D05 board.
> 
> Signed-off-by: Zhou Wang <wangzhou1-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
>  arch/arm64/boot/dts/hisilicon/hip07-d05.dts |  4 ++++
>  arch/arm64/boot/dts/hisilicon/hip07.dtsi    | 21 +++++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> index f5d7f08..fe7c16c 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> +++ b/arch/arm64/boot/dts/hisilicon/hip07-d05.dts
> @@ -84,3 +84,7 @@
>  &sas1 {
>  	status = "ok";
>  };
> +
> +&p0_pcie2_a {
> +	status = "ok";
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> index 283d7b5..077b2d7b 100644
> --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> @@ -1534,5 +1534,26 @@
>  				     <637 1>,<638 1>,<639 1>;
>  			status = "disabled";
>  		};
> +
> +		p0_pcie2_a: pcie@a00a0000 {
> +			compatible = "hisilicon,pcie-almost-ecam";

The compatible string should be "hisilicon,hip07-pcie-ecam".

> +			reg = <0 0xa8000000 0 0x800000>,<0 0xa00a0000 0 0x10000>;
> +			bus-range = <0x80 0x87>;
> +			msi-map = <0x8000 &p0_its_dsa_a 0x8000 0x800>;
> +			msi-map-mask = <0xffff>;
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			device_type = "pci";
> +			dma-coherent;
> +			ranges = <0x02000000 0 0xa8800000 0 0xa8800000 0 0x77f0000
> +				  0x01000000 0 0 0 0xafff0000 0 0x10000>;

Can you also check whether the ranges are working or not with current UEFI?
Thanks!

Best Regards,
Wei

> +			#interrupt-cells = <1>;
> +			interrupt-map-mask = <0xf800 0 0 7>;
> +			interrupt-map = <0x0 0 0 1 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 2 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 3 &mbigen_pcie2_a 671 4
> +					 0x0 0 0 4 &mbigen_pcie2_a 671 4>;
> +			status = "disabled";
> +		};
>  	};
>  };
> 

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html

  reply	other threads:[~2017-08-04 13:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-18  8:33 [PATCH] arm64: dts: hisi: add PCIe host controller node for hip07 SoC Zhou Wang
2017-07-18  8:33 ` Zhou Wang
2017-08-04 13:01 ` Wei Xu [this message]
2017-08-04 13:01   ` Wei Xu
2017-08-07  0:59   ` Zhou Wang
2017-08-07  0:59     ` Zhou Wang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=5984703A.4060302@hisilicon.com \
    --to=xuwei5@hisilicon.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.