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From: Daniel Borkmann <daniel@iogearbox.net>
To: Jiong Wang <jiong.wang@netronome.com>
Cc: xdp-newbies@vger.kernel.org, llvm-dev@lists.llvm.org,
	iovisor-dev@lists.iovisor.org, oss-drivers@netronome.com,
	ys114321@gmail.com
Subject: Re: [PATCH RFC 0/4] Initial 32-bit eBPF encoding support
Date: Mon, 18 Sep 2017 23:29:41 +0200	[thread overview]
Message-ID: <59C03AC5.3080109@iogearbox.net> (raw)
In-Reply-To: <1505767641-40512-1-git-send-email-jiong.wang@netronome.com>

On 09/18/2017 10:47 PM, Jiong Wang wrote:
> Hi,
>
>    Currently, LLVM eBPF backend always generate code in 64-bit mode, this may
> cause troubles when JITing to 32-bit targets.
>
>    For example, it is quite common for XDP eBPF program to access some packet
> fields through base + offset that the default eBPF will generate BPF_ALU64 for
> the address formation, later when JITing to 32-bit hardware, BPF_ALU64 needs
> to be expanded into 32 bit ALU sequences even though the address space is
> 32-bit that the high bits is not significant.
>
>    While a complete 32-bit mode implemention may need an new ABI (something like
> -target-abi=ilp32), this patch set first add some initial code so we could
> construct 32-bit eBPF tests through hand-written assembly.
>
>    A new 32-bit register set is introduced, its name is with "w" prefix and LLVM
> assembler will encode statements like "w1 += w2" into the following 8-bit code
> field:
>
>      BPF_ADD | BPF_X | BPF_ALU
>
> BPF_ALU will be used instead of BPF_ALU64.
>
>    NOTE, currently you can only use "w" register with ALU statements, not with
> others like branches etc as they don't have different encoding for 32-bit
> target.

Great to see work in this direction! Can we also enable to use / emit
all the 32bit BPF_ALU instructions whenever possible for the currently
available bpf targets while at it (which only use BPF_ALU64 right now)?

Thanks,
Daniel

> *** BLURB HERE ***
>
> Jiong Wang (4):
>    Improve instruction encoding descriptions
>    Improve class inheritance in instruction patterns
>    New 32-bit register set
>    Initial 32-bit ALU (BPF_ALU) encoding support in assembler
>
>   lib/Target/BPF/BPFInstrFormats.td               |  84 +++-
>   lib/Target/BPF/BPFInstrInfo.td                  | 506 +++++++++++-------------
>   lib/Target/BPF/BPFRegisterInfo.td               |  74 +++-
>   lib/Target/BPF/Disassembler/BPFDisassembler.cpp |  15 +
>   test/MC/BPF/insn-unit-32.s                      |  53 +++
>   5 files changed, 427 insertions(+), 305 deletions(-)
>   create mode 100644 test/MC/BPF/insn-unit-32.s
>

  parent reply	other threads:[~2017-09-18 21:29 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-09-18 20:47 [PATCH RFC 0/4] Initial 32-bit eBPF encoding support Jiong Wang
2017-09-18 20:47 ` [PATCH RFC 1/4] Improve instruction encoding descriptions Jiong Wang
2017-09-18 20:47 ` [PATCH RFC 2/4] Improve class inheritance in instruction patterns Jiong Wang
2017-09-18 20:47 ` [PATCH RFC 3/4] New 32-bit register set Jiong Wang
2017-09-19  6:44   ` [iovisor-dev] " Y Song
2017-09-19 23:10     ` Jiong Wang
2017-09-22  4:55       ` Y Song
2017-09-18 20:47 ` [PATCH RFC 4/4] Initial 32-bit ALU encoding support in assembler Jiong Wang
2017-09-18 21:29 ` Daniel Borkmann [this message]
2017-09-19 23:20   ` [PATCH RFC 0/4] Initial 32-bit eBPF encoding support Jiong Wang
2017-09-19 23:24     ` Daniel Borkmann
2017-09-21 18:56     ` [iovisor-dev] " Alexei Starovoitov
2017-09-21 19:36       ` Daniel Borkmann
2017-09-22 16:24       ` [oss-drivers] " Jakub Kicinski
2017-09-23  5:03         ` Yonghong Song
2017-09-23  8:41           ` Jakub Kicinski
2017-09-23 14:42             ` Y Song
2017-09-24  5:46             ` Alexei Starovoitov
2017-09-19  4:49 ` Fulvio Risso
2017-09-19 22:56   ` Jiong Wang

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