[PATCH v2 0/6] Power domains support for Exynos5433 SoCs

[PATCH v2 0/6] Power domains support for Exynos5433 SoCs

[Marek Szyprowski]

Hello,

This patchset is a final step to add support for all power domains
in Exynos5433 SoCs. This patchset contains patches which add definitions
of the power domains found in Exynos5433 SoCs. Finally all the
dependencies has been merged to v4.15-rc1, so the domains can be
instantiated in exynos5433.dtsi.

Patches have been generated on top of Linux v4.15-rc1.

Best regards
Marek Szyprowski
Samsung R&D Institute Poland

Changelog:

v2:
- dropped exynos-pd patch, which has been already merged
- dropped FSYS power domain patch until the issues with SD card mode
  switch failure gets resolved

v1: https://www.spinics.net/lists/linux-samsung-soc/msg57719.html
- initial version


Patch summary:

Marek Szyprowski (6):
  arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
  arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 114 +++++++++++++++++++++++++++++
 1 file changed, 114 insertions(+)

-- 
2.15.0

[PATCH v2 1/6] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, three GSCL video scalers and
their SYSMMUs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 9484d2f867dc..2a03be0c9ae7 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -443,6 +443,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_GSCL_111>,
 				<&cmu_top CLK_ACLK_GSCL_333>;
+			power-domains = <&pd_gscl>;
 		};
 
 		cmu_apollo: clock-controller@11900000 {
@@ -543,6 +544,13 @@
 				<&cmu_top CLK_ACLK_CAM1_552>;
 		};
 
+		pd_gscl: power-domain@105c4000 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4000 0x20>;
+			#power-domain-cells = <0>;
+			label = "GSCL";
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -910,6 +918,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		gsc_1: video-scaler@13C10000 {
@@ -923,6 +932,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl1>;
+			power-domains = <&pd_gscl>;
 		};
 
 		gsc_2: video-scaler@13C20000 {
@@ -936,6 +946,7 @@
 				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
 				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
 			iommus = <&sysmmu_gscl2>;
+			power-domains = <&pd_gscl>;
 		};
 
 		jpeg: codec@15020000 {
@@ -1010,6 +1021,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_gscl1: sysmmu@13c90000 {
@@ -1020,6 +1032,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_gscl2: sysmmu@13ca0000 {
@@ -1030,6 +1043,7 @@
 			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
 				 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_gscl>;
 		};
 
 		sysmmu_jpeg: sysmmu@15060000 {
-- 
2.15.0

Re: [PATCH v2 1/6] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, three GSCL video scalers and
> their SYSMMUs.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 9484d2f867dc..2a03be0c9ae7 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -443,6 +443,7 @@
>  			clocks = <&xxti>,
>  				<&cmu_top CLK_ACLK_GSCL_111>,
>  				<&cmu_top CLK_ACLK_GSCL_333>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		cmu_apollo: clock-controller@11900000 {
> @@ -543,6 +544,13 @@
>  				<&cmu_top CLK_ACLK_CAM1_552>;
>  		};
>  
> +		pd_gscl: power-domain@105c4000 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c4000 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "GSCL";
> +		};
> +
>  		tmu_atlas0: tmu@10060000 {
>  			compatible = "samsung,exynos5433-tmu";
>  			reg = <0x10060000 0x200>;
> @@ -910,6 +918,7 @@
>  				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
>  				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
>  			iommus = <&sysmmu_gscl0>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		gsc_1: video-scaler@13C10000 {
> @@ -923,6 +932,7 @@
>  				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
>  				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
>  			iommus = <&sysmmu_gscl1>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		gsc_2: video-scaler@13C20000 {
> @@ -936,6 +946,7 @@
>  				 <&cmu_gscl CLK_ACLK_XIU_GSCLX>,
>  				 <&cmu_gscl CLK_ACLK_GSCLBEND_333>;
>  			iommus = <&sysmmu_gscl2>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		jpeg: codec@15020000 {
> @@ -1010,6 +1021,7 @@
>  			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
>  				 <&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
>  			#iommu-cells = <0>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		sysmmu_gscl1: sysmmu@13c90000 {
> @@ -1020,6 +1032,7 @@
>  			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
>  				 <&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
>  			#iommu-cells = <0>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		sysmmu_gscl2: sysmmu@13ca0000 {
> @@ -1030,6 +1043,7 @@
>  			clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
>  				 <&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
>  			#iommu-cells = <0>;
> +			power-domains = <&pd_gscl>;
>  		};
>  
>  		sysmmu_jpeg: sysmmu@15060000 {
> 

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 1/6] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:33PM +0100, Marek Szyprowski wrote:
> This patch adds support for GSCL power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, three GSCL video scalers and
> their SYSMMUs.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[PATCH v2 2/6] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for DISP power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, two display controllers
(DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices.

OCSigned-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 2a03be0c9ae7..95f30ccc00a3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -386,6 +386,7 @@
 				<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 				<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 				<&cmu_mif CLK_ACLK_DISP_333>;
+			power-domains = <&pd_disp>;
 		};
 
 		cmu_aud: clock-controller@114c0000 {
@@ -551,6 +552,13 @@
 			label = "GSCL";
 		};
 
+		pd_disp: power-domain@105c4080 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4080 0x20>;
+			#power-domain-cells = <0>;
+			label = "DISP";
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -754,6 +762,7 @@
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				"aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				"sclk_decon_vclk", "sclk_decon_eclk";
+			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
@@ -791,6 +800,7 @@
 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
 				      "sclk_decon_vclk", "sclk_decon_eclk";
 			samsung,disp-sysreg = <&syscon_disp>;
+			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
@@ -816,6 +826,7 @@
 					"phyclk_mipidphy0_rxclkesc0",
 					"sclk_rgb_vclk_to_dsim0",
 					"sclk_mipi";
+			power-domains = <&pd_disp>;
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -839,6 +850,7 @@
 			clocks = <&cmu_disp CLK_PCLK_MIC0>,
 				<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
 			clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
+			power-domains = <&pd_disp>;
 			samsung,disp-syscon = <&syscon_disp>;
 			status = "disabled";
 
@@ -980,6 +992,7 @@
 			clock-names = "pclk", "aclk";
 			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
 				<&cmu_disp CLK_ACLK_SMMU_DECON0X>;
+			power-domains = <&pd_disp>;
 			#iommu-cells = <0>;
 		};
 
@@ -991,6 +1004,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 				<&cmu_disp CLK_ACLK_SMMU_DECON1X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_tv0x: sysmmu@13a20000 {
@@ -1001,6 +1015,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
 				<&cmu_disp CLK_ACLK_SMMU_TV0X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_tv1x: sysmmu@13a30000 {
@@ -1011,6 +1026,7 @@
 			clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
 				<&cmu_disp CLK_ACLK_SMMU_TV1X>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_disp>;
 		};
 
 		sysmmu_gscl0: sysmmu@13c80000 {
-- 
2.15.0

Re: [PATCH v2 2/6] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for DISP power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, two display controllers
> (DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices.
> 
> OCSigned-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

[snip]

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 2/6] arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:34PM +0100, Marek Szyprowski wrote:
> This patch adds support for DISP power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, two display controllers
> (DECON and DECON TV), their SYSMMUs, MIC, DSI and HDMI video devices.
> 
> OCSigned-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 16 ++++++++++++++++
>  1 file changed, 16 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, JPEG codec device and its
SYSMMU.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 95f30ccc00a3..0a06be283a31 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -476,6 +476,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_SCLK_JPEG_MSCL>,
 				<&cmu_top CLK_ACLK_MSCL_400>;
+			power-domains = <&pd_mscl>;
 		};
 
 		cmu_mfc: clock-controller@15280000 {
@@ -552,6 +553,13 @@
 			label = "GSCL";
 		};
 
+		pd_mscl: power-domain@105c4040 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4040 0x20>;
+			#power-domain-cells = <0>;
+			label = "MSCL";
+		};
+
 		pd_disp: power-domain@105c4080 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4080 0x20>;
@@ -971,6 +979,7 @@
 				 <&cmu_mscl CLK_ACLK_XIU_MSCLX>,
 				 <&cmu_mscl CLK_SCLK_JPEG>;
 			iommus = <&sysmmu_jpeg>;
+			power-domains = <&pd_mscl>;
 		};
 
 		mfc: codec@152E0000 {
@@ -1070,6 +1079,7 @@
 			clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
 				 <&cmu_mscl CLK_ACLK_SMMU_JPEG>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mscl>;
 		};
 
 		sysmmu_mfc_0: sysmmu@15200000 {
-- 
2.15.0

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Chanwoo Choi]

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, JPEG codec device and its
> SYSMMU.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

[snip]

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 30일 11:20, Chanwoo Choi wrote:
> On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
>> This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
>> contains following devices: a clock controller, JPEG codec device and its
>> SYSMMU.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>>  1 file changed, 10 insertions(+)
> 
> Looks good to me.
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> 
> [snip]
> 

When I tested this patch with enabling exynos-bus.c,
I got the following external abort. In order to fix this abort,
I add the power-domain property to arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
as following:

[Adding power-domain to bus device-tree node]
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
index ec11343dc528..0e1a7e01b8ed 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
@@ -47,6 +47,7 @@
                clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
                clock-names = "bus";
                operating-points-v2 = <&bus_g2d_400_opp_table>;
+               power-domains = <&pd_mscl>;
                status = "disabled";
        };
 
@@ -55,6 +56,7 @@
                clocks = <&cmu_top CLK_ACLK_MFC_400>;
                clock-names = "bus";
                operating-points-v2 = <&bus_g2d_400_opp_table>;
+               power-domains = <&pd_mfc>;
                status = "disabled";
        };
 
@@ -63,6 +65,7 @@
                clocks = <&cmu_top CLK_ACLK_MSCL_400>;
                clock-names = "bus";
                operating-points-v2 = <&bus_g2d_400_opp_table>;
+               power-domains = <&pd_mscl>;
                status = "disabled";
        }; 

[Abort message]
    5.314836] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
[    5.314883] exynos5433-cmu 15280000.clock-controller: resume latency exceeded, 26291 ns
[    5.314909] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
[    5.314949] exynos5433-cmu 15280000.clock-controller: suspend latency exceeded, 24334 ns
[    5.314989] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
[    5.315034] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
[    5.315109] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
[    5.315157] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
[    5.315200] exynos5433-cmu 15280000.clock-controller: suspend latency exceeded, 27458 ns
[    5.315252] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_resume()
[    5.315509] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_suspend()
[    5.315783] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_resume()
[    5.316027] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_suspend()
[    5.316295] Synchronous External Abort: synchronous external abort (0x96000210) at 0xffffff80093f5600
[    5.316308] Internal error: : 96000210 [#1] PREEMPT SMP
[    5.316317] Modules linked in:
[    5.316336] CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.15.0-rc1-next-20171129+ #4
[    5.316342] Hardware name: Samsung TM2 board (DT)
[    5.316364] Workqueue: devfreq_wq devfreq_monitor
[    5.316377] task: ffffffc0ca96b600 task.stack: ffffff80093a8000
[    5.316388] pstate: a0000085 (NzCv daIf -PAN -UAO)
[    5.316405] pc : clk_divider_set_rate+0x54/0x118
[    5.316417] lr : clk_divider_set_rate+0x44/0x118
[    5.316422] sp : ffffff80093aba00
[    5.316428] x29: ffffff80093aba00 x28: ffffffc0ca820080 
[    5.316445] x27: ffffffc0ca820030 x26: 0000000000000000 
[    5.316459] x25: 0000000005f5e100 x24: 0000000005f5e100 
[    5.316474] x23: ffffffc0ca213a00 x22: 00000000017d7840 
[    5.316488] x21: 0000000000000000 x20: 0000000000000003 
[    5.316503] x19: ffffffc0ca203380 x18: 0000000000000000 
[    5.316517] x17: ffffffffffffffff x16: 00000000ffffffff 
[    5.316532] x15: 00000000000c8dae x14: 28646e6570737573 
[    5.316547] x13: 5f656d69746e7572 x12: 5f64706e6567203a 
[    5.316562] x11: 72656c6c6f72746e x10: 0000000000000980 
[    5.316576] x9 : ffffff80093ab6b0 x8 : ffffffc0ca96bfe0 
[    5.316590] x7 : 0000000000000004 x6 : 003c14dc022e9800 
[    5.316604] x5 : 0000000000000003 x4 : ffffff80093ac000 
[    5.316619] x3 : ffffff80093f5600 x2 : 0000000000000000 
[    5.316633] x1 : 0000000000000000 x0 : 0000000000000000 
[    5.316650] Process kworker/u16:0 (pid: 5, stack limit = 0xffffff80093a8000)
[    5.316655] Call trace:
[    5.316668]  clk_divider_set_rate+0x54/0x118
[    5.316680]  clk_change_rate+0xfc/0x4e0
[    5.316691]  clk_change_rate+0x1f0/0x4e0
[    5.316701]  clk_change_rate+0x1f0/0x4e0
[    5.316712]  clk_change_rate+0x1f0/0x4e0
[    5.316723]  clk_core_set_rate_nolock+0x138/0x148
[    5.316733]  clk_set_rate+0x28/0x50
[    5.316746]  exynos_bus_passive_target+0x6c/0x11c
[    5.316758]  update_devfreq_passive+0x58/0xb4
[    5.316769]  devfreq_passive_notifier_call+0x50/0x5c
[    5.316780]  notifier_call_chain+0x4c/0x88
[    5.316790]  __srcu_notifier_call_chain+0x54/0x80
[    5.316800]  srcu_notifier_call_chain+0x14/0x1c
[    5.316811]  update_devfreq+0x100/0x1b4
[    5.316821]  devfreq_monitor+0x2c/0x88
[    5.316833]  process_one_work+0x148/0x3d8
[    5.316843]  worker_thread+0x13c/0x3f8
[    5.316855]  kthread+0x100/0x12c
[    5.316867]  ret_from_fork+0x10/0x18

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

Dear Chanwoo,

On 2017-11-30 03:51, Chanwoo Choi wrote:
> On 2017년 11월 30일 11:20, Chanwoo Choi wrote:
>> On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
>>> This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
>>> contains following devices: a clock controller, JPEG codec device and its
>>> SYSMMU.
>>>
>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>> ---
>>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>>>   1 file changed, 10 insertions(+)
>> Looks good to me.
>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>>
>> [snip]
>>
> When I tested this patch with enabling exynos-bus.c,
> I got the following external abort. In order to fix this abort,
> I add the power-domain property to arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
> as following:

Thanks for this report. You are right that exynos-bus devices should be
also added to respective power domains. I will also check how to add
runtime PM support and awareness of power domain to exynos-bus driver,
to avoid blocking respective power domains in turned on state.

> [Adding power-domain to bus device-tree node]
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
> index ec11343dc528..0e1a7e01b8ed 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
> @@ -47,6 +47,7 @@
>                  clocks = <&cmu_top CLK_SCLK_JPEG_MSCL>;
>                  clock-names = "bus";
>                  operating-points-v2 = <&bus_g2d_400_opp_table>;
> +               power-domains = <&pd_mscl>;
>                  status = "disabled";
>          };
>   
> @@ -55,6 +56,7 @@
>                  clocks = <&cmu_top CLK_ACLK_MFC_400>;
>                  clock-names = "bus";
>                  operating-points-v2 = <&bus_g2d_400_opp_table>;
> +               power-domains = <&pd_mfc>;
>                  status = "disabled";
>          };
>   
> @@ -63,6 +65,7 @@
>                  clocks = <&cmu_top CLK_ACLK_MSCL_400>;
>                  clock-names = "bus";
>                  operating-points-v2 = <&bus_g2d_400_opp_table>;
> +               power-domains = <&pd_mscl>;
>                  status = "disabled";
>          };
>
> [Abort message]
>      5.314836] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
> [    5.314883] exynos5433-cmu 15280000.clock-controller: resume latency exceeded, 26291 ns
> [    5.314909] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
> [    5.314949] exynos5433-cmu 15280000.clock-controller: suspend latency exceeded, 24334 ns
> [    5.314989] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
> [    5.315034] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
> [    5.315109] exynos5433-cmu 15280000.clock-controller: genpd_runtime_resume()
> [    5.315157] exynos5433-cmu 15280000.clock-controller: genpd_runtime_suspend()
> [    5.315200] exynos5433-cmu 15280000.clock-controller: suspend latency exceeded, 27458 ns
> [    5.315252] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_resume()
> [    5.315509] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_suspend()
> [    5.315783] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_resume()
> [    5.316027] exynos5433-cmu 150d0000.clock-controller: genpd_runtime_suspend()
> [    5.316295] Synchronous External Abort: synchronous external abort (0x96000210) at 0xffffff80093f5600
> [    5.316308] Internal error: : 96000210 [#1] PREEMPT SMP
> [    5.316317] Modules linked in:
> [    5.316336] CPU: 0 PID: 5 Comm: kworker/u16:0 Not tainted 4.15.0-rc1-next-20171129+ #4
> [    5.316342] Hardware name: Samsung TM2 board (DT)
> [    5.316364] Workqueue: devfreq_wq devfreq_monitor
> [    5.316377] task: ffffffc0ca96b600 task.stack: ffffff80093a8000
> [    5.316388] pstate: a0000085 (NzCv daIf -PAN -UAO)
> [    5.316405] pc : clk_divider_set_rate+0x54/0x118
> [    5.316417] lr : clk_divider_set_rate+0x44/0x118
> [    5.316422] sp : ffffff80093aba00
> [    5.316428] x29: ffffff80093aba00 x28: ffffffc0ca820080
> [    5.316445] x27: ffffffc0ca820030 x26: 0000000000000000
> [    5.316459] x25: 0000000005f5e100 x24: 0000000005f5e100
> [    5.316474] x23: ffffffc0ca213a00 x22: 00000000017d7840
> [    5.316488] x21: 0000000000000000 x20: 0000000000000003
> [    5.316503] x19: ffffffc0ca203380 x18: 0000000000000000
> [    5.316517] x17: ffffffffffffffff x16: 00000000ffffffff
> [    5.316532] x15: 00000000000c8dae x14: 28646e6570737573
> [    5.316547] x13: 5f656d69746e7572 x12: 5f64706e6567203a
> [    5.316562] x11: 72656c6c6f72746e x10: 0000000000000980
> [    5.316576] x9 : ffffff80093ab6b0 x8 : ffffffc0ca96bfe0
> [    5.316590] x7 : 0000000000000004 x6 : 003c14dc022e9800
> [    5.316604] x5 : 0000000000000003 x4 : ffffff80093ac000
> [    5.316619] x3 : ffffff80093f5600 x2 : 0000000000000000
> [    5.316633] x1 : 0000000000000000 x0 : 0000000000000000
> [    5.316650] Process kworker/u16:0 (pid: 5, stack limit = 0xffffff80093a8000)
> [    5.316655] Call trace:
> [    5.316668]  clk_divider_set_rate+0x54/0x118
> [    5.316680]  clk_change_rate+0xfc/0x4e0
> [    5.316691]  clk_change_rate+0x1f0/0x4e0
> [    5.316701]  clk_change_rate+0x1f0/0x4e0
> [    5.316712]  clk_change_rate+0x1f0/0x4e0
> [    5.316723]  clk_core_set_rate_nolock+0x138/0x148
> [    5.316733]  clk_set_rate+0x28/0x50
> [    5.316746]  exynos_bus_passive_target+0x6c/0x11c
> [    5.316758]  update_devfreq_passive+0x58/0xb4
> [    5.316769]  devfreq_passive_notifier_call+0x50/0x5c
> [    5.316780]  notifier_call_chain+0x4c/0x88
> [    5.316790]  __srcu_notifier_call_chain+0x54/0x80
> [    5.316800]  srcu_notifier_call_chain+0x14/0x1c
> [    5.316811]  update_devfreq+0x100/0x1b4
> [    5.316821]  devfreq_monitor+0x2c/0x88
> [    5.316833]  process_one_work+0x148/0x3d8
> [    5.316843]  worker_thread+0x13c/0x3f8
> [    5.316855]  kthread+0x100/0x12c
> [    5.316867]  ret_from_fork+0x10/0x18
>

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Marek Szyprowski]

Dear Chanwoo,

On 2017-11-30 10:35, Marek Szyprowski wrote:
> On 2017-11-30 03:51, Chanwoo Choi wrote:
>> On 2017년 11월 30일 11:20, Chanwoo Choi wrote:
>>> On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
>>>> This patch adds support for MSCL power domain to Exynos 5433 SoCs, 
>>>> which
>>>> contains following devices: a clock controller, JPEG codec device 
>>>> and its
>>>> SYSMMU.
>>>>
>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>> ---
>>>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>>>>   1 file changed, 10 insertions(+)
>>> Looks good to me.
>>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>
>>> [snip]
>>>
>> When I tested this patch with enabling exynos-bus.c,
>> I got the following external abort. In order to fix this abort,
>> I add the power-domain property to 
>> arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
>> as following:
>
> Thanks for this report. You are right that exynos-bus devices should be
> also added to respective power domains. I will also check how to add
> runtime PM support and awareness of power domain to exynos-bus driver,
> to avoid blocking respective power domains in turned on state.

I've investigated it further and it turned out to be a missing case in
my runtime PM patch for clocks core.

In this case exynos-bus operates on a clock, which is in the
TOP CMU and TOP power domain (always on), which has no relation with
the newly added MSCL power domain. We should not mix this by forcing
exynos-bus to be in the MSCL domain.

The reported external abort is solved by proper patch for clock core:
https://patchwork.kernel.org/patch/10084725/

This patch (and the other patches from this patch series) can be applied
without any changes.

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 30일 21:21, Marek Szyprowski wrote:
> Dear Chanwoo,
> 
> On 2017-11-30 10:35, Marek Szyprowski wrote:
>> On 2017-11-30 03:51, Chanwoo Choi wrote:
>>> On 2017년 11월 30일 11:20, Chanwoo Choi wrote:
>>>> On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
>>>>> This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
>>>>> contains following devices: a clock controller, JPEG codec device and its
>>>>> SYSMMU.
>>>>>
>>>>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>>>>> ---
>>>>>   arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>>>>>   1 file changed, 10 insertions(+)
>>>> Looks good to me.
>>>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>>>>
>>>> [snip]
>>>>
>>> When I tested this patch with enabling exynos-bus.c,
>>> I got the following external abort. In order to fix this abort,
>>> I add the power-domain property to arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
>>> as following:
>>
>> Thanks for this report. You are right that exynos-bus devices should be
>> also added to respective power domains. I will also check how to add
>> runtime PM support and awareness of power domain to exynos-bus driver,
>> to avoid blocking respective power domains in turned on state.
> 
> I've investigated it further and it turned out to be a missing case in
> my runtime PM patch for clocks core.
> 
> In this case exynos-bus operates on a clock, which is in the
> TOP CMU and TOP power domain (always on), which has no relation with
> the newly added MSCL power domain. We should not mix this by forcing
> exynos-bus to be in the MSCL domain.
> 
> The reported external abort is solved by proper patch for clock core:
> https://patchwork.kernel.org/patch/10084725/
> 
> This patch (and the other patches from this patch series) can be applied
> without any changes.

I tested it with your clk patch. It is well working. Thanks.

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 3/6] arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:35PM +0100, Marek Szyprowski wrote:
> This patch adds support for MSCL power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, JPEG codec device and its
> SYSMMU.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[PATCH v2 4/6] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

[Marek Szyprowski]

This patch adds support for MFC power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, MFC codec device and its
SYSMMUs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0a06be283a31..cfa2a0d4dc2f 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -486,6 +486,7 @@
 
 			clock-names = "oscclk", "aclk_mfc_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+			power-domains = <&pd_mfc>;
 		};
 
 		cmu_hevc: clock-controller@14f80000 {
@@ -567,6 +568,13 @@
 			label = "DISP";
 		};
 
+		pd_mfc: power-domain@105c4180 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4180 0x20>;
+			#power-domain-cells = <0>;
+			label = "MFC";
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -992,6 +1000,7 @@
 				 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
 			iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
 			iommu-names = "left", "right";
+			power-domains = <&pd_mfc>;
 		};
 
 		sysmmu_decon0x: sysmmu@13a00000 {
@@ -1090,6 +1099,7 @@
 			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
 				 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mfc>;
 		};
 
 		sysmmu_mfc_1: sysmmu@15210000 {
@@ -1100,6 +1110,7 @@
 			clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
 				 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
 			#iommu-cells = <0>;
+			power-domains = <&pd_mfc>;
 		};
 
 		serial_0: serial@14c10000 {
-- 
2.15.0

Re: [PATCH v2 4/6] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for MFC power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, MFC codec device and its
> SYSMMUs.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 0a06be283a31..cfa2a0d4dc2f 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -486,6 +486,7 @@

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

[snip]

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 4/6] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 30일 11:21, Chanwoo Choi wrote:
> Dear Marek,
> 
> On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
>> This patch adds support for MFC power domain to Exynos 5433 SoCs, which
>> contains following devices: a clock controller, MFC codec device and its
>> SYSMMUs.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
>>  1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> index 0a06be283a31..cfa2a0d4dc2f 100644
>> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
>> @@ -486,6 +486,7 @@
> 
> Looks good to me.
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> 
> [snip]
> 

As I commented on patch3, when adding the MFC power domain,
you need to add the 'power-domain' property for  'bus_mfc' device-tree node
as following:

[Adding power-domain to bus device-tree node]
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
index ec11343dc528..0e1a7e01b8ed 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi
 
@@ -55,6 +56,7 @@
                clocks = <&cmu_top CLK_ACLK_MFC_400>;
                clock-names = "bus";
                operating-points-v2 = <&bus_g2d_400_opp_table>;
+               power-domains = <&pd_mfc>;
                status = "disabled";
        };


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 4/6] arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:36PM +0100, Marek Szyprowski wrote:
> This patch adds support for MFC power domain to Exynos 5433 SoCs, which
> contains following devices: a clock controller, MFC codec device and its
> SYSMMUs.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[PATCH v2 5/6] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC

[Marek Szyprowski]

This patch adds support for AUD power domain to Exynos5433 SoCs, which
contains following devices: a clock controller, a pin controller, LPASS
module, I2S controller, ADMA PL330 engine and UART #3 device.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index cfa2a0d4dc2f..2c019a0fd8e3 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -395,6 +395,7 @@
 			#clock-cells = <1>;
 			clock-names = "oscclk", "fout_aud_pll";
 			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
+			power-domains = <&pd_aud>;
 		};
 
 		cmu_bus0: clock-controller@13600000 {
@@ -568,6 +569,13 @@
 			label = "DISP";
 		};
 
+		pd_aud: power-domain@105c40c0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40c0 0x20>;
+			#power-domain-cells = <0>;
+			label = "AUD";
+		};
+
 		pd_mfc: power-domain@105c4180 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4180 0x20>;
@@ -687,6 +695,7 @@
 			compatible = "samsung,exynos5433-pinctrl";
 			reg = <0x114b0000 0x1000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_aud>;
 		};
 
 		pinctrl_cpif: pinctrl@10fe0000 {
@@ -1566,6 +1575,7 @@
 			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
 			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
+			power-domains = <&pd_aud>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1579,6 +1589,7 @@
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				power-domains = <&pd_aud>;
 			};
 
 			i2s0: i2s0@11440000 {
@@ -1595,6 +1606,7 @@
 				clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2s0_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 
@@ -1607,6 +1619,7 @@
 				clock-names = "uart", "clk_uart_baud0";
 				pinctrl-names = "default";
 				pinctrl-0 = <&uart_aud_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 		};
-- 
2.15.0

Re: [PATCH v2 5/6] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for AUD power domain to Exynos5433 SoCs, which
> contains following devices: a clock controller, a pin controller, LPASS
> module, I2S controller, ADMA PL330 engine and UART #3 device.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index cfa2a0d4dc2f..2c019a0fd8e3 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -395,6 +395,7 @@
>  			#clock-cells = <1>;
>  			clock-names = "oscclk", "fout_aud_pll";
>  			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
> +			power-domains = <&pd_aud>;
>  		};
>  
>  		cmu_bus0: clock-controller@13600000 {
> @@ -568,6 +569,13 @@
>  			label = "DISP";
>  		};
>  
> +		pd_aud: power-domain@105c40c0 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c40c0 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "AUD";
> +		};
> +
>  		pd_mfc: power-domain@105c4180 {
>  			compatible = "samsung,exynos5433-pd";
>  			reg = <0x105c4180 0x20>;
> @@ -687,6 +695,7 @@
>  			compatible = "samsung,exynos5433-pinctrl";
>  			reg = <0x114b0000 0x1000>;
>  			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
> +			power-domains = <&pd_aud>;
>  		};
>  
>  		pinctrl_cpif: pinctrl@10fe0000 {
> @@ -1566,6 +1575,7 @@
>  			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
>  			clock-names = "sfr0_ctrl";
>  			samsung,pmu-syscon = <&pmu_system_controller>;
> +			power-domains = <&pd_aud>;
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			ranges;
> @@ -1579,6 +1589,7 @@
>  				#dma-cells = <1>;
>  				#dma-channels = <8>;
>  				#dma-requests = <32>;
> +				power-domains = <&pd_aud>;
>  			};
>  
>  			i2s0: i2s0@11440000 {
> @@ -1595,6 +1606,7 @@
>  				clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&i2s0_bus>;
> +				power-domains = <&pd_aud>;
>  				status = "disabled";
>  			};
>  
> @@ -1607,6 +1619,7 @@
>  				clock-names = "uart", "clk_uart_baud0";
>  				pinctrl-names = "default";
>  				pinctrl-0 = <&uart_aud_bus>;
> +				power-domains = <&pd_aud>;
>  				status = "disabled";
>  			};
>  		};
> 

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 5/6] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:37PM +0100, Marek Szyprowski wrote:
> This patch adds support for AUD power domain to Exynos5433 SoCs, which
> contains following devices: a clock controller, a pin controller, LPASS
> module, I2S controller, ADMA PL330 engine and UART #3 device.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof

[PATCH v2 6/6] arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

[Marek Szyprowski]

This patch adds support for G2D, G3D, CAM0, CAM1, ISP, HVEC power domains
to Exynos5433 SoCs. Currently only clock controllers for those domains are
defined. CAM1 is a parent of CAM0 power domain and CAM0 is a parent of ISP
power domain.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 50 ++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 2c019a0fd8e3..1962b8074349 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -361,6 +361,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_G2D_266>,
 				<&cmu_top CLK_ACLK_G2D_400>;
+			power-domains = <&pd_g2d>;
 		};
 
 		cmu_disp: clock-controller@13b90000 {
@@ -432,6 +433,7 @@
 
 			clock-names = "oscclk", "aclk_g3d_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
+			power-domains = <&pd_g3d>;
 		};
 
 		cmu_gscl: clock-controller@13cf0000 {
@@ -497,6 +499,7 @@
 
 			clock-names = "oscclk", "aclk_hevc_400";
 			clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
+			power-domains = <&pd_hevc>;
 		};
 
 		cmu_isp: clock-controller@146d0000 {
@@ -510,6 +513,7 @@
 			clocks = <&xxti>,
 				<&cmu_top CLK_ACLK_ISP_DIS_400>,
 				<&cmu_top CLK_ACLK_ISP_400>;
+			power-domains = <&pd_isp>;
 		};
 
 		cmu_cam0: clock-controller@120d0000 {
@@ -525,6 +529,7 @@
 				<&cmu_top CLK_ACLK_CAM0_333>,
 				<&cmu_top CLK_ACLK_CAM0_400>,
 				<&cmu_top CLK_ACLK_CAM0_552>;
+			power-domains = <&pd_cam0>;
 		};
 
 		cmu_cam1: clock-controller@145d0000 {
@@ -546,6 +551,7 @@
 				<&cmu_top CLK_ACLK_CAM1_333>,
 				<&cmu_top CLK_ACLK_CAM1_400>,
 				<&cmu_top CLK_ACLK_CAM1_552>;
+			power-domains = <&pd_cam1>;
 		};
 
 		pd_gscl: power-domain@105c4000 {
@@ -555,6 +561,14 @@
 			label = "GSCL";
 		};
 
+		pd_cam0: power-domain@105c4020 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4020 0x20>;
+			#power-domain-cells = <0>;
+			power-domains = <&pd_cam1>;
+			label = "CAM0";
+		};
+
 		pd_mscl: power-domain@105c4040 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4040 0x20>;
@@ -562,6 +576,13 @@
 			label = "MSCL";
 		};
 
+		pd_g3d: power-domain@105c4060 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4060 0x20>;
+			#power-domain-cells = <0>;
+			label = "G3D";
+		};
+
 		pd_disp: power-domain@105c4080 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4080 0x20>;
@@ -569,6 +590,13 @@
 			label = "DISP";
 		};
 
+		pd_cam1: power-domain@105c40a0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40a0 0x20>;
+			#power-domain-cells = <0>;
+			label = "CAM1";
+		};
+
 		pd_aud: power-domain@105c40c0 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c40c0 0x20>;
@@ -576,6 +604,21 @@
 			label = "AUD";
 		};
 
+		pd_g2d: power-domain@105c4120 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4120 0x20>;
+			#power-domain-cells = <0>;
+			label = "G2D";
+		};
+
+		pd_isp: power-domain@105c4140 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c4140 0x20>;
+			#power-domain-cells = <0>;
+			power-domains = <&pd_cam0>;
+			label = "ISP";
+		};
+
 		pd_mfc: power-domain@105c4180 {
 			compatible = "samsung,exynos5433-pd";
 			reg = <0x105c4180 0x20>;
@@ -583,6 +626,13 @@
 			label = "MFC";
 		};
 
+		pd_hevc: power-domain@105c41c0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c41c0 0x20>;
+			#power-domain-cells = <0>;
+			label = "HEVC";
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
-- 
2.15.0

Re: [PATCH v2 6/6] arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

[Chanwoo Choi]

Dear Marek,

On 2017년 11월 29일 20:26, Marek Szyprowski wrote:
> This patch adds support for G2D, G3D, CAM0, CAM1, ISP, HVEC power domains
> to Exynos5433 SoCs. Currently only clock controllers for those domains are
> defined. CAM1 is a parent of CAM0 power domain and CAM0 is a parent of ISP
> power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 50 ++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> index 2c019a0fd8e3..1962b8074349 100644
> --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -361,6 +361,7 @@
>  			clocks = <&xxti>,
>  				<&cmu_top CLK_ACLK_G2D_266>,
>  				<&cmu_top CLK_ACLK_G2D_400>;
> +			power-domains = <&pd_g2d>;
>  		};
>  
>  		cmu_disp: clock-controller@13b90000 {
> @@ -432,6 +433,7 @@
>  
>  			clock-names = "oscclk", "aclk_g3d_400";
>  			clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
> +			power-domains = <&pd_g3d>;
>  		};
>  
>  		cmu_gscl: clock-controller@13cf0000 {
> @@ -497,6 +499,7 @@
>  
>  			clock-names = "oscclk", "aclk_hevc_400";
>  			clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
> +			power-domains = <&pd_hevc>;
>  		};
>  
>  		cmu_isp: clock-controller@146d0000 {
> @@ -510,6 +513,7 @@
>  			clocks = <&xxti>,
>  				<&cmu_top CLK_ACLK_ISP_DIS_400>,
>  				<&cmu_top CLK_ACLK_ISP_400>;
> +			power-domains = <&pd_isp>;
>  		};
>  
>  		cmu_cam0: clock-controller@120d0000 {
> @@ -525,6 +529,7 @@
>  				<&cmu_top CLK_ACLK_CAM0_333>,
>  				<&cmu_top CLK_ACLK_CAM0_400>,
>  				<&cmu_top CLK_ACLK_CAM0_552>;
> +			power-domains = <&pd_cam0>;
>  		};
>  
>  		cmu_cam1: clock-controller@145d0000 {
> @@ -546,6 +551,7 @@
>  				<&cmu_top CLK_ACLK_CAM1_333>,
>  				<&cmu_top CLK_ACLK_CAM1_400>,
>  				<&cmu_top CLK_ACLK_CAM1_552>;
> +			power-domains = <&pd_cam1>;
>  		};
>  
>  		pd_gscl: power-domain@105c4000 {
> @@ -555,6 +561,14 @@
>  			label = "GSCL";
>  		};
>  
> +		pd_cam0: power-domain@105c4020 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c4020 0x20>;
> +			#power-domain-cells = <0>;
> +			power-domains = <&pd_cam1>;
> +			label = "CAM0";
> +		};
> +
>  		pd_mscl: power-domain@105c4040 {
>  			compatible = "samsung,exynos5433-pd";
>  			reg = <0x105c4040 0x20>;
> @@ -562,6 +576,13 @@
>  			label = "MSCL";
>  		};
>  
> +		pd_g3d: power-domain@105c4060 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c4060 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "G3D";
> +		};
> +
>  		pd_disp: power-domain@105c4080 {
>  			compatible = "samsung,exynos5433-pd";
>  			reg = <0x105c4080 0x20>;
> @@ -569,6 +590,13 @@
>  			label = "DISP";
>  		};
>  
> +		pd_cam1: power-domain@105c40a0 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c40a0 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "CAM1";
> +		};
> +
>  		pd_aud: power-domain@105c40c0 {
>  			compatible = "samsung,exynos5433-pd";
>  			reg = <0x105c40c0 0x20>;
> @@ -576,6 +604,21 @@
>  			label = "AUD";
>  		};
>  
> +		pd_g2d: power-domain@105c4120 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c4120 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "G2D";
> +		};
> +
> +		pd_isp: power-domain@105c4140 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c4140 0x20>;
> +			#power-domain-cells = <0>;
> +			power-domains = <&pd_cam0>;
> +			label = "ISP";
> +		};
> +
>  		pd_mfc: power-domain@105c4180 {
>  			compatible = "samsung,exynos5433-pd";
>  			reg = <0x105c4180 0x20>;
> @@ -583,6 +626,13 @@
>  			label = "MFC";
>  		};
>  
> +		pd_hevc: power-domain@105c41c0 {
> +			compatible = "samsung,exynos5433-pd";
> +			reg = <0x105c41c0 0x20>;
> +			#power-domain-cells = <0>;
> +			label = "HEVC";
> +		};
> +
>  		tmu_atlas0: tmu@10060000 {
>  			compatible = "samsung,exynos5433-tmu";
>  			reg = <0x10060000 0x200>;
> 

Looks good to me.
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>


-- 
Best Regards,
Chanwoo Choi
Samsung Electronics

Re: [PATCH v2 6/6] arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

[Krzysztof Kozlowski]

On Wed, Nov 29, 2017 at 12:26:38PM +0100, Marek Szyprowski wrote:
> This patch adds support for G2D, G3D, CAM0, CAM1, ISP, HVEC power domains
> to Exynos5433 SoCs. Currently only clock controllers for those domains are
> defined. CAM1 is a parent of CAM0 power domain and CAM0 is a parent of ISP
> power domain.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 50 ++++++++++++++++++++++++++++++
>  1 file changed, 50 insertions(+)
> 

Thanks, applied.

Best regards,
Krzysztof