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From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Jonathan.Zhang@cavium.com, Marc Zyngier <marc.zyngier@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	Dongjiu Geng <gengdongjiu@huawei.com>,
	kvmarm@lists.cs.columbia.edu
Subject: Re: [PATCH v5 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA
Date: Mon, 08 Jan 2018 16:27:13 +0000	[thread overview]
Message-ID: <5A539BE1.20003@arm.com> (raw)
In-Reply-To: <20171215155101.23505-14-james.morse@arm.com>

Hi,

On 15/12/17 15:51, James Morse wrote:
> From: Dongjiu Geng <gengdongjiu@huawei.com>
> 
> ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external
> aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps
> all Non-secure EL1&0 error record accesses to EL2.
> 
> This patch enables the two bits for the guest OS, guaranteeing that
> KVM takes external aborts and traps attempts to access the physical
> error registers.
> 
> ERRIDR_EL1 advertises the number of error records, we return
> zero meaning we can treat all the other registers as RAZ/WI too.
> 
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> [removed specific emulation, use trap_raz_wi() directly for everything,
>  rephrased parts of the commit message]
> Signed-off-by: James Morse <james.morse@arm.com>

v4 of this patch had a Reviewed-by Marc and Christoffer, which I didn't pick up
because I'm an idiot:

https://patchwork.kernel.org/patch/10017537/


Thanks,

James

WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA
Date: Mon, 08 Jan 2018 16:27:13 +0000	[thread overview]
Message-ID: <5A539BE1.20003@arm.com> (raw)
In-Reply-To: <20171215155101.23505-14-james.morse@arm.com>

Hi,

On 15/12/17 15:51, James Morse wrote:
> From: Dongjiu Geng <gengdongjiu@huawei.com>
> 
> ARMv8.2 adds a new bit HCR_EL2.TEA which routes synchronous external
> aborts to EL2, and adds a trap control bit HCR_EL2.TERR which traps
> all Non-secure EL1&0 error record accesses to EL2.
> 
> This patch enables the two bits for the guest OS, guaranteeing that
> KVM takes external aborts and traps attempts to access the physical
> error registers.
> 
> ERRIDR_EL1 advertises the number of error records, we return
> zero meaning we can treat all the other registers as RAZ/WI too.
> 
> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
> [removed specific emulation, use trap_raz_wi() directly for everything,
>  rephrased parts of the commit message]
> Signed-off-by: James Morse <james.morse@arm.com>

v4 of this patch had a Reviewed-by Marc and Christoffer, which I didn't pick up
because I'm an idiot:

https://patchwork.kernel.org/patch/10017537/


Thanks,

James

  reply	other threads:[~2018-01-08 16:24 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-15 15:50 [PATCH v5 00/13] arm64/KVM: RAS & IESB for firmware first support James Morse
2017-12-15 15:50 ` James Morse
2017-12-15 15:50 ` [PATCH v5 01/13] arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 16:24   ` Suzuki K Poulose
2017-12-15 16:24     ` Suzuki K Poulose
2017-12-15 15:50 ` [PATCH v5 02/13] arm64: sysreg: Move to use definitions for all the SCTLR bits James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 03/13] arm64: cpufeature: Detect CPU RAS Extentions James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 04/13] arm64: kernel: Survive corrected RAS errors notified by SError James Morse
2017-12-15 15:50   ` James Morse
2017-12-16  2:53   ` gengdongjiu
2017-12-16  2:53     ` gengdongjiu
2018-01-05 18:28     ` James Morse
2018-01-05 18:28       ` James Morse
2017-12-16  4:08   ` gengdongjiu
2017-12-16  4:08     ` gengdongjiu
2017-12-16  4:51     ` gengdongjiu
2017-12-16  4:51       ` gengdongjiu
2018-01-05 18:28       ` James Morse
2018-01-05 18:28         ` James Morse
2017-12-15 15:50 ` [PATCH v5 05/13] arm64: Unconditionally enable IESB on exception entry/return for firmware-first James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 06/13] arm64: kernel: Prepare for a DISR user James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 07/13] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse
2017-12-15 15:50   ` James Morse
2018-01-08 16:26   ` James Morse
2018-01-08 16:26     ` James Morse
2017-12-15 15:50 ` [PATCH v5 08/13] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 09/13] KVM: arm64: Save/Restore guest DISR_EL1 James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 10/13] KVM: arm64: Save ESR_EL2 on guest SError James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:50 ` [PATCH v5 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse
2017-12-15 15:50   ` James Morse
2017-12-15 15:51 ` [PATCH v5 12/13] KVM: arm64: Handle RAS SErrors from EL2 " James Morse
2017-12-15 15:51   ` James Morse
2017-12-15 15:51 ` [PATCH v5 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA James Morse
2017-12-15 15:51   ` James Morse
2018-01-08 16:27   ` James Morse [this message]
2018-01-08 16:27     ` James Morse

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