* [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
@ 2018-01-11 1:44 Junwei Zhang
[not found] ` <1515635053-623-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Junwei Zhang @ 2018-01-11 1:44 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Junwei Zhang
v2: fix register access
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae976e3..c73a476 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
- adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
- adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
+ adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+ adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
/* Primitive Buffer */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
@@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+ PACKET3_DMA_DATA_DST_SEL(0) |
PACKET3_DMA_DATA_SRC_SEL(2)));
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
-
+ amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS |
+ PACKET3_DMA_DATA_CMD_RAW_WAIT |
+ adev->gfx.ngg.gds_reserve_size);
gfx_v9_0_write_data_to_reg(ring, 0, false,
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
--
1.9.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
[not found] ` <1515635053-623-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-11 2:30 ` Zhang, Jerry (Junwei)
0 siblings, 0 replies; 6+ messages in thread
From: Zhang, Jerry (Junwei) @ 2018-01-11 2:30 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Please ignore this one, a minor update is coming.
Sorry for annoyance.
Jerry
On 01/11/2018 09:44 AM, Junwei Zhang wrote:
> v2: fix register access
>
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ae976e3..c73a476 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
> adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
> adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
> adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
> - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
> - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
> + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
> + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
>
> /* Primitive Buffer */
> r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
> @@ -1181,13 +1181,15 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> + PACKET3_DMA_DATA_DST_SEL(0) |
> PACKET3_DMA_DATA_SRC_SEL(2)));
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
> amdgpu_ring_write(ring, 0);
> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
> -
> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_DAS |
> + PACKET3_DMA_DATA_CMD_RAW_WAIT |
> + adev->gfx.ngg.gds_reserve_size);
>
> gfx_v9_0_write_data_to_reg(ring, 0, false,
> SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
@ 2018-01-11 2:30 Junwei Zhang
[not found] ` <1515637852-2238-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Junwei Zhang @ 2018-01-11 2:30 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Junwei Zhang
v2: fix register access
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ae976e3..6db3645 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
- adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
- adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
+ adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
+ adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
/* Primitive Buffer */
r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
@@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
+ PACKET3_DMA_DATA_DST_SEL(1) |
PACKET3_DMA_DATA_SRC_SEL(2)));
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, 0);
amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
amdgpu_ring_write(ring, 0);
- amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
-
+ amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
+ adev->gfx.ngg.gds_reserve_size);
gfx_v9_0_write_data_to_reg(ring, 0, false,
SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
[not found] ` <1515637852-2238-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-11 2:50 ` Chunming Zhou
[not found] ` <5585fbaf-d71f-3892-18e7-b6a2ea0a4e1b-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Chunming Zhou @ 2018-01-11 2:50 UTC (permalink / raw)
To: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Could I how to verify this is valid fix?
Regards,
David Zhou
On 2018年01月11日 10:30, Junwei Zhang wrote:
> v2: fix register access
>
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ae976e3..6db3645 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
> adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
> adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
> adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
> - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
> - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
> + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
> + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
>
> /* Primitive Buffer */
> r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
> @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
>
> amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
> amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
> + PACKET3_DMA_DATA_DST_SEL(1) |
> PACKET3_DMA_DATA_SRC_SEL(2)));
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, 0);
> amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
> amdgpu_ring_write(ring, 0);
> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
> -
> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
> + adev->gfx.ngg.gds_reserve_size);
>
> gfx_v9_0_write_data_to_reg(ring, 0, false,
> SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
[not found] ` <5585fbaf-d71f-3892-18e7-b6a2ea0a4e1b-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-11 2:57 ` Zhang, Jerry (Junwei)
[not found] ` <5A56D2B6.9040105-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Zhang, Jerry (Junwei) @ 2018-01-11 2:57 UTC (permalink / raw)
To: Chunming Zhou, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 01/11/2018 10:50 AM, Chunming Zhou wrote:
> Could I how to verify this is valid fix?
For now, check if there is no vm fault or any other side effect when loading
amdgpu with ngg=1.
Later development will be implemented with OGL team together.
Jerry
>
> Regards,
>
> David Zhou
>
>
> On 2018年01月11日 10:30, Junwei Zhang wrote:
>> v2: fix register access
>>
>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ae976e3..6db3645 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
>> adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
>> adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
>> adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
>> - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE);
>> - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
>> + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
>> + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
>> /* Primitive Buffer */
>> r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
>> @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
>> amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>> amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>> + PACKET3_DMA_DATA_DST_SEL(1) |
>> PACKET3_DMA_DATA_SRC_SEL(2)));
>> amdgpu_ring_write(ring, 0);
>> amdgpu_ring_write(ring, 0);
>> amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
>> amdgpu_ring_write(ring, 0);
>> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
>> -
>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
>> + adev->gfx.ngg.gds_reserve_size);
>> gfx_v9_0_write_data_to_reg(ring, 0, false,
>> SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2)
[not found] ` <5A56D2B6.9040105-5C7GfCeVMHo@public.gmane.org>
@ 2018-01-11 9:23 ` Christian König
0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2018-01-11 9:23 UTC (permalink / raw)
To: Zhang, Jerry (Junwei), Chunming Zhou,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Can't judge the other changes, but replacing the SOC15 macro with a
register read looks like a valid fix to me.
For now the patch is Acked-by: Christian König <christian.koenig@amd.com>.
Regards,
Christian.
Am 11.01.2018 um 03:57 schrieb Zhang, Jerry (Junwei):
> On 01/11/2018 10:50 AM, Chunming Zhou wrote:
>> Could I how to verify this is valid fix?
>
> For now, check if there is no vm fault or any other side effect when
> loading amdgpu with ngg=1.
>
> Later development will be implemented with OGL team together.
>
> Jerry
>
>>
>> Regards,
>>
>> David Zhou
>>
>>
>> On 2018年01月11日 10:30, Junwei Zhang wrote:
>>> v2: fix register access
>>>
>>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++----
>>> 1 file changed, 5 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index ae976e3..6db3645 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct
>>> amdgpu_device *adev)
>>> adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
>>> adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
>>> adev->gds.mem.gfx_partition_size -=
>>> adev->gfx.ngg.gds_reserve_size;
>>> - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0,
>>> mmGDS_VMID0_BASE);
>>> - adev->gfx.ngg.gds_reserve_addr +=
>>> adev->gds.mem.gfx_partition_size;
>>> + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0,
>>> mmGDS_VMID0_BASE);
>>> + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0,
>>> mmGDS_VMID0_SIZE);
>>> /* Primitive Buffer */
>>> r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
>>> @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct
>>> amdgpu_device *adev)
>>> amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
>>> amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
>>> + PACKET3_DMA_DATA_DST_SEL(1) |
>>> PACKET3_DMA_DATA_SRC_SEL(2)));
>>> amdgpu_ring_write(ring, 0);
>>> amdgpu_ring_write(ring, 0);
>>> amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
>>> amdgpu_ring_write(ring, 0);
>>> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
>>> -
>>> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
>>> + adev->gfx.ngg.gds_reserve_size);
>>> gfx_v9_0_write_data_to_reg(ring, 0, false,
>>> SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-01-11 9:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-01-11 2:30 [PATCH v2] drm/amdgpu/gfx9: fix ngg enablement to clear gds reserved memory (v2) Junwei Zhang
[not found] ` <1515637852-2238-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-01-11 2:50 ` Chunming Zhou
[not found] ` <5585fbaf-d71f-3892-18e7-b6a2ea0a4e1b-5C7GfCeVMHo@public.gmane.org>
2018-01-11 2:57 ` Zhang, Jerry (Junwei)
[not found] ` <5A56D2B6.9040105-5C7GfCeVMHo@public.gmane.org>
2018-01-11 9:23 ` Christian König
-- strict thread matches above, loose matches on Subject: below --
2018-01-11 1:44 Junwei Zhang
[not found] ` <1515635053-623-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2018-01-11 2:30 ` Zhang, Jerry (Junwei)
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