From: James Morse <james.morse@arm.com>
To: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Jonathan.Zhang@cavium.com, Marc Zyngier <marc.zyngier@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
Dongjiu Geng <gengdongjiu@huawei.com>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v6 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit
Date: Mon, 22 Jan 2018 18:18:54 +0000 [thread overview]
Message-ID: <5A662B0E.7060305@arm.com> (raw)
In-Reply-To: <20180119192055.GH21802@cbox>
Hi Christoffer,
On 19/01/18 19:20, Christoffer Dall wrote:
> On Mon, Jan 15, 2018 at 07:39:04PM +0000, James Morse wrote:
>> We expect to have firmware-first handling of RAS SErrors, with errors
>> notified via an APEI method. For systems without firmware-first, add
>> some minimal handling to KVM.
>>
>> There are two ways KVM can take an SError due to a guest, either may be a
>> RAS error: we exit the guest due to an SError routed to EL2 by HCR_EL2.AMO,
>> or we take an SError from EL2 when we unmask PSTATE.A from __guest_exit.
>>
>> For SError that interrupt a guest and are routed to EL2 the existing
>> behaviour is to inject an impdef SError into the guest.
>>
>> Add code to handle RAS SError based on the ESR. For uncontained and
>> uncategorized errors arm64_is_fatal_ras_serror() will panic(), these
>> errors compromise the host too. All other error types are contained:
>> For the fatal errors the vCPU can't make progress, so we inject a virtual
>> SError. We ignore contained errors where we can make progress as if
>> we're lucky, we may not hit them again.
>>
>> If only some of the CPUs support RAS the guest will see the cpufeature
>> sanitised version of the id registers, but we may still take RAS SError
>> on this CPU. Move the SError handling out of handle_exit() into a new
>> handler that runs before we can be preempted. This allows us to use
>> this_cpu_has_cap(), via arm64_is_ras_serror().
>
> Would it be possible to optimize this a bit later on by caching
> this_cpu_has_cap() in vcpu_load() so that we can use a single
> handle_exit function to process all exits?
If vcpu_load() prevents pre-emption between the guest-exit exception and the
this_cpu_has_cap() test then we wouldn't need a separate handle_exit().
But, if we support kernel-first RAS or firmware-first's NOTIFY_SEI we shouldn't
unmask SError until we've fed the guest-exit:SError into the RAS code. This
would also need the SError related handle_exit() calls to be separate/earlier.
(there was some verbiage on this in the cover letter).
(I started down the 'make handle_exit() non-preemptible', but WF{E,I}'s
kvm_vcpu_block()->schedule() and kvm_vcpu_on_spin()s use of kvm_vcpu_yield_to()
put an end to that).
In terms of caching this_cpu_has_cap() value, is this due to a performance
concern? It's all called behind 'exception_index == ARM_EXCEPTION_EL1_SERROR',
so we've already taken an SError out of the guest. Once its all put together
we're likely to have a pending signal for user-space.
'Corrected' (or at least ignorable) errors are going to be the odd one out, I
don't think we should worry about these!
Thanks,
James
WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit
Date: Mon, 22 Jan 2018 18:18:54 +0000 [thread overview]
Message-ID: <5A662B0E.7060305@arm.com> (raw)
In-Reply-To: <20180119192055.GH21802@cbox>
Hi Christoffer,
On 19/01/18 19:20, Christoffer Dall wrote:
> On Mon, Jan 15, 2018 at 07:39:04PM +0000, James Morse wrote:
>> We expect to have firmware-first handling of RAS SErrors, with errors
>> notified via an APEI method. For systems without firmware-first, add
>> some minimal handling to KVM.
>>
>> There are two ways KVM can take an SError due to a guest, either may be a
>> RAS error: we exit the guest due to an SError routed to EL2 by HCR_EL2.AMO,
>> or we take an SError from EL2 when we unmask PSTATE.A from __guest_exit.
>>
>> For SError that interrupt a guest and are routed to EL2 the existing
>> behaviour is to inject an impdef SError into the guest.
>>
>> Add code to handle RAS SError based on the ESR. For uncontained and
>> uncategorized errors arm64_is_fatal_ras_serror() will panic(), these
>> errors compromise the host too. All other error types are contained:
>> For the fatal errors the vCPU can't make progress, so we inject a virtual
>> SError. We ignore contained errors where we can make progress as if
>> we're lucky, we may not hit them again.
>>
>> If only some of the CPUs support RAS the guest will see the cpufeature
>> sanitised version of the id registers, but we may still take RAS SError
>> on this CPU. Move the SError handling out of handle_exit() into a new
>> handler that runs before we can be preempted. This allows us to use
>> this_cpu_has_cap(), via arm64_is_ras_serror().
>
> Would it be possible to optimize this a bit later on by caching
> this_cpu_has_cap() in vcpu_load() so that we can use a single
> handle_exit function to process all exits?
If vcpu_load() prevents pre-emption between the guest-exit exception and the
this_cpu_has_cap() test then we wouldn't need a separate handle_exit().
But, if we support kernel-first RAS or firmware-first's NOTIFY_SEI we shouldn't
unmask SError until we've fed the guest-exit:SError into the RAS code. This
would also need the SError related handle_exit() calls to be separate/earlier.
(there was some verbiage on this in the cover letter).
(I started down the 'make handle_exit() non-preemptible', but WF{E,I}'s
kvm_vcpu_block()->schedule() and kvm_vcpu_on_spin()s use of kvm_vcpu_yield_to()
put an end to that).
In terms of caching this_cpu_has_cap() value, is this due to a performance
concern? It's all called behind 'exception_index == ARM_EXCEPTION_EL1_SERROR',
so we've already taken an SError out of the guest. Once its all put together
we're likely to have a pending signal for user-space.
'Corrected' (or at least ignorable) errors are going to be the odd one out, I
don't think we should worry about these!
Thanks,
James
next prev parent reply other threads:[~2018-01-22 18:16 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-15 19:38 [PATCH v6 00/13] arm64/KVM: RAS & IESB for firmware first support James Morse
2018-01-15 19:38 ` James Morse
2018-01-15 19:38 ` [PATCH v6 01/13] arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early James Morse
2018-01-15 19:38 ` James Morse
2018-01-16 9:51 ` Marc Zyngier
2018-01-16 15:04 ` Catalin Marinas
2018-01-16 15:09 ` Suzuki K Poulose
2018-01-15 19:38 ` [PATCH v6 02/13] arm64: sysreg: Move to use definitions for all the SCTLR bits James Morse
2018-01-15 19:38 ` James Morse
2018-01-15 19:38 ` [PATCH v6 03/13] arm64: cpufeature: Detect CPU RAS Extentions James Morse
2018-01-15 19:38 ` James Morse
2018-01-16 10:26 ` Suzuki K Poulose
2018-01-16 11:17 ` gengdongjiu
2018-01-22 19:32 ` James Morse
2018-01-22 19:32 ` James Morse
2018-01-23 9:06 ` gengdongjiu
2018-01-23 9:06 ` gengdongjiu
2018-01-23 19:05 ` James Morse
2018-01-23 19:05 ` James Morse
2018-01-25 8:27 ` gengdongjiu
2018-01-25 8:27 ` gengdongjiu
2018-01-15 19:38 ` [PATCH v6 04/13] arm64: kernel: Survive corrected RAS errors notified by SError James Morse
2018-01-15 19:38 ` James Morse
2018-01-15 19:38 ` [PATCH v6 05/13] arm64: Unconditionally enable IESB on exception entry/return for firmware-first James Morse
2018-01-15 19:38 ` James Morse
2018-01-16 9:55 ` Marc Zyngier
2018-01-15 19:38 ` [PATCH v6 06/13] arm64: kernel: Prepare for a DISR user James Morse
2018-01-15 19:38 ` James Morse
2018-01-16 11:11 ` Suzuki K Poulose
2018-01-15 19:39 ` [PATCH v6 07/13] KVM: arm/arm64: mask/unmask daif around VHE guests James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 10:01 ` Marc Zyngier
2018-01-15 19:39 ` [PATCH v6 08/13] KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2 James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 10:05 ` Marc Zyngier
2018-01-15 19:39 ` [PATCH v6 09/13] KVM: arm64: Save/Restore guest DISR_EL1 James Morse
2018-01-15 19:39 ` James Morse
2018-01-15 19:39 ` [PATCH v6 10/13] KVM: arm64: Save ESR_EL2 on guest SError James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 9:41 ` Marc Zyngier
2018-01-15 19:39 ` [PATCH v6 11/13] KVM: arm64: Handle RAS SErrors from EL1 on guest exit James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 9:29 ` Marc Zyngier
2018-01-19 19:20 ` Christoffer Dall
2018-01-19 19:20 ` Christoffer Dall
2018-01-22 18:18 ` James Morse [this message]
2018-01-22 18:18 ` James Morse
2018-01-23 15:32 ` Christoffer Dall
2018-01-23 15:32 ` Christoffer Dall
2018-01-30 19:18 ` James Morse
2018-01-30 19:18 ` James Morse
2018-01-15 19:39 ` [PATCH v6 12/13] KVM: arm64: Handle RAS SErrors from EL2 " James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 9:36 ` Marc Zyngier
2018-01-19 19:54 ` Christoffer Dall
2018-01-19 19:54 ` Christoffer Dall
2018-01-15 19:39 ` [PATCH v6 13/13] KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA James Morse
2018-01-15 19:39 ` James Morse
2018-01-16 17:36 ` [PATCH v6 00/13] arm64/KVM: RAS & IESB for firmware first support Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5A662B0E.7060305@arm.com \
--to=james.morse@arm.com \
--cc=Jonathan.Zhang@cavium.com \
--cc=catalin.marinas@arm.com \
--cc=christoffer.dall@linaro.org \
--cc=gengdongjiu@huawei.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.