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From: skannan@codeaurora.org (Saravana Kannan)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2] perf/core: Add support for PMUs that can be read from more than 1 CPU
Date: Mon, 05 Mar 2018 14:02:12 -0800	[thread overview]
Message-ID: <5A9DBE64.3060209@codeaurora.org> (raw)
In-Reply-To: <20180305122140.wwwu4hvhssouuzcp@lakrids.cambridge.arm.com>

On 03/05/2018 04:21 AM, Mark Rutland wrote:
> On Mon, Mar 05, 2018 at 12:17:02PM +0000, Mark Rutland wrote:
>> On Fri, Mar 02, 2018 at 05:14:53PM -0800, Saravana Kannan wrote:
>
>>> @@ -629,6 +629,7 @@ struct perf_event {
>>>
>>>   	int				oncpu;
>>>   	int				cpu;
>>> +	cpumask_t			readable_on_cpus;
>>
>> For most PMUs, this will be emptry, and it's potentially *very* large
>> (e.g. on systems where NR_CPUS is 4096). Please use a poitner to a mask,
>> as I suggested in [1], e.g.
>
>> [1] https://lkml.kernel.org/r/20171128124534.3jvuala525wvn64r at wfg-t540p.sh.intel.com
>
> Whoops, that should've been:
>
> [1] https://lkml.kernel.org/r/20180225143802.denbkubqjg2dc7af at salmiak
>

I didn't notice you mentioned the use of pointers, but I was planning on 
doing that anyway. But then I realize people will complain about 
cacheline bouncing across 4096 CPUs if I use a cpu mask pointer.

Thanks,
Saravana

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

WARNING: multiple messages have this Message-ID (diff)
From: Saravana Kannan <skannan@codeaurora.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: suzuki.poulose@arm.com, Peter Zijlstra <peterz@infradead.org>,
	rananta@codeaurora.org,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	linux-kernel@vger.kernel.org,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>,
	Namhyung Kim <namhyung@kernel.org>,
	avilaj@codeaurora.org, Jiri Olsa <jolsa@redhat.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] perf/core: Add support for PMUs that can be read from more than 1 CPU
Date: Mon, 05 Mar 2018 14:02:12 -0800	[thread overview]
Message-ID: <5A9DBE64.3060209@codeaurora.org> (raw)
In-Reply-To: <20180305122140.wwwu4hvhssouuzcp@lakrids.cambridge.arm.com>

On 03/05/2018 04:21 AM, Mark Rutland wrote:
> On Mon, Mar 05, 2018 at 12:17:02PM +0000, Mark Rutland wrote:
>> On Fri, Mar 02, 2018 at 05:14:53PM -0800, Saravana Kannan wrote:
>
>>> @@ -629,6 +629,7 @@ struct perf_event {
>>>
>>>   	int				oncpu;
>>>   	int				cpu;
>>> +	cpumask_t			readable_on_cpus;
>>
>> For most PMUs, this will be emptry, and it's potentially *very* large
>> (e.g. on systems where NR_CPUS is 4096). Please use a poitner to a mask,
>> as I suggested in [1], e.g.
>
>> [1] https://lkml.kernel.org/r/20171128124534.3jvuala525wvn64r@wfg-t540p.sh.intel.com
>
> Whoops, that should've been:
>
> [1] https://lkml.kernel.org/r/20180225143802.denbkubqjg2dc7af@salmiak
>

I didn't notice you mentioned the use of pointers, but I was planning on 
doing that anyway. But then I realize people will complain about 
cacheline bouncing across 4096 CPUs if I use a cpu mask pointer.

Thanks,
Saravana

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

  reply	other threads:[~2018-03-05 22:02 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-03  1:14 [PATCH v2] perf/core: Add support for PMUs that can be read from more than 1 CPU Saravana Kannan
2018-03-03  1:14 ` Saravana Kannan
2018-03-05 12:17 ` Mark Rutland
2018-03-05 12:17   ` Mark Rutland
2018-03-05 12:21   ` Mark Rutland
2018-03-05 12:21     ` Mark Rutland
2018-03-05 22:02     ` Saravana Kannan [this message]
2018-03-05 22:02       ` Saravana Kannan
2018-03-05 22:06   ` Saravana Kannan
2018-03-05 22:06     ` Saravana Kannan

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