[PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Christian König]

Add the necessary handling.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a82b3eb429e8..453bd7ea50e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -560,7 +560,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 				uint64_t *addr, uint64_t *flags)
 {
-	if (!(*flags & AMDGPU_PDE_PTE))
+	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 		*addr = adev->vm_manager.vram_base_offset + *addr -
 			adev->gmc.vram_start;
 	BUG_ON(*addr & 0xFFFF00000000003FULL);
-- 
2.17.1

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[PATCH 1/5] drm/amdgpu: remove extra root PD alignment

[Christian König]

Just another leftover from radeon.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a6b1126c61fd..53ce9982a5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 {
 	struct amdgpu_bo_param bp;
 	struct amdgpu_bo *root;
-	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
-		AMDGPU_VM_PTE_COUNT(adev) * 8);
 	unsigned long size;
 	uint64_t flags;
 	int r, i;
@@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
 	memset(&bp, 0, sizeof(bp));
 	bp.size = size;
-	bp.byte_align = align;
+	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
 	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
 	bp.flags = flags;
 	bp.type = ttm_bo_type_kernel;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1162c2bf3138..1c9049feaaea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
 /* number of entries in page table */
 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
 
-/* PTBs (Page Table Blocks) need to be aligned to 32K */
-#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
-
 #define AMDGPU_PTE_VALID	(1ULL << 0)
 #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
 #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
-- 
2.17.1

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[PATCH 2/5] drm/amdgpu: add helper for VM PD/PT allocation parameters v2

[Christian König]

Add a helper function to figure them out only once.

v2: fix typo with memset

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
 1 file changed, 28 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 53ce9982a5ee..d7ecbeb2f8a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 	return r;
 }
 
+/**
+ * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requesting vm
+ * @bp: resulting BO allocation parameters
+ */
+static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+			       int level, struct amdgpu_bo_param *bp)
+{
+	memset(bp, 0, sizeof(*bp));
+
+	bp->size = amdgpu_vm_bo_size(adev, level);
+	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
+	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
+	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	if (vm->use_cpu_for_update)
+		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+	else
+		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
+	bp->type = ttm_bo_type_kernel;
+	if (vm->root.base.bo)
+		bp->resv = vm->root.base.bo->tbo.resv;
+}
+
 /**
  * amdgpu_vm_alloc_levels - allocate the PD/PT levels
  *
@@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
 				  unsigned level, bool ats)
 {
 	unsigned shift = amdgpu_vm_level_shift(adev, level);
+	struct amdgpu_bo_param bp;
 	unsigned pt_idx, from, to;
-	u64 flags;
 	int r;
 
 	if (!parent->entries) {
@@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
 	saddr = saddr & ((1 << shift) - 1);
 	eaddr = eaddr & ((1 << shift) - 1);
 
-	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-	if (vm->use_cpu_for_update)
-		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else
-		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-				AMDGPU_GEM_CREATE_SHADOW);
+	amdgpu_vm_bo_param(adev, vm, level, &bp);
 
 	/* walk over the address space and allocate the page tables */
 	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
-		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
 		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
 		struct amdgpu_bo *pt;
 
 		if (!entry->base.bo) {
-			struct amdgpu_bo_param bp;
-
-			memset(&bp, 0, sizeof(bp));
-			bp.size = amdgpu_vm_bo_size(adev, level);
-			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
-			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
-			bp.flags = flags;
-			bp.type = ttm_bo_type_kernel;
-			bp.resv = resv;
 			r = amdgpu_bo_create(adev, &bp, &pt);
 			if (r)
 				return r;
@@ -2566,8 +2576,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 {
 	struct amdgpu_bo_param bp;
 	struct amdgpu_bo *root;
-	unsigned long size;
-	uint64_t flags;
 	int r, i;
 
 	vm->va = RB_ROOT_CACHED;
@@ -2604,20 +2612,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 		  "CPU update of VM recommended only for large BAR system\n");
 	vm->last_update = NULL;
 
-	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-	if (vm->use_cpu_for_update)
-		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else
-		flags |= AMDGPU_GEM_CREATE_SHADOW;
-
-	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
-	memset(&bp, 0, sizeof(bp));
-	bp.size = size;
-	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
-	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
-	bp.flags = flags;
-	bp.type = ttm_bo_type_kernel;
-	bp.resv = NULL;
+	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
 	r = amdgpu_bo_create(adev, &bp, &root);
 	if (r)
 		goto error_free_sched_entity;
-- 
2.17.1

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[PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Christian König]

Add the necessary handling.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a82b3eb429e8..453bd7ea50e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -560,7 +560,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 				uint64_t *addr, uint64_t *flags)
 {
-	if (!(*flags & AMDGPU_PDE_PTE))
+	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 		*addr = adev->vm_manager.vram_base_offset + *addr -
 			adev->gmc.vram_start;
 	BUG_ON(*addr & 0xFFFF00000000003FULL);
-- 
2.17.1

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[PATCH 4/5] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Christian König]

Helper to get the PDE for a PD/PT.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++++++++++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
 5 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 36058feac64f..6f79ce108728 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -26,6 +26,38 @@
 
 #include "amdgpu.h"
 
+/**
+ * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
+ *
+ * @bo: the BO to get the PDE for
+ * @level: the level in the PD hirarchy
+ * @addr: resulting addr
+ * @flags: resulting flags
+ *
+ * Get the address and flags to be used for a PDE.
+ */
+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+			       uint64_t *addr, uint64_t *flags)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct ttm_dma_tt *ttm;
+
+	switch (bo->tbo.mem.mem_type) {
+	case TTM_PL_TT:
+		ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
+		*addr = ttm->dma_address[0];
+		break;
+	case TTM_PL_VRAM:
+		*addr = amdgpu_bo_gpu_offset(bo);
+		break;
+	default:
+		*addr = 0;
+		break;
+	}
+	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
+	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
+}
+
 /**
  * amdgpu_gmc_pd_addr - return the address of the root directory
  *
@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 	uint64_t pd_addr;
 
-	pd_addr = amdgpu_bo_gpu_offset(bo);
 	/* TODO: move that into ASIC specific code */
 	if (adev->asic_type >= CHIP_VEGA10) {
 		uint64_t flags = AMDGPU_PTE_VALID;
 
-		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
+		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
 		pd_addr |= flags;
+	} else {
+		pd_addr = amdgpu_bo_gpu_offset(bo);
 	}
 	return pd_addr;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 7c469cce0498..0d2c9f65ca13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 	return (gmc->real_vram_size == gmc->visible_vram_size);
 }
 
+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+			       uint64_t *addr, uint64_t *flags);
 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index eb08a03b82a0..72366643e3c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 }
 
 /**
- * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
  *
  * @ttm: The ttm_tt object to compute the flags for
  * @mem: The memory registry backing this ttm_tt object
+ *
+ * Figure out the flags to use for a VM PDE.
  */
-uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
-				 struct ttm_mem_reg *mem)
+uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
 {
 	uint64_t flags = 0;
 
@@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 			flags |= AMDGPU_PTE_SNOOPED;
 	}
 
+	return flags;
+}
+
+/**
+ * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ *
+ * @ttm: The ttm_tt object to compute the flags for
+ * @mem: The memory registry backing this ttm_tt object
+ */
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+				 struct ttm_mem_reg *mem)
+{
+	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
+
 	flags |= adev->gart.gart_pte_flags;
 	flags |= AMDGPU_PTE_READABLE;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 8b3cc6687769..fe8f276e9811 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 				       int *last_invalidated);
 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
+uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 				 struct ttm_mem_reg *mem);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index d7ecbeb2f8a4..c951ebeac5fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -992,9 +992,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
 		pbo = pbo->parent;
 
 	level += params->adev->vm_manager.root_level;
-	pt = amdgpu_bo_gpu_offset(entry->base.bo);
-	flags = AMDGPU_PTE_VALID;
-	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
+	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
 	pde = (entry - parent->entries) * 8;
 	if (bo->shadow)
 		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
-- 
2.17.1

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[PATCH 5/5] drm/amdgpu: enable GTT PD/PT for raven v2

[Christian König]

Should work on Vega10 as well, but with an obvious performance hit.

Older APUs can be enabled as well, but will probably be more work.

v2: fix error checking

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index c951ebeac5fd..c80555efbfac 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -308,6 +308,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			list_move(&bo_base->vm_status, &vm->moved);
 			spin_unlock(&vm->moved_lock);
 		} else {
+			r = amdgpu_ttm_alloc_gart(&bo->tbo);
+			if (r)
+				break;
 			list_move(&bo_base->vm_status, &vm->relocated);
 		}
 	}
@@ -396,6 +399,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 	if (r)
 		goto error;
 
+	r = amdgpu_ttm_alloc_gart(&bo->tbo);
+	if (r)
+		return r;
+
 	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 	if (r)
 		goto error;
@@ -461,7 +468,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	bp->size = amdgpu_vm_bo_size(adev, level);
 	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
 	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)
+		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
+	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
+	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 	if (vm->use_cpu_for_update)
 		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 	else
-- 
2.17.1

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Re: [PATCH 5/5] drm/amdgpu: enable GTT PD/PT for raven v2

[Alex Deucher]

On Fri, Aug 24, 2018 at 10:21 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Should work on Vega10 as well, but with an obvious performance hit.
>
> Older APUs can be enabled as well, but will probably be more work.
>
> v2: fix error checking
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index c951ebeac5fd..c80555efbfac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -308,6 +308,9 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>                         list_move(&bo_base->vm_status, &vm->moved);
>                         spin_unlock(&vm->moved_lock);
>                 } else {
> +                       r = amdgpu_ttm_alloc_gart(&bo->tbo);
> +                       if (r)
> +                               break;
>                         list_move(&bo_base->vm_status, &vm->relocated);
>                 }
>         }
> @@ -396,6 +399,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>         if (r)
>                 goto error;
>
> +       r = amdgpu_ttm_alloc_gart(&bo->tbo);
> +       if (r)
> +               return r;
> +
>         r = amdgpu_job_alloc_with_ib(adev, 64, &job);
>         if (r)
>                 goto error;
> @@ -461,7 +468,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>         bp->size = amdgpu_vm_bo_size(adev, level);
>         bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
>         bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> -       bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +       if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)

Maybe change this to (asic_type >= VEGA10 and flags & IS_APU) so we
get it automatically on newer APUs.  Either way:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Alex

> +               bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
> +       bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
> +       bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> +               AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>         if (vm->use_cpu_for_update)
>                 bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
>         else
> --
> 2.17.1
>
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Re: [PATCH 4/5] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Alex Deucher]

On Fri, Aug 24, 2018 at 10:20 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Helper to get the PDE for a PD/PT.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

A few comments below.  With those fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++++++++++++++++++++++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
>  5 files changed, 57 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 36058feac64f..6f79ce108728 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -26,6 +26,38 @@
>
>  #include "amdgpu.h"
>
> +/**
> + * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
> + *
> + * @bo: the BO to get the PDE for
> + * @level: the level in the PD hirarchy
> + * @addr: resulting addr
> + * @flags: resulting flags
> + *
> + * Get the address and flags to be used for a PDE.

Define PDE (Page Directory Entry) to make it clear what it is.

> + */
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +                              uint64_t *addr, uint64_t *flags)
> +{
> +       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +       struct ttm_dma_tt *ttm;
> +
> +       switch (bo->tbo.mem.mem_type) {
> +       case TTM_PL_TT:
> +               ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
> +               *addr = ttm->dma_address[0];
> +               break;
> +       case TTM_PL_VRAM:
> +               *addr = amdgpu_bo_gpu_offset(bo);
> +               break;
> +       default:
> +               *addr = 0;
> +               break;
> +       }
> +       *flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
> +       amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
> +}
> +
>  /**
>   * amdgpu_gmc_pd_addr - return the address of the root directory
>   *
> @@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>         uint64_t pd_addr;
>
> -       pd_addr = amdgpu_bo_gpu_offset(bo);
>         /* TODO: move that into ASIC specific code */
>         if (adev->asic_type >= CHIP_VEGA10) {
>                 uint64_t flags = AMDGPU_PTE_VALID;
>
> -               amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +               amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
>                 pd_addr |= flags;
> +       } else {
> +               pd_addr = amdgpu_bo_gpu_offset(bo);
>         }
>         return pd_addr;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 7c469cce0498..0d2c9f65ca13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>         return (gmc->real_vram_size == gmc->visible_vram_size);
>  }
>
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +                              uint64_t *addr, uint64_t *flags);
>  uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index eb08a03b82a0..72366643e3c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
>  }
>
>  /**
> - * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
>   *
>   * @ttm: The ttm_tt object to compute the flags for
>   * @mem: The memory registry backing this ttm_tt object
> + *
> + * Figure out the flags to use for a VM PDE.

Define PDE here as well.

>   */
> -uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> -                                struct ttm_mem_reg *mem)
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
>  {
>         uint64_t flags = 0;
>
> @@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>                         flags |= AMDGPU_PTE_SNOOPED;
>         }
>
> +       return flags;
> +}
> +
> +/**
> + * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + *
> + * @ttm: The ttm_tt object to compute the flags for
> + * @mem: The memory registry backing this ttm_tt object

Define PTE here and add a function description.

> + */
> +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> +                                struct ttm_mem_reg *mem)
> +{
> +       uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
> +
>         flags |= adev->gart.gart_pte_flags;
>         flags |= AMDGPU_PTE_READABLE;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 8b3cc6687769..fe8f276e9811 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
>                                        int *last_invalidated);
>  bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
>  bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
>  uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>                                  struct ttm_mem_reg *mem);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index d7ecbeb2f8a4..c951ebeac5fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -992,9 +992,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
>                 pbo = pbo->parent;
>
>         level += params->adev->vm_manager.root_level;
> -       pt = amdgpu_bo_gpu_offset(entry->base.bo);
> -       flags = AMDGPU_PTE_VALID;
> -       amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
> +       amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
>         pde = (entry - parent->entries) * 8;
>         if (bo->shadow)
>                 params->func(params, bo->shadow, pde, pt, 1, 0, flags);
> --
> 2.17.1
>
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Re: [PATCH 1/5] drm/amdgpu: remove extra root PD alignment

[Alex Deucher]

On Fri, Aug 24, 2018 at 10:20 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Just another leftover from radeon.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>  2 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index a6b1126c61fd..53ce9982a5ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>         struct amdgpu_bo_param bp;
>         struct amdgpu_bo *root;
> -       const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
> -               AMDGPU_VM_PTE_COUNT(adev) * 8);
>         unsigned long size;
>         uint64_t flags;
>         int r, i;
> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>         size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>         memset(&bp, 0, sizeof(bp));
>         bp.size = size;
> -       bp.byte_align = align;
> +       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>         bp.flags = flags;
>         bp.type = ttm_bo_type_kernel;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 1162c2bf3138..1c9049feaaea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>  /* number of entries in page table */
>  #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>
> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
> -
>  #define AMDGPU_PTE_VALID       (1ULL << 0)
>  #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
>  #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
> --
> 2.17.1
>
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Re: [PATCH 2/5] drm/amdgpu: add helper for VM PD/PT allocation parameters v2

[Alex Deucher]

On Fri, Aug 24, 2018 at 10:21 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Add a helper function to figure them out only once.
>
> v2: fix typo with memset
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
>  1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 53ce9982a5ee..d7ecbeb2f8a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>         return r;
>  }
>
> +/**
> + * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: requesting vm
> + * @bp: resulting BO allocation parameters
> + */
> +static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> +                              int level, struct amdgpu_bo_param *bp)
> +{
> +       memset(bp, 0, sizeof(*bp));
> +
> +       bp->size = amdgpu_vm_bo_size(adev, level);
> +       bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
> +       bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> +       bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +       if (vm->use_cpu_for_update)
> +               bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> +       else
> +               bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
> +       bp->type = ttm_bo_type_kernel;
> +       if (vm->root.base.bo)
> +               bp->resv = vm->root.base.bo->tbo.resv;
> +}
> +
>  /**
>   * amdgpu_vm_alloc_levels - allocate the PD/PT levels
>   *
> @@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>                                   unsigned level, bool ats)
>  {
>         unsigned shift = amdgpu_vm_level_shift(adev, level);
> +       struct amdgpu_bo_param bp;
>         unsigned pt_idx, from, to;
> -       u64 flags;
>         int r;
>
>         if (!parent->entries) {
> @@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>         saddr = saddr & ((1 << shift) - 1);
>         eaddr = eaddr & ((1 << shift) - 1);
>
> -       flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -       if (vm->use_cpu_for_update)
> -               flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -       else
> -               flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
> -                               AMDGPU_GEM_CREATE_SHADOW);
> +       amdgpu_vm_bo_param(adev, vm, level, &bp);
>
>         /* walk over the address space and allocate the page tables */
>         for (pt_idx = from; pt_idx <= to; ++pt_idx) {
> -               struct reservation_object *resv = vm->root.base.bo->tbo.resv;
>                 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
>                 struct amdgpu_bo *pt;
>
>                 if (!entry->base.bo) {
> -                       struct amdgpu_bo_param bp;
> -
> -                       memset(&bp, 0, sizeof(bp));
> -                       bp.size = amdgpu_vm_bo_size(adev, level);
> -                       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -                       bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -                       bp.flags = flags;
> -                       bp.type = ttm_bo_type_kernel;
> -                       bp.resv = resv;
>                         r = amdgpu_bo_create(adev, &bp, &pt);
>                         if (r)
>                                 return r;
> @@ -2566,8 +2576,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>         struct amdgpu_bo_param bp;
>         struct amdgpu_bo *root;
> -       unsigned long size;
> -       uint64_t flags;
>         int r, i;
>
>         vm->va = RB_ROOT_CACHED;
> @@ -2604,20 +2612,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>                   "CPU update of VM recommended only for large BAR system\n");
>         vm->last_update = NULL;
>
> -       flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -       if (vm->use_cpu_for_update)
> -               flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -       else
> -               flags |= AMDGPU_GEM_CREATE_SHADOW;
> -
> -       size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
> -       memset(&bp, 0, sizeof(bp));
> -       bp.size = size;
> -       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -       bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -       bp.flags = flags;
> -       bp.type = ttm_bo_type_kernel;
> -       bp.resv = NULL;
> +       amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
>         r = amdgpu_bo_create(adev, &bp, &root);
>         if (r)
>                 goto error_free_sched_entity;
> --
> 2.17.1
>
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Re: [PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Alex Deucher]

On Fri, Aug 24, 2018 at 10:21 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Add the necessary handling.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index a82b3eb429e8..453bd7ea50e7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -560,7 +560,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
>  static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
>                                 uint64_t *addr, uint64_t *flags)
>  {
> -       if (!(*flags & AMDGPU_PDE_PTE))
> +       if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
>                 *addr = adev->vm_manager.vram_base_offset + *addr -
>                         adev->gmc.vram_start;
>         BUG_ON(*addr & 0xFFFF00000000003FULL);
> --
> 2.17.1
>
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Re: [PATCH 1/5] drm/amdgpu: remove extra root PD alignment

[Zhang, Jerry (Junwei)]

On 08/25/2018 12:09 AM, Alex Deucher wrote:
> On Fri, Aug 24, 2018 at 10:20 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>>
>> Just another leftover from radeon.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>>   2 files changed, 1 insertion(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index a6b1126c61fd..53ce9982a5ee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>   {
>>          struct amdgpu_bo_param bp;
>>          struct amdgpu_bo *root;
>> -       const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
>> -               AMDGPU_VM_PTE_COUNT(adev) * 8);
>>          unsigned long size;
>>          uint64_t flags;
>>          int r, i;
>> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>          size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>>          memset(&bp, 0, sizeof(bp));
>>          bp.size = size;
>> -       bp.byte_align = align;
>> +       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>>          bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>>          bp.flags = flags;
>>          bp.type = ttm_bo_type_kernel;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 1162c2bf3138..1c9049feaaea 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>>   /* number of entries in page table */
>>   #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>>
>> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
>> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
>> -
>>   #define AMDGPU_PTE_VALID       (1ULL << 0)
>>   #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
>>   #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
>> --
>> 2.17.1
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 3/5] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Zhang, Jerry (Junwei)]

On 08/25/2018 12:09 AM, Alex Deucher wrote:
> On Fri, Aug 24, 2018 at 10:21 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>>
>> Add the necessary handling.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index a82b3eb429e8..453bd7ea50e7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -560,7 +560,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
>>   static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
>>                                  uint64_t *addr, uint64_t *flags)
>>   {
>> -       if (!(*flags & AMDGPU_PDE_PTE))
>> +       if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
>>                  *addr = adev->vm_manager.vram_base_offset + *addr -
>>                          adev->gmc.vram_start;
>>          BUG_ON(*addr & 0xFFFF00000000003FULL);
>> --
>> 2.17.1
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 4/5] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Zhang, Jerry (Junwei)]

On 08/24/2018 10:20 PM, Christian König wrote:
> Helper to get the PDE for a PD/PT.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++++++++++++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++--
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
>   5 files changed, 57 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 36058feac64f..6f79ce108728 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -26,6 +26,38 @@
>
>   #include "amdgpu.h"
>
> +/**
> + * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
> + *
> + * @bo: the BO to get the PDE for
> + * @level: the level in the PD hirarchy
> + * @addr: resulting addr
> + * @flags: resulting flags
> + *
> + * Get the address and flags to be used for a PDE.
> + */
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +			       uint64_t *addr, uint64_t *flags)
> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	struct ttm_dma_tt *ttm;
> +
> +	switch (bo->tbo.mem.mem_type) {
> +	case TTM_PL_TT:
> +		ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
> +		*addr = ttm->dma_address[0];
> +		break;
> +	case TTM_PL_VRAM:
> +		*addr = amdgpu_bo_gpu_offset(bo);
> +		break;
> +	default:
> +		*addr = 0;
> +		break;
> +	}
> +	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
> +	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
> +}
> +
>   /**
>    * amdgpu_gmc_pd_addr - return the address of the root directory
>    *
> @@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>   	uint64_t pd_addr;
>
> -	pd_addr = amdgpu_bo_gpu_offset(bo);
>   	/* TODO: move that into ASIC specific code */
>   	if (adev->asic_type >= CHIP_VEGA10) {
>   		uint64_t flags = AMDGPU_PTE_VALID;
>
> -		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
>   		pd_addr |= flags;
> +	} else {
> +		pd_addr = amdgpu_bo_gpu_offset(bo);
>   	}
>   	return pd_addr;
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 7c469cce0498..0d2c9f65ca13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>   	return (gmc->real_vram_size == gmc->visible_vram_size);
>   }
>
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +			       uint64_t *addr, uint64_t *flags);
>   uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index eb08a03b82a0..72366643e3c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
>   }
>
>   /**
> - * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
>    *
>    * @ttm: The ttm_tt object to compute the flags for
>    * @mem: The memory registry backing this ttm_tt object
> + *
> + * Figure out the flags to use for a VM PDE.
>    */
> -uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> -				 struct ttm_mem_reg *mem)
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
>   {
>   	uint64_t flags = 0;
>
> @@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>   			flags |= AMDGPU_PTE_SNOOPED;
>   	}
>
> +	return flags;
> +}
> +
> +/**
> + * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + *
> + * @ttm: The ttm_tt object to compute the flags for
> + * @mem: The memory registry backing this ttm_tt object
> + */
> +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> +				 struct ttm_mem_reg *mem)
> +{
> +	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
> +
>   	flags |= adev->gart.gart_pte_flags;
>   	flags |= AMDGPU_PTE_READABLE;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 8b3cc6687769..fe8f276e9811 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
>   				       int *last_invalidated);
>   bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
>   bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
>   uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>   				 struct ttm_mem_reg *mem);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index d7ecbeb2f8a4..c951ebeac5fd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -992,9 +992,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
>   		pbo = pbo->parent;
>
>   	level += params->adev->vm_manager.root_level;
> -	pt = amdgpu_bo_gpu_offset(entry->base.bo);
> -	flags = AMDGPU_PTE_VALID;
> -	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
> +	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
>   	pde = (entry - parent->entries) * 8;
>   	if (bo->shadow)
>   		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
>
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