[PATCH 1/7] drm/amdgpu: correctly sign extend 48bit addresses v3

[PATCH 1/7] drm/amdgpu: correctly sign extend 48bit addresses v3

[Christian König]

Correct sign extend the GMC addresses to 48bit.

v2: sign extending turned out easier than thought.
v3: clean up the defines and move them into amdgpu_gmc.h as well

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c     |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c    | 10 ++++-----
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h    | 26 ++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c    |  8 +++----
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c   |  6 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     |  7 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h     | 13 -----------
 9 files changed, 44 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 8c652ecc4f9a..bc5ccfca68c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -135,7 +135,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
 			.gpuvm_size = min(adev->vm_manager.max_pfn
 					  << AMDGPU_GPU_PAGE_SHIFT,
-					  AMDGPU_VA_HOLE_START),
+					  AMDGPU_GMC_HOLE_START),
 			.drm_render_minor = adev->ddev->render->index
 		};
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index dd734970e167..ef2bfc04b41c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -835,7 +835,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 				continue;
 
-			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
+			va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
 			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
 			if (r) {
 				DRM_ERROR("IB va_start is invalid\n");
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 71792d820ae0..d30a0838851b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -572,16 +572,16 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 		return -EINVAL;
 	}
 
-	if (args->va_address >= AMDGPU_VA_HOLE_START &&
-	    args->va_address < AMDGPU_VA_HOLE_END) {
+	if (args->va_address >= AMDGPU_GMC_HOLE_START &&
+	    args->va_address < AMDGPU_GMC_HOLE_END) {
 		dev_dbg(&dev->pdev->dev,
 			"va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
-			args->va_address, AMDGPU_VA_HOLE_START,
-			AMDGPU_VA_HOLE_END);
+			args->va_address, AMDGPU_GMC_HOLE_START,
+			AMDGPU_GMC_HOLE_END);
 		return -EINVAL;
 	}
 
-	args->va_address &= AMDGPU_VA_HOLE_MASK;
+	args->va_address &= AMDGPU_GMC_HOLE_MASK;
 
 	if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
 		dev_dbg(&dev->pdev->dev, "invalid flags combination 0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 72fcc9338f5e..48715dd5808a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -30,6 +30,19 @@
 
 #include "amdgpu_irq.h"
 
+/* VA hole for 48bit addresses on Vega10 */
+#define AMDGPU_GMC_HOLE_START	0x0000800000000000ULL
+#define AMDGPU_GMC_HOLE_END	0xffff800000000000ULL
+
+/*
+ * Hardware is programmed as if the hole doesn't exists with start and end
+ * address values.
+ *
+ * This mask is used to remove the upper 16bits of the VA and so come up with
+ * the linear addr value.
+ */
+#define AMDGPU_GMC_HOLE_MASK	0x0000ffffffffffffULL
+
 struct firmware;
 
 /*
@@ -131,6 +144,19 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 	return (gmc->real_vram_size == gmc->visible_vram_size);
 }
 
+/**
+ * amdgpu_gmc_sign_extend - sign extend the given gmc address
+ *
+ * @addr: address to extend
+ */
+static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
+{
+	if (addr >= AMDGPU_GMC_HOLE_START)
+		addr |= AMDGPU_GMC_HOLE_END;
+
+	return addr;
+}
+
 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 			       uint64_t *addr, uint64_t *flags);
 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 9c4e45936ade..29ac3873eeb0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -655,11 +655,11 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
 
 		dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
 		dev_info.virtual_address_max =
-			min(vm_size, AMDGPU_VA_HOLE_START);
+			min(vm_size, AMDGPU_GMC_HOLE_START);
 
-		if (vm_size > AMDGPU_VA_HOLE_START) {
-			dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
-			dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
+		if (vm_size > AMDGPU_GMC_HOLE_START) {
+			dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
+			dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
 		}
 		dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
 		dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index b5f20b42439e..0cbf651a88a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1368,7 +1368,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
 	WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 		     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
 
-	return bo->tbo.offset;
+	return amdgpu_gmc_sign_extend(bo->tbo.offset);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 38856365580d..f2f358aa0597 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -28,9 +28,7 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
 	uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
 
 	addr -= AMDGPU_VA_RESERVED_SIZE;
-
-	if (addr >= AMDGPU_VA_HOLE_START)
-		addr |= AMDGPU_VA_HOLE_END;
+	addr = amdgpu_gmc_sign_extend(addr);
 
 	return addr;
 }
@@ -73,7 +71,7 @@ void amdgpu_free_static_csa(struct amdgpu_device *adev) {
 int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			  struct amdgpu_bo_va **bo_va)
 {
-	uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_VA_HOLE_MASK;
+	uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
 	struct ww_acquire_ctx ticket;
 	struct list_head list;
 	struct amdgpu_bo_list_entry pd;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 153c9bec341a..a3675c7b6190 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -400,7 +400,7 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 		if (level == adev->vm_manager.root_level) {
 			ats_entries = amdgpu_vm_level_shift(adev, level);
 			ats_entries += AMDGPU_GPU_PAGE_SHIFT;
-			ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
+			ats_entries = AMDGPU_GMC_HOLE_START >> ats_entries;
 			ats_entries = min(ats_entries, entries);
 			entries -= ats_entries;
 		} else {
@@ -630,7 +630,7 @@ int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 	eaddr = saddr + size - 1;
 
 	if (vm->pte_support_ats)
-		ats = saddr < AMDGPU_VA_HOLE_START;
+		ats = saddr < AMDGPU_GMC_HOLE_START;
 
 	saddr /= AMDGPU_GPU_PAGE_SIZE;
 	eaddr /= AMDGPU_GPU_PAGE_SIZE;
@@ -1935,7 +1935,8 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
 			struct amdgpu_bo_va_mapping, list);
 		list_del(&mapping->list);
 
-		if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
+		if (vm->pte_support_ats &&
+		    mapping->start < AMDGPU_GMC_HOLE_START)
 			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
 
 		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 62116fa44718..ae61fa587180 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -101,19 +101,6 @@ struct amdgpu_bo_list_entry;
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE			(1ULL << 20)
 
-/* VA hole for 48bit addresses on Vega10 */
-#define AMDGPU_VA_HOLE_START			0x0000800000000000ULL
-#define AMDGPU_VA_HOLE_END			0xffff800000000000ULL
-
-/*
- * Hardware is programmed as if the hole doesn't exists with start and end
- * address values.
- *
- * This mask is used to remove the upper 16bits of the VA and so come up with
- * the linear addr value.
- */
-#define AMDGPU_VA_HOLE_MASK			0x0000ffffffffffffULL
-
 /* max vmids dedicated for process */
 #define AMDGPU_VM_MAX_RESERVED_VMID	1
 
-- 
2.17.1

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[PATCH 2/7] drm/amdgpu: put GART away from VRAM v2

[Christian König]

Always try to put the GART away from where VRAM is.

v2: correctly handle the 4GB limitation

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 265ec6807130..c6bcc4715373 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -116,6 +116,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
  */
 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
 {
+	const uint64_t four_gb = 0x100000000ULL;
 	u64 size_af, size_bf;
 
 	mc->gart_size += adev->pm.smu_prv_buffer_size;
@@ -124,8 +125,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
 	 * the GART base on a 4GB boundary as well.
 	 */
 	size_bf = mc->vram_start;
-	size_af = adev->gmc.mc_mask + 1 -
-		ALIGN(mc->vram_end + 1, 0x100000000ULL);
+	size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->vram_end + 1, four_gb);
 
 	if (mc->gart_size > max(size_bf, size_af)) {
 		dev_warn(adev->dev, "limiting GART\n");
@@ -136,7 +136,9 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
 	    (size_af < mc->gart_size))
 		mc->gart_start = 0;
 	else
-		mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
+		mc->gart_start = mc->mc_mask - mc->gart_size + 1;
+
+	mc->gart_start &= four_gb - 1;
 	mc->gart_end = mc->gart_start + mc->gart_size - 1;
 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
-- 
2.17.1

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Re: [PATCH 2/7] drm/amdgpu: put GART away from VRAM v2

[Zhang, Jerry (Junwei)]

On 08/29/2018 10:08 PM, Christian König wrote:
> Always try to put the GART away from where VRAM is.
>
> v2: correctly handle the 4GB limitation
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Fix my concern :)

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 265ec6807130..c6bcc4715373 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -116,6 +116,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
>    */
>   void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
>   {
> +	const uint64_t four_gb = 0x100000000ULL;
>   	u64 size_af, size_bf;
>
>   	mc->gart_size += adev->pm.smu_prv_buffer_size;
> @@ -124,8 +125,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
>   	 * the GART base on a 4GB boundary as well.
>   	 */
>   	size_bf = mc->vram_start;
> -	size_af = adev->gmc.mc_mask + 1 -
> -		ALIGN(mc->vram_end + 1, 0x100000000ULL);
> +	size_af = adev->gmc.mc_mask + 1 - ALIGN(mc->vram_end + 1, four_gb);
>
>   	if (mc->gart_size > max(size_bf, size_af)) {
>   		dev_warn(adev->dev, "limiting GART\n");
> @@ -136,7 +136,9 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
>   	    (size_af < mc->gart_size))
>   		mc->gart_start = 0;
>   	else
> -		mc->gart_start = ALIGN(mc->vram_end + 1, 0x100000000ULL);
> +		mc->gart_start = mc->mc_mask - mc->gart_size + 1;
> +
> +	mc->gart_start &= four_gb - 1;
>   	mc->gart_end = mc->gart_start + mc->gart_size - 1;
>   	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
>   			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
>
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[PATCH 3/7] drm/amdgpu: add amdgpu_gmc_agp_location v2

[Christian König]

Helper to figure out the location of the AGP BAR.

v2: fix a couple of bugs

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 43 +++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  5 +++
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index c6bcc4715373..1d201fd3f4af 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -143,3 +143,46 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
 	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
 			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
 }
+
+/**
+ * amdgpu_gmc_agp_location - try to find AGP location
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
+ * Function will place try to find a place for the AGP BAR in the MC address
+ * space.
+ *
+ * AGP BAR will be assigned the largest available hole in the address space.
+ * Should be called after VRAM and GART locations are setup.
+ */
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
+{
+	const uint64_t sixteen_gb = 1ULL << 34;
+	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
+	u64 size_af, size_bf;
+
+	if (mc->vram_start > mc->gart_start) {
+		size_bf = (mc->vram_start & sixteen_gb_mask) -
+			ALIGN(mc->gart_end + 1, sixteen_gb);
+		size_af = mc->mc_mask + 1 - ALIGN(mc->vram_end, sixteen_gb);
+	} else {
+		size_bf = mc->vram_start & sixteen_gb_mask;
+		size_af = (mc->gart_start & sixteen_gb_mask) -
+			ALIGN(mc->vram_end, sixteen_gb);
+	}
+
+	if (size_bf > size_af) {
+		mc->agp_start = mc->vram_start > mc->gart_start ?
+			mc->gart_end + 1 : 0;
+		mc->agp_size = size_bf;
+	} else {
+		mc->agp_start = (mc->vram_start > mc->gart_start ?
+			mc->vram_end : mc->gart_end) + 1,
+		mc->agp_size = size_af;
+	}
+
+	mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
+	mc->agp_end = mc->agp_start + mc->agp_size - 1;
+	dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
+			mc->agp_size >> 20, mc->agp_start, mc->agp_end);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 48715dd5808a..c9985e7dc9e5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -94,6 +94,9 @@ struct amdgpu_gmc {
 	 * about vram size near mc fb location */
 	u64			mc_vram_size;
 	u64			visible_vram_size;
+	u64			agp_size;
+	u64			agp_start;
+	u64			agp_end;
 	u64			gart_size;
 	u64			gart_start;
 	u64			gart_end;
@@ -164,5 +167,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 			      u64 base);
 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
 			      struct amdgpu_gmc *mc);
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+			     struct amdgpu_gmc *mc);
 
 #endif
-- 
2.17.1

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Re: [PATCH 3/7] drm/amdgpu: add amdgpu_gmc_agp_location v2

[Zhang, Jerry (Junwei)]

On 08/29/2018 10:08 PM, Christian König wrote:
> Helper to figure out the location of the AGP BAR.
>
> v2: fix a couple of bugs
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 43 +++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  5 +++
>   2 files changed, 48 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index c6bcc4715373..1d201fd3f4af 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -143,3 +143,46 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
>   	dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
>   			mc->gart_size >> 20, mc->gart_start, mc->gart_end);
>   }
> +
> +/**
> + * amdgpu_gmc_agp_location - try to find AGP location
> + * @adev: amdgpu device structure holding all necessary informations
> + * @mc: memory controller structure holding memory informations
> + *
> + * Function will place try to find a place for the AGP BAR in the MC address
> + * space.
> + *
> + * AGP BAR will be assigned the largest available hole in the address space.
> + * Should be called after VRAM and GART locations are setup.
> + */
> +void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
> +{
> +	const uint64_t sixteen_gb = 1ULL << 34;
> +	const uint64_t sixteen_gb_mask = ~(sixteen_gb - 1);
> +	u64 size_af, size_bf;
> +
> +	if (mc->vram_start > mc->gart_start) {
> +		size_bf = (mc->vram_start & sixteen_gb_mask) -
> +			ALIGN(mc->gart_end + 1, sixteen_gb);
> +		size_af = mc->mc_mask + 1 - ALIGN(mc->vram_end, sixteen_gb);
> +	} else {
> +		size_bf = mc->vram_start & sixteen_gb_mask;
> +		size_af = (mc->gart_start & sixteen_gb_mask) -
> +			ALIGN(mc->vram_end, sixteen_gb);

we may need ALIGN(mc->vram_end + 1, sixteen_gb) for size_af.

> +	}
> +
> +	if (size_bf > size_af) {
> +		mc->agp_start = mc->vram_start > mc->gart_start ?
> +			mc->gart_end + 1 : 0;
> +		mc->agp_size = size_bf;
> +	} else {
> +		mc->agp_start = (mc->vram_start > mc->gart_start ?
> +			mc->vram_end : mc->gart_end) + 1,
> +		mc->agp_size = size_af;
> +	}
> +
> +	mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
> +	mc->agp_end = mc->agp_start + mc->agp_size - 1;
> +	dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
> +			mc->agp_size >> 20, mc->agp_start, mc->agp_end);
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 48715dd5808a..c9985e7dc9e5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -94,6 +94,9 @@ struct amdgpu_gmc {
>   	 * about vram size near mc fb location */
>   	u64			mc_vram_size;
>   	u64			visible_vram_size;
> +	u64			agp_size;
> +	u64			agp_start;
> +	u64			agp_end;
>   	u64			gart_size;
>   	u64			gart_start;
>   	u64			gart_end;
> @@ -164,5 +167,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
>   			      u64 base);
>   void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
>   			      struct amdgpu_gmc *mc);
> +void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
> +			     struct amdgpu_gmc *mc);
>
>   #endif
>
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[PATCH 4/7] drm/amdgpu: use the AGP aperture for system memory access v2

[Christian König]

Start to use the old AGP aperture for system memory access.

v2: Move that to amdgpu_ttm_alloc_gart

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 23 ++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 58 ++++++++++++++-----------
 3 files changed, 57 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 1d201fd3f4af..65aee57b35fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -79,6 +79,29 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
 	return pd_addr;
 }
 
+/**
+ * amdgpu_gmc_agp_addr - return the address in the AGP address space
+ *
+ * @tbo: TTM BO which needs the address, must be in GTT domain
+ *
+ * Tries to figure out how to access the BO through the AGP aperture. Returns
+ * AMDGPU_BO_INVALID_OFFSET if that is not possible.
+ */
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
+	struct ttm_dma_tt *ttm;
+
+	if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
+		return AMDGPU_BO_INVALID_OFFSET;
+
+	ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
+	if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
+		return AMDGPU_BO_INVALID_OFFSET;
+
+	return adev->gmc.agp_start + ttm->dma_address[0];
+}
+
 /**
  * amdgpu_gmc_vram_location - try to find VRAM location
  *
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index c9985e7dc9e5..265ca415c64c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -163,6 +163,7 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
 			       uint64_t *addr, uint64_t *flags);
 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 			      u64 base);
 void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d9f3201c9e5c..8a158ee922f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1081,41 +1081,49 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 	struct ttm_mem_reg tmp;
 	struct ttm_placement placement;
 	struct ttm_place placements;
-	uint64_t flags;
+	uint64_t addr, flags;
 	int r;
 
 	if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 		return 0;
 
-	/* allocate GART space */
-	tmp = bo->mem;
-	tmp.mm_node = NULL;
-	placement.num_placement = 1;
-	placement.placement = &placements;
-	placement.num_busy_placement = 1;
-	placement.busy_placement = &placements;
-	placements.fpfn = 0;
-	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
-	placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
-		TTM_PL_FLAG_TT;
+	addr = amdgpu_gmc_agp_addr(bo);
+	if (addr != AMDGPU_BO_INVALID_OFFSET) {
+		bo->mem.start = addr >> PAGE_SHIFT;
+	} else {
 
-	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
-	if (unlikely(r))
-		return r;
+		/* allocate GART space */
+		tmp = bo->mem;
+		tmp.mm_node = NULL;
+		placement.num_placement = 1;
+		placement.placement = &placements;
+		placement.num_busy_placement = 1;
+		placement.busy_placement = &placements;
+		placements.fpfn = 0;
+		placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
+		placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
+			TTM_PL_FLAG_TT;
+
+		r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
+		if (unlikely(r))
+			return r;
 
-	/* compute PTE flags for this buffer object */
-	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
+		/* compute PTE flags for this buffer object */
+		flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 
-	/* Bind pages */
-	gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
-	r = amdgpu_ttm_gart_bind(adev, bo, flags);
-	if (unlikely(r)) {
-		ttm_bo_mem_put(bo, &tmp);
-		return r;
+		/* Bind pages */
+		gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
+			adev->gmc.gart_start;
+		r = amdgpu_ttm_gart_bind(adev, bo, flags);
+		if (unlikely(r)) {
+			ttm_bo_mem_put(bo, &tmp);
+			return r;
+		}
+
+		ttm_bo_mem_put(bo, &bo->mem);
+		bo->mem = tmp;
 	}
 
-	ttm_bo_mem_put(bo, &bo->mem);
-	bo->mem = tmp;
 	bo->offset = (bo->mem.start << PAGE_SHIFT) +
 		bo->bdev->man[bo->mem.mem_type].gpu_offset;
 
-- 
2.17.1

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Re: [PATCH 4/7] drm/amdgpu: use the AGP aperture for system memory access v2

[Zhang, Jerry (Junwei)]

On 08/29/2018 10:08 PM, Christian König wrote:
> Start to use the old AGP aperture for system memory access.
>
> v2: Move that to amdgpu_ttm_alloc_gart
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 23 ++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 58 ++++++++++++++-----------
>   3 files changed, 57 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 1d201fd3f4af..65aee57b35fe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -79,6 +79,29 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>   	return pd_addr;
>   }
>
> +/**
> + * amdgpu_gmc_agp_addr - return the address in the AGP address space
> + *
> + * @tbo: TTM BO which needs the address, must be in GTT domain
> + *
> + * Tries to figure out how to access the BO through the AGP aperture. Returns
> + * AMDGPU_BO_INVALID_OFFSET if that is not possible.
> + */
> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
> +	struct ttm_dma_tt *ttm;
> +
> +	if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
> +		return AMDGPU_BO_INVALID_OFFSET;

If GTT bo size is 1 page, it will also access in AGP address space?

Jerry
> +
> +	ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
> +	if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
> +		return AMDGPU_BO_INVALID_OFFSET;
> +
> +	return adev->gmc.agp_start + ttm->dma_address[0];
> +}
> +
>   /**
>    * amdgpu_gmc_vram_location - try to find VRAM location
>    *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index c9985e7dc9e5..265ca415c64c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -163,6 +163,7 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
>   void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
>   			       uint64_t *addr, uint64_t *flags);
>   uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
>   void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
>   			      u64 base);
>   void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index d9f3201c9e5c..8a158ee922f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1081,41 +1081,49 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>   	struct ttm_mem_reg tmp;
>   	struct ttm_placement placement;
>   	struct ttm_place placements;
> -	uint64_t flags;
> +	uint64_t addr, flags;
>   	int r;
>
>   	if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
>   		return 0;
>
> -	/* allocate GART space */
> -	tmp = bo->mem;
> -	tmp.mm_node = NULL;
> -	placement.num_placement = 1;
> -	placement.placement = &placements;
> -	placement.num_busy_placement = 1;
> -	placement.busy_placement = &placements;
> -	placements.fpfn = 0;
> -	placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
> -	placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
> -		TTM_PL_FLAG_TT;
> +	addr = amdgpu_gmc_agp_addr(bo);
> +	if (addr != AMDGPU_BO_INVALID_OFFSET) {
> +		bo->mem.start = addr >> PAGE_SHIFT;
> +	} else {
>
> -	r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
> -	if (unlikely(r))
> -		return r;
> +		/* allocate GART space */
> +		tmp = bo->mem;
> +		tmp.mm_node = NULL;
> +		placement.num_placement = 1;
> +		placement.placement = &placements;
> +		placement.num_busy_placement = 1;
> +		placement.busy_placement = &placements;
> +		placements.fpfn = 0;
> +		placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
> +		placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
> +			TTM_PL_FLAG_TT;
> +
> +		r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
> +		if (unlikely(r))
> +			return r;
>
> -	/* compute PTE flags for this buffer object */
> -	flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
> +		/* compute PTE flags for this buffer object */
> +		flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
>
> -	/* Bind pages */
> -	gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
> -	r = amdgpu_ttm_gart_bind(adev, bo, flags);
> -	if (unlikely(r)) {
> -		ttm_bo_mem_put(bo, &tmp);
> -		return r;
> +		/* Bind pages */
> +		gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
> +			adev->gmc.gart_start;
> +		r = amdgpu_ttm_gart_bind(adev, bo, flags);
> +		if (unlikely(r)) {
> +			ttm_bo_mem_put(bo, &tmp);
> +			return r;
> +		}
> +
> +		ttm_bo_mem_put(bo, &bo->mem);
> +		bo->mem = tmp;
>   	}
>
> -	ttm_bo_mem_put(bo, &bo->mem);
> -	bo->mem = tmp;
>   	bo->offset = (bo->mem.start << PAGE_SHIFT) +
>   		bo->bdev->man[bo->mem.mem_type].gpu_offset;
>
>
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Re: [PATCH 4/7] drm/amdgpu: use the AGP aperture for system memory access v2

[Christian König]

Am 30.08.2018 um 05:20 schrieb Zhang, Jerry (Junwei):
> On 08/29/2018 10:08 PM, Christian König wrote:
>> Start to use the old AGP aperture for system memory access.
>>
>> v2: Move that to amdgpu_ttm_alloc_gart
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 23 ++++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 58 ++++++++++++++-----------
>>   3 files changed, 57 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> index 1d201fd3f4af..65aee57b35fe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> @@ -79,6 +79,29 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>>       return pd_addr;
>>   }
>>
>> +/**
>> + * amdgpu_gmc_agp_addr - return the address in the AGP address space
>> + *
>> + * @tbo: TTM BO which needs the address, must be in GTT domain
>> + *
>> + * Tries to figure out how to access the BO through the AGP 
>> aperture. Returns
>> + * AMDGPU_BO_INVALID_OFFSET if that is not possible.
>> + */
>> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
>> +{
>> +    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>> +    struct ttm_dma_tt *ttm;
>> +
>> +    if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
>> +        return AMDGPU_BO_INVALID_OFFSET;
>
> If GTT bo size is 1 page, it will also access in AGP address space?

Yes, that is the idea here.

We basically can avoid GART mappings for BOs in the GTT domain which are 
only one page in size.

Christian.

>
> Jerry
>> +
>> +    ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
>> +    if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
>> +        return AMDGPU_BO_INVALID_OFFSET;
>> +
>> +    return adev->gmc.agp_start + ttm->dma_address[0];
>> +}
>> +
>>   /**
>>    * amdgpu_gmc_vram_location - try to find VRAM location
>>    *
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> index c9985e7dc9e5..265ca415c64c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> @@ -163,6 +163,7 @@ static inline uint64_t 
>> amdgpu_gmc_sign_extend(uint64_t addr)
>>   void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
>>                      uint64_t *addr, uint64_t *flags);
>>   uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
>>   void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct 
>> amdgpu_gmc *mc,
>>                     u64 base);
>>   void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index d9f3201c9e5c..8a158ee922f7 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -1081,41 +1081,49 @@ int amdgpu_ttm_alloc_gart(struct 
>> ttm_buffer_object *bo)
>>       struct ttm_mem_reg tmp;
>>       struct ttm_placement placement;
>>       struct ttm_place placements;
>> -    uint64_t flags;
>> +    uint64_t addr, flags;
>>       int r;
>>
>>       if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
>>           return 0;
>>
>> -    /* allocate GART space */
>> -    tmp = bo->mem;
>> -    tmp.mm_node = NULL;
>> -    placement.num_placement = 1;
>> -    placement.placement = &placements;
>> -    placement.num_busy_placement = 1;
>> -    placement.busy_placement = &placements;
>> -    placements.fpfn = 0;
>> -    placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>> -    placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
>> -        TTM_PL_FLAG_TT;
>> +    addr = amdgpu_gmc_agp_addr(bo);
>> +    if (addr != AMDGPU_BO_INVALID_OFFSET) {
>> +        bo->mem.start = addr >> PAGE_SHIFT;
>> +    } else {
>>
>> -    r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
>> -    if (unlikely(r))
>> -        return r;
>> +        /* allocate GART space */
>> +        tmp = bo->mem;
>> +        tmp.mm_node = NULL;
>> +        placement.num_placement = 1;
>> +        placement.placement = &placements;
>> +        placement.num_busy_placement = 1;
>> +        placement.busy_placement = &placements;
>> +        placements.fpfn = 0;
>> +        placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>> +        placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
>> +            TTM_PL_FLAG_TT;
>> +
>> +        r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
>> +        if (unlikely(r))
>> +            return r;
>>
>> -    /* compute PTE flags for this buffer object */
>> -    flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
>> +        /* compute PTE flags for this buffer object */
>> +        flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
>>
>> -    /* Bind pages */
>> -    gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - 
>> adev->gmc.gart_start;
>> -    r = amdgpu_ttm_gart_bind(adev, bo, flags);
>> -    if (unlikely(r)) {
>> -        ttm_bo_mem_put(bo, &tmp);
>> -        return r;
>> +        /* Bind pages */
>> +        gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
>> +            adev->gmc.gart_start;
>> +        r = amdgpu_ttm_gart_bind(adev, bo, flags);
>> +        if (unlikely(r)) {
>> +            ttm_bo_mem_put(bo, &tmp);
>> +            return r;
>> +        }
>> +
>> +        ttm_bo_mem_put(bo, &bo->mem);
>> +        bo->mem = tmp;
>>       }
>>
>> -    ttm_bo_mem_put(bo, &bo->mem);
>> -    bo->mem = tmp;
>>       bo->offset = (bo->mem.start << PAGE_SHIFT) +
>>           bo->bdev->man[bo->mem.mem_type].gpu_offset;
>>
>>

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Re: [PATCH 4/7] drm/amdgpu: use the AGP aperture for system memory access v2

[Zhang, Jerry (Junwei)]

On 08/30/2018 08:15 PM, Christian König wrote:
> Am 30.08.2018 um 05:20 schrieb Zhang, Jerry (Junwei):
>> On 08/29/2018 10:08 PM, Christian König wrote:
>>> Start to use the old AGP aperture for system memory access.
>>>
>>> v2: Move that to amdgpu_ttm_alloc_gart
>>>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 23 ++++++++++
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  1 +
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 58 ++++++++++++++-----------
>>>   3 files changed, 57 insertions(+), 25 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>>> index 1d201fd3f4af..65aee57b35fe 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>>> @@ -79,6 +79,29 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>>>       return pd_addr;
>>>   }
>>>
>>> +/**
>>> + * amdgpu_gmc_agp_addr - return the address in the AGP address space
>>> + *
>>> + * @tbo: TTM BO which needs the address, must be in GTT domain
>>> + *
>>> + * Tries to figure out how to access the BO through the AGP aperture. Returns
>>> + * AMDGPU_BO_INVALID_OFFSET if that is not possible.
>>> + */
>>> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo)
>>> +{
>>> +    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
>>> +    struct ttm_dma_tt *ttm;
>>> +
>>> +    if (bo->num_pages != 1 || bo->ttm->caching_state == tt_cached)
>>> +        return AMDGPU_BO_INVALID_OFFSET;
>>
>> If GTT bo size is 1 page, it will also access in AGP address space?
>
> Yes, that is the idea here.
>
> We basically can avoid GART mappings for BOs in the GTT domain which are only one page in size.

Thanks to explain that, got the intention.

Jerry

>
> Christian.
>
>>
>> Jerry
>>> +
>>> +    ttm = container_of(bo->ttm, struct ttm_dma_tt, ttm);
>>> +    if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
>>> +        return AMDGPU_BO_INVALID_OFFSET;
>>> +
>>> +    return adev->gmc.agp_start + ttm->dma_address[0];
>>> +}
>>> +
>>>   /**
>>>    * amdgpu_gmc_vram_location - try to find VRAM location
>>>    *
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> index c9985e7dc9e5..265ca415c64c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>>> @@ -163,6 +163,7 @@ static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr)
>>>   void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
>>>                      uint64_t *addr, uint64_t *flags);
>>>   uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>>> +uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo);
>>>   void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
>>>                     u64 base);
>>>   void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> index d9f3201c9e5c..8a158ee922f7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> @@ -1081,41 +1081,49 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
>>>       struct ttm_mem_reg tmp;
>>>       struct ttm_placement placement;
>>>       struct ttm_place placements;
>>> -    uint64_t flags;
>>> +    uint64_t addr, flags;
>>>       int r;
>>>
>>>       if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
>>>           return 0;
>>>
>>> -    /* allocate GART space */
>>> -    tmp = bo->mem;
>>> -    tmp.mm_node = NULL;
>>> -    placement.num_placement = 1;
>>> -    placement.placement = &placements;
>>> -    placement.num_busy_placement = 1;
>>> -    placement.busy_placement = &placements;
>>> -    placements.fpfn = 0;
>>> -    placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>>> -    placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
>>> -        TTM_PL_FLAG_TT;
>>> +    addr = amdgpu_gmc_agp_addr(bo);
>>> +    if (addr != AMDGPU_BO_INVALID_OFFSET) {
>>> +        bo->mem.start = addr >> PAGE_SHIFT;
>>> +    } else {
>>>
>>> -    r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
>>> -    if (unlikely(r))
>>> -        return r;
>>> +        /* allocate GART space */
>>> +        tmp = bo->mem;
>>> +        tmp.mm_node = NULL;
>>> +        placement.num_placement = 1;
>>> +        placement.placement = &placements;
>>> +        placement.num_busy_placement = 1;
>>> +        placement.busy_placement = &placements;
>>> +        placements.fpfn = 0;
>>> +        placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>>> +        placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
>>> +            TTM_PL_FLAG_TT;
>>> +
>>> +        r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
>>> +        if (unlikely(r))
>>> +            return r;
>>>
>>> -    /* compute PTE flags for this buffer object */
>>> -    flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
>>> +        /* compute PTE flags for this buffer object */
>>> +        flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
>>>
>>> -    /* Bind pages */
>>> -    gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
>>> -    r = amdgpu_ttm_gart_bind(adev, bo, flags);
>>> -    if (unlikely(r)) {
>>> -        ttm_bo_mem_put(bo, &tmp);
>>> -        return r;
>>> +        /* Bind pages */
>>> +        gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
>>> +            adev->gmc.gart_start;
>>> +        r = amdgpu_ttm_gart_bind(adev, bo, flags);
>>> +        if (unlikely(r)) {
>>> +            ttm_bo_mem_put(bo, &tmp);
>>> +            return r;
>>> +        }
>>> +
>>> +        ttm_bo_mem_put(bo, &bo->mem);
>>> +        bo->mem = tmp;
>>>       }
>>>
>>> -    ttm_bo_mem_put(bo, &bo->mem);
>>> -    bo->mem = tmp;
>>>       bo->offset = (bo->mem.start << PAGE_SHIFT) +
>>>           bo->bdev->man[bo->mem.mem_type].gpu_offset;
>>>
>>>
>
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[PATCH 5/7] drm/amdgpu: manually map the shadow BOs again

[Christian König]

Otherwise we won't be able to use the AGP aperture.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +----
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 5 +++++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 0cbf651a88a6..de990bdcdd6c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -163,10 +163,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
 
 	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 		places[c].fpfn = 0;
-		if (flags & AMDGPU_GEM_CREATE_SHADOW)
-			places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
-		else
-			places[c].lpfn = 0;
+		places[c].lpfn = 0;
 		places[c].flags = TTM_PL_FLAG_TT;
 		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 			places[c].flags |= TTM_PL_FLAG_WC |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index a3675c7b6190..abe1db4c63f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -346,6 +346,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			r = amdgpu_ttm_alloc_gart(&bo->tbo);
 			if (r)
 				break;
+			if (bo->shadow) {
+				r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
+				if (r)
+					break;
+			}
 			list_move(&bo_base->vm_status, &vm->relocated);
 		}
 	}
-- 
2.17.1

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Re: [PATCH 5/7] drm/amdgpu: manually map the shadow BOs again

[Zhang, Jerry (Junwei)]

On 08/29/2018 10:08 PM, Christian König wrote:
> Otherwise we won't be able to use the AGP aperture.

do you mean we use AGP for GTT shadow only now?

Jerry
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +----
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 5 +++++
>   2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 0cbf651a88a6..de990bdcdd6c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -163,10 +163,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
>
>   	if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>   		places[c].fpfn = 0;
> -		if (flags & AMDGPU_GEM_CREATE_SHADOW)
> -			places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
> -		else
> -			places[c].lpfn = 0;
> +		places[c].lpfn = 0;
>   		places[c].flags = TTM_PL_FLAG_TT;
>   		if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>   			places[c].flags |= TTM_PL_FLAG_WC |
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index a3675c7b6190..abe1db4c63f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -346,6 +346,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   			r = amdgpu_ttm_alloc_gart(&bo->tbo);
>   			if (r)
>   				break;
> +			if (bo->shadow) {
> +				r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
> +				if (r)
> +					break;
> +			}
>   			list_move(&bo_base->vm_status, &vm->relocated);
>   		}
>   	}
>
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Re: [PATCH 5/7] drm/amdgpu: manually map the shadow BOs again

[Christian König]

Am 30.08.2018 um 05:29 schrieb Zhang, Jerry (Junwei):
> On 08/29/2018 10:08 PM, Christian König wrote:
>> Otherwise we won't be able to use the AGP aperture.
>
> do you mean we use AGP for GTT shadow only now?

No, on older hw generations the page tables are usually larger than one 
PAGE.

So we need to work a bit more on this,
Christian.

>
> Jerry
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +----
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c     | 5 +++++
>>   2 files changed, 6 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> index 0cbf651a88a6..de990bdcdd6c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> @@ -163,10 +163,7 @@ void amdgpu_bo_placement_from_domain(struct 
>> amdgpu_bo *abo, u32 domain)
>>
>>       if (domain & AMDGPU_GEM_DOMAIN_GTT) {
>>           places[c].fpfn = 0;
>> -        if (flags & AMDGPU_GEM_CREATE_SHADOW)
>> -            places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
>> -        else
>> -            places[c].lpfn = 0;
>> +        places[c].lpfn = 0;
>>           places[c].flags = TTM_PL_FLAG_TT;
>>           if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
>>               places[c].flags |= TTM_PL_FLAG_WC |
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index a3675c7b6190..abe1db4c63f9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -346,6 +346,11 @@ int amdgpu_vm_validate_pt_bos(struct 
>> amdgpu_device *adev, struct amdgpu_vm *vm,
>>               r = amdgpu_ttm_alloc_gart(&bo->tbo);
>>               if (r)
>>                   break;
>> +            if (bo->shadow) {
>> +                r = amdgpu_ttm_alloc_gart(&bo->shadow->tbo);
>> +                if (r)
>> +                    break;
>> +            }
>>               list_move(&bo_base->vm_status, &vm->relocated);
>>           }
>>       }
>>

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[PATCH 6/7] drm/amdgpu: enable AGP aperture for GMC9

[Christian König]

Enable the old AGP aperture to avoid GART mappings.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 +++++-----
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  1 +
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 10 +++++-----
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3403ded39d13..ffd0ec9586d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -65,16 +65,16 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 {
 	uint64_t value;
 
-	/* Disable AGP. */
+	/* Program the AGP BAR */
 	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
+	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-		     adev->gmc.vram_start >> 18);
+		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
 	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-		     adev->gmc.vram_end >> 18);
+		     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
 
 	/* Set default page address. */
 	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 04d50893a6f2..719f45cdaf6a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -751,6 +751,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
 		base = mmhub_v1_0_get_fb_location(adev);
 	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
 	amdgpu_gmc_gart_location(adev, mc);
+	amdgpu_gmc_agp_location(adev, mc);
 	/* base offset of vram pages */
 	adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 5f6a9c85488f..73d7c075dd33 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -76,16 +76,16 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
 	uint64_t value;
 	uint32_t tmp;
 
-	/* Disable AGP. */
+	/* Program the AGP BAR */
 	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
-	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
-	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
+	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 
 	/* Program the system aperture low logical page number. */
 	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-		     adev->gmc.vram_start >> 18);
+		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
 	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-		     adev->gmc.vram_end >> 18);
+		     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
 
 	/* Set default page address. */
 	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
-- 
2.17.1

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Re: [PATCH 6/7] drm/amdgpu: enable AGP aperture for GMC9

[Zhang, Jerry (Junwei)]

On 08/29/2018 10:08 PM, Christian König wrote:
> Enable the old AGP aperture to avoid GART mappings.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 +++++-----
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  1 +
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 10 +++++-----
>   3 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 3403ded39d13..ffd0ec9586d1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -65,16 +65,16 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
>   {
>   	uint64_t value;
>
> -	/* Disable AGP. */
> +	/* Program the AGP BAR */
>   	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
> -	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
> -	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0xFFFFFFFF);
> +	WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> +	WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
>
>   	/* Program the system aperture low logical page number. */
>   	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> -		     adev->gmc.vram_start >> 18);
> +		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
>   	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> -		     adev->gmc.vram_end >> 18);
> +		     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
>
>   	/* Set default page address. */
>   	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 04d50893a6f2..719f45cdaf6a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -751,6 +751,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
>   		base = mmhub_v1_0_get_fb_location(adev);
>   	amdgpu_gmc_vram_location(adev, &adev->gmc, base);
>   	amdgpu_gmc_gart_location(adev, mc);
> +	amdgpu_gmc_agp_location(adev, mc);
>   	/* base offset of vram pages */
>   	adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
>   }
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 5f6a9c85488f..73d7c075dd33 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -76,16 +76,16 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
>   	uint64_t value;
>   	uint32_t tmp;
>
> -	/* Disable AGP. */
> +	/* Program the AGP BAR */
>   	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
> -	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
> -	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FFFFFF);
> +	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> +	WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
>
>   	/* Program the system aperture low logical page number. */
>   	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> -		     adev->gmc.vram_start >> 18);
> +		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
>   	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
> -		     adev->gmc.vram_end >> 18);
> +		     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
>
>   	/* Set default page address. */
>   	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
>
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[PATCH 7/7] drm/amdgpu: try to make kernel allocations USWC

[Christian König]

Not 100% sure if that is a good idea or not. In theory only the writeback BO
should be read most of the time, but who knows?

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index de990bdcdd6c..794c874309d0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -255,7 +255,8 @@ int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 	bp.byte_align = align;
 	bp.domain = domain;
 	bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
-		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+		AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 	bp.type = ttm_bo_type_kernel;
 	bp.resv = NULL;
 
-- 
2.17.1

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