* [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-26 23:03 ` Jonas Karlman 0 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman This series adds initial support for the Xunlong Orange Pi 3B board. The Xunlong Orange Pi 3B is a single-board computer based on the Rockchip RK3566 SoC. Schematic for Orange Pi 3B can be downloaded from: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html Changes in v2: - Add DT for v2.1 hw revision, rename initial DT to v1.1: - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) - Rename led node and move led pinctrl props - Use regulator-.* nodename for fixed regulators - Drop rockchip,mic-in-differential prop - Add cap-mmc-highspeed to sdhci node - Add no-mmc and no-sd to sdmmc1 node Jonas Karlman (2): dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B arm64: dts: rockchip: Add Xunlong Orange Pi 3B .../devicetree/bindings/arm/rockchip.yaml | 8 + arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ 5 files changed, 787 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi -- 2.45.2 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-26 23:03 ` Jonas Karlman 0 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman This series adds initial support for the Xunlong Orange Pi 3B board. The Xunlong Orange Pi 3B is a single-board computer based on the Rockchip RK3566 SoC. Schematic for Orange Pi 3B can be downloaded from: http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html Changes in v2: - Add DT for v2.1 hw revision, rename initial DT to v1.1: - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) - Rename led node and move led pinctrl props - Use regulator-.* nodename for fixed regulators - Drop rockchip,mic-in-differential prop - Add cap-mmc-highspeed to sdhci node - Add no-mmc and no-sd to sdmmc1 node Jonas Karlman (2): dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B arm64: dts: rockchip: Add Xunlong Orange Pi 3B .../devicetree/bindings/arm/rockchip.yaml | 8 + arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ 5 files changed, 787 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi -- 2.45.2 ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-26 23:03 ` Jonas Karlman -1 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Add devicetree binding for the Xunlong Orange Pi 3B board. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- v2: Add v1.1/v2.1 suffix to support new hw revision Acked-by tag was not collected because of this change. --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index bbb2d7c217fc..3710e06618bc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -988,6 +988,14 @@ properties: - const: wolfvision,rk3568-pf5 - const: rockchip,rk3568 + - description: Xunlong Orange Pi 3B + items: + - enum: + - xunlong,orangepi-3b-v1.1 + - xunlong,orangepi-3b-v2.1 + - const: xunlong,orangepi-3b + - const: rockchip,rk3566 + - description: Xunlong Orange Pi 5 Plus items: - const: xunlong,orangepi-5-plus -- 2.45.2 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-26 23:03 ` Jonas Karlman 0 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Add devicetree binding for the Xunlong Orange Pi 3B board. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- v2: Add v1.1/v2.1 suffix to support new hw revision Acked-by tag was not collected because of this change. --- Documentation/devicetree/bindings/arm/rockchip.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index bbb2d7c217fc..3710e06618bc 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -988,6 +988,14 @@ properties: - const: wolfvision,rk3568-pf5 - const: rockchip,rk3568 + - description: Xunlong Orange Pi 3B + items: + - enum: + - xunlong,orangepi-3b-v1.1 + - xunlong,orangepi-3b-v2.1 + - const: xunlong,orangepi-3b + - const: rockchip,rk3566 + - description: Xunlong Orange Pi 5 Plus items: - const: xunlong,orangepi-5-plus -- 2.45.2 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-27 7:47 ` Krzysztof Kozlowski -1 siblings, 0 replies; 22+ messages in thread From: Krzysztof Kozlowski @ 2024-06-27 7:47 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 27/06/2024 01:03, Jonas Karlman wrote: > Add devicetree binding for the Xunlong Orange Pi 3B board. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-27 7:47 ` Krzysztof Kozlowski 0 siblings, 0 replies; 22+ messages in thread From: Krzysztof Kozlowski @ 2024-06-27 7:47 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 27/06/2024 01:03, Jonas Karlman wrote: > Add devicetree binding for the Xunlong Orange Pi 3B board. > > Signed-off-by: Jonas Karlman <jonas@kwiboo.se> > --- Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-26 23:03 ` Jonas Karlman -1 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman The Xunlong Orange Pi 3B is a single-board computer based on the Rockchip RK3566 SoC. Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- v2: - Add DT for v2.1 hw revision, rename initial DT to v1.1: - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) - Rename led node and move led pinctrl props - Use regulator-.* nodename for fixed regulators - Drop rockchip,mic-in-differential prop - Add cap-mmc-highspeed to sdhci node - Add no-mmc and no-sd to sdmmc1 node Following issue is reported by dtbs_check and is fixed by series at [1]: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# [1] https://lore.kernel.org/all/20240622-rk809-fixes-v2-0-c0db420d3639@collabora.com/ --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ 4 files changed, 779 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ae0ae02f51e9..df5a74c407f4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinetab2-v0.1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 000000000000..074e93bd4b85 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v1.1"; + compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio5-supply = <&vcc_3v3>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 000000000000..d894bff41e61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v2.1"; + compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566"; + + vccio_phy1: regulator-1v8-vccio-phy { + compatible = "regulator-fixed"; + regulator-name = "vccio_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; +}; + +&pmu_io_domains { + vccio5-supply = <&vccio_phy1>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&uart1 { + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + interrupt-parent = <&gpio2>; + interrupts = <RK_PC0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi new file mode 100644 index 000000000000..d539570f531e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Xunlong Orange Pi 3B"; + compatible = "xunlong,orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc3v3_pcie30: regulator-3v3-vcc-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pins>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led: work-led { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_pins: pcie20-pins { + rockchip,pins = + <1 RK_PB0 4 &pcfg_pull_none>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie20_pwren: pcie20-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- 2.45.2 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-26 23:03 ` Jonas Karlman 0 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2024-06-26 23:03 UTC (permalink / raw) To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman The Xunlong Orange Pi 3B is a single-board computer based on the Rockchip RK3566 SoC. Add initial support for eMMC, SD-card, Ethernet, HDMI, PCIe and USB. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> --- v2: - Add DT for v2.1 hw revision, rename initial DT to v1.1: - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) - Rename led node and move led pinctrl props - Use regulator-.* nodename for fixed regulators - Drop rockchip,mic-in-differential prop - Add cap-mmc-highspeed to sdhci node - Add no-mmc and no-sd to sdmmc1 node Following issue is reported by dtbs_check and is fixed by series at [1]: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# [1] https://lore.kernel.org/all/20240622-rk809-fixes-v2-0-c0db420d3639@collabora.com/ --- arch/arm64/boot/dts/rockchip/Makefile | 2 + .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ 4 files changed, 779 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index ae0ae02f51e9..df5a74c407f4 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -81,6 +81,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v1.1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-orangepi-3b-v2.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinetab2-v0.1.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts new file mode 100644 index 000000000000..074e93bd4b85 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v1.1"; + compatible = "xunlong,orangepi-3b-v1.1", "xunlong,orangepi-3b", "rockchip,rk3566"; +}; + +&pmu_io_domains { + vccio5-supply = <&vcc_3v3>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts new file mode 100644 index 000000000000..d894bff41e61 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-orangepi-3b.dtsi" + +/ { + model = "Xunlong Orange Pi 3B v2.1"; + compatible = "xunlong,orangepi-3b-v2.1", "xunlong,orangepi-3b", "rockchip,rk3566"; + + vccio_phy1: regulator-1v8-vccio-phy { + compatible = "regulator-fixed"; + regulator-name = "vccio_phy1"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + }; +}; + +&pmu_io_domains { + vccio5-supply = <&vccio_phy1>; +}; + +&gmac1 { + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + reset-assert-us = <20000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&sdmmc1 { + #address-cells = <1>; + #size-cells = <0>; + + brcmf: wifi@1 { + compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD6 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host_h>; + }; +}; + +&uart1 { + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + interrupt-parent = <&gpio2>; + interrupts = <RK_PC0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wakeup"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_wake_host_h &host_wake_bt_h>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi new file mode 100644 index 000000000000..d539570f531e --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi @@ -0,0 +1,678 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/soc/rockchip,vop2.h> +#include "rk3566.dtsi" + +/ { + model = "Xunlong Orange Pi 3B"; + compatible = "xunlong,orangepi-3b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + + led-0 { + color = <LED_COLOR_ID_GREEN>; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc3v3_pcie30: regulator-3v3-vcc-pcie30 { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pwren>; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: regulator-3v3-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb_host: regulator-5v0-vcc-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: regulator-5v0-vcc-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren_h>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + post-power-on-delay-ms = <200>; + power-off-delay-us = <5000000>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clocks = <&cru I2S1_MCLKOUT_TX>; + clock-names = "mclk"; + clock-output-names = "rk809-clkout1", "rk809-clkout2"; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + #sound-dai-cells = <0>; + system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&pcie2x1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie20_pins>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + bluetooth { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_h: bt-wake-host-h { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + host_wake_bt_h: host-wake-bt-h { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led: work-led { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie20_pins: pcie20-pins { + rockchip,pins = + <1 RK_PB0 4 &pcfg_pull_none>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + pcie20_pwren: pcie20-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren_h: usb-otg-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_wake_host_h: wifi-wake-host-h { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + no-mmc; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sfc { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = <ROCKCHIP_VOP2_EP_HDMI0>; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; -- 2.45.2 ^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-28 0:01 ` kernel test robot -1 siblings, 0 replies; 22+ messages in thread From: kernel test robot @ 2024-06-28 0:01 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: oe-kbuild-all, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Hi Jonas, kernel test robot noticed the following build warnings: [auto build test WARNING on rockchip/for-next] [also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.10-rc5 next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Jonas-Karlman/dt-bindings-arm-rockchip-Add-Xunlong-Orange-Pi-3B/20240627-175050 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next patch link: https://lore.kernel.org/r/20240626230319.1425316-3-jonas%40kwiboo.se patch subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B config: arm64-randconfig-051-20240628 (https://download.01.org/0day-ci/archive/20240628/202406280724.E053qdhz-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.2.0 dtschema version: 2024.6.dev2+g3b69bad reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406280724.E053qdhz-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406280724.E053qdhz-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-28 0:01 ` kernel test robot 0 siblings, 0 replies; 22+ messages in thread From: kernel test robot @ 2024-06-28 0:01 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: oe-kbuild-all, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Hi Jonas, kernel test robot noticed the following build warnings: [auto build test WARNING on rockchip/for-next] [also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.10-rc5 next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Jonas-Karlman/dt-bindings-arm-rockchip-Add-Xunlong-Orange-Pi-3B/20240627-175050 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next patch link: https://lore.kernel.org/r/20240626230319.1425316-3-jonas%40kwiboo.se patch subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B config: arm64-randconfig-051-20240628 (https://download.01.org/0day-ci/archive/20240628/202406280724.E053qdhz-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.2.0 dtschema version: 2024.6.dev2+g3b69bad reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406280724.E053qdhz-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406280724.E053qdhz-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-28 10:49 ` kernel test robot -1 siblings, 0 replies; 22+ messages in thread From: kernel test robot @ 2024-06-28 10:49 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: oe-kbuild-all, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Hi Jonas, kernel test robot noticed the following build warnings: [auto build test WARNING on rockchip/for-next] [also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.10-rc5 next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Jonas-Karlman/dt-bindings-arm-rockchip-Add-Xunlong-Orange-Pi-3B/20240627-175050 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next patch link: https://lore.kernel.org/r/20240626230319.1425316-3-jonas%40kwiboo.se patch subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B config: arm64-randconfig-051-20240628 (https://download.01.org/0day-ci/archive/20240628/202406281834.nNnojcHy-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.2.0 dtschema version: 2024.6.dev3+g650bf2d reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406281834.nNnojcHy-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406281834.nNnojcHy-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-28 10:49 ` kernel test robot 0 siblings, 0 replies; 22+ messages in thread From: kernel test robot @ 2024-06-28 10:49 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: oe-kbuild-all, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel, Jonas Karlman Hi Jonas, kernel test robot noticed the following build warnings: [auto build test WARNING on rockchip/for-next] [also build test WARNING on robh/for-next krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.10-rc5 next-20240627] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/Jonas-Karlman/dt-bindings-arm-rockchip-Add-Xunlong-Orange-Pi-3B/20240627-175050 base: https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next patch link: https://lore.kernel.org/r/20240626230319.1425316-3-jonas%40kwiboo.se patch subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B config: arm64-randconfig-051-20240628 (https://download.01.org/0day-ci/archive/20240628/202406281834.nNnojcHy-lkp@intel.com/config) compiler: aarch64-linux-gcc (GCC) 13.2.0 dtschema version: 2024.6.dev3+g650bf2d reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240628/202406281834.nNnojcHy-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202406281834.nNnojcHy-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- >> arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2025-03-08 14:53 ` Arturas Moskvinas -1 siblings, 0 replies; 22+ messages in thread From: Arturas Moskvinas @ 2025-03-08 14:53 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 6/27/24 2:03 AM, Jonas Karlman wrote: > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. ...> + > +&gmac1 { > + phy-handle = <&rgmii_phy1>; > + status = "okay"; > +}; > + > +&mdio1 { > + rgmii_phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; Jonas, were you able to test V1.1 board's Ethernet? Whenever I start the board - Ethernet initialization fails with: ``` [ 21.140055] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) ``` But if reset is performed inside gmac - initialization succeeds. Eg. patch: ``` --- linux-6.12.17.orig/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts +++ linux-6.12.17/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -16,14 +16,14 @@ &gmac1 { phy-handle = <&rgmii_phy1>; status = "okay"; + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 200000>; }; &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-assert-us = <20000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; }; }; ``` > + reset-assert-us = <20000>; > + reset-deassert-us = <50000>; > + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > + }; > +}; Arturas Moskvinas ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2025-03-08 14:53 ` Arturas Moskvinas 0 siblings, 0 replies; 22+ messages in thread From: Arturas Moskvinas @ 2025-03-08 14:53 UTC (permalink / raw) To: Jonas Karlman, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 6/27/24 2:03 AM, Jonas Karlman wrote: > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. ...> + > +&gmac1 { > + phy-handle = <&rgmii_phy1>; > + status = "okay"; > +}; > + > +&mdio1 { > + rgmii_phy1: ethernet-phy@1 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <1>; Jonas, were you able to test V1.1 board's Ethernet? Whenever I start the board - Ethernet initialization fails with: ``` [ 21.140055] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19) ``` But if reset is performed inside gmac - initialization succeeds. Eg. patch: ``` --- linux-6.12.17.orig/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts +++ linux-6.12.17/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts @@ -16,14 +16,14 @@ &gmac1 { phy-handle = <&rgmii_phy1>; status = "okay"; + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 200000>; }; &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; - reset-assert-us = <20000>; - reset-deassert-us = <50000>; - reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; }; }; ``` > + reset-assert-us = <20000>; > + reset-deassert-us = <50000>; > + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > + }; > +}; Arturas Moskvinas _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2025-03-08 14:53 ` Arturas Moskvinas @ 2025-03-08 16:34 ` Jonas Karlman -1 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2025-03-08 16:34 UTC (permalink / raw) To: Arturas Moskvinas Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Hi Arturas, On 2025-03-08 15:53, Arturas Moskvinas wrote: > On 6/27/24 2:03 AM, Jonas Karlman wrote: > >> The Xunlong Orange Pi 3B is a single-board computer based on the >> Rockchip RK3566 SoC. > ...> + >> +&gmac1 { >> + phy-handle = <&rgmii_phy1>; >> + status = "okay"; >> +}; >> + >> +&mdio1 { >> + rgmii_phy1: ethernet-phy@1 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <1>; > > Jonas, were you able to test V1.1 board's Ethernet? Yes, I have both a v1.1.1 and v2.1 hw revision of this board and Ethernet should be working on both hw revisions. > > Whenever I start the board - Ethernet initialization fails with: > ``` > [ 21.140055] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: > Cannot attach to PHY (error: -19) > ``` This is because of a reset issue with Ethernet PHYs in Linux, see [1]. Two workarounds: 1. Let boot firmware reset the PHY before Linux, i.e. use U-Boot v2024.10 or newer. 2. Use a ethernet-phy-id compatible with correct phy-id to force Linux to attach the PHY. I suggest you try to wipe U-Boot from SPI flash on your board and update to use U-Boot v2025.01 and try again. > > But if reset is performed inside gmac - initialization succeeds. Use of deprecated snps,reset- props is not a proper fix for this issue, instead Linux could use an improve Ethernet PHY initialization handling and ensuring the PHY is reset before it tries to read a phy-id from it. [1] https://lore.kernel.org/r/47d55aca-bee6-810f-379f-9431649fefa6@kwiboo.se/ Regards, Jonas > > Eg. patch: > ``` > --- > linux-6.12.17.orig/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > +++ linux-6.12.17/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > @@ -16,14 +16,14 @@ > &gmac1 { > phy-handle = <&rgmii_phy1>; > status = "okay"; > + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > + snps,reset-active-low; > + snps,reset-delays-us = <0 50000 200000>; > }; > > &mdio1 { > rgmii_phy1: ethernet-phy@1 { > compatible = "ethernet-phy-ieee802.3-c22"; > reg = <1>; > - reset-assert-us = <20000>; > - reset-deassert-us = <50000>; > - reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > }; > }; > ``` >> + reset-assert-us = <20000>; >> + reset-deassert-us = <50000>; >> + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; >> + }; >> +}; > > > Arturas Moskvinas ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2025-03-08 16:34 ` Jonas Karlman 0 siblings, 0 replies; 22+ messages in thread From: Jonas Karlman @ 2025-03-08 16:34 UTC (permalink / raw) To: Arturas Moskvinas Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel Hi Arturas, On 2025-03-08 15:53, Arturas Moskvinas wrote: > On 6/27/24 2:03 AM, Jonas Karlman wrote: > >> The Xunlong Orange Pi 3B is a single-board computer based on the >> Rockchip RK3566 SoC. > ...> + >> +&gmac1 { >> + phy-handle = <&rgmii_phy1>; >> + status = "okay"; >> +}; >> + >> +&mdio1 { >> + rgmii_phy1: ethernet-phy@1 { >> + compatible = "ethernet-phy-ieee802.3-c22"; >> + reg = <1>; > > Jonas, were you able to test V1.1 board's Ethernet? Yes, I have both a v1.1.1 and v2.1 hw revision of this board and Ethernet should be working on both hw revisions. > > Whenever I start the board - Ethernet initialization fails with: > ``` > [ 21.140055] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: > Cannot attach to PHY (error: -19) > ``` This is because of a reset issue with Ethernet PHYs in Linux, see [1]. Two workarounds: 1. Let boot firmware reset the PHY before Linux, i.e. use U-Boot v2024.10 or newer. 2. Use a ethernet-phy-id compatible with correct phy-id to force Linux to attach the PHY. I suggest you try to wipe U-Boot from SPI flash on your board and update to use U-Boot v2025.01 and try again. > > But if reset is performed inside gmac - initialization succeeds. Use of deprecated snps,reset- props is not a proper fix for this issue, instead Linux could use an improve Ethernet PHY initialization handling and ensuring the PHY is reset before it tries to read a phy-id from it. [1] https://lore.kernel.org/r/47d55aca-bee6-810f-379f-9431649fefa6@kwiboo.se/ Regards, Jonas > > Eg. patch: > ``` > --- > linux-6.12.17.orig/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > +++ linux-6.12.17/arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > @@ -16,14 +16,14 @@ > &gmac1 { > phy-handle = <&rgmii_phy1>; > status = "okay"; > + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > + snps,reset-active-low; > + snps,reset-delays-us = <0 50000 200000>; > }; > > &mdio1 { > rgmii_phy1: ethernet-phy@1 { > compatible = "ethernet-phy-ieee802.3-c22"; > reg = <1>; > - reset-assert-us = <20000>; > - reset-deassert-us = <50000>; > - reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; > }; > }; > ``` >> + reset-assert-us = <20000>; >> + reset-deassert-us = <50000>; >> + reset-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; >> + }; >> +}; > > > Arturas Moskvinas _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2025-03-08 16:34 ` Jonas Karlman @ 2025-03-08 19:03 ` Arturas Moskvinas -1 siblings, 0 replies; 22+ messages in thread From: Arturas Moskvinas @ 2025-03-08 19:03 UTC (permalink / raw) To: Jonas Karlman Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 3/8/25 6:34 PM, Jonas Karlman wrote: > This is because of a reset issue with Ethernet PHYs in Linux, see [1]. > > Two workarounds: > 1. Let boot firmware reset the PHY before Linux, i.e. use U-Boot > v2024.10 or newer. > 2. Use a ethernet-phy-id compatible with correct phy-id to force Linux > to attach the PHY. > > I suggest you try to wipe U-Boot from SPI flash on your board and update > to use U-Boot v2025.01 and try again. Wiping board SPI flash which contained old U-boot and using 2025.01 from SD card fixed issue hence DTS is OK. Though I do not remember that I ever wrote anything into SPI flash in first place (I touched board almost year ago so potentially forgot about it) maybe it was shipped like that with the board... Arturas Moskvinas ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2025-03-08 19:03 ` Arturas Moskvinas 0 siblings, 0 replies; 22+ messages in thread From: Arturas Moskvinas @ 2025-03-08 19:03 UTC (permalink / raw) To: Jonas Karlman Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree, linux-arm-kernel, linux-rockchip, linux-kernel On 3/8/25 6:34 PM, Jonas Karlman wrote: > This is because of a reset issue with Ethernet PHYs in Linux, see [1]. > > Two workarounds: > 1. Let boot firmware reset the PHY before Linux, i.e. use U-Boot > v2024.10 or newer. > 2. Use a ethernet-phy-id compatible with correct phy-id to force Linux > to attach the PHY. > > I suggest you try to wipe U-Boot from SPI flash on your board and update > to use U-Boot v2025.01 and try again. Wiping board SPI flash which contained old U-boot and using 2025.01 from SD card fixed issue hence DTS is OK. Though I do not remember that I ever wrote anything into SPI flash in first place (I touched board almost year ago so potentially forgot about it) maybe it was shipped like that with the board... Arturas Moskvinas _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-06-27 14:34 ` Rob Herring (Arm) -1 siblings, 0 replies; 22+ messages in thread From: Rob Herring (Arm) @ 2024-06-27 14:34 UTC (permalink / raw) To: Jonas Karlman Cc: linux-rockchip, Conor Dooley, Krzysztof Kozlowski, linux-arm-kernel, linux-kernel, devicetree, Heiko Stuebner On Wed, 26 Jun 2024 23:03:10 +0000, Jonas Karlman wrote: > This series adds initial support for the Xunlong Orange Pi 3B board. > > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. > > Schematic for Orange Pi 3B can be downloaded from: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html > > Changes in v2: > - Add DT for v2.1 hw revision, rename initial DT to v1.1: > - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) > - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) > - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) > - Rename led node and move led pinctrl props > - Use regulator-.* nodename for fixed regulators > - Drop rockchip,mic-in-differential prop > - Add cap-mmc-highspeed to sdhci node > - Add no-mmc and no-sd to sdmmc1 node > > Jonas Karlman (2): > dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B > arm64: dts: rockchip: Add Xunlong Orange Pi 3B > > .../devicetree/bindings/arm/rockchip.yaml | 8 + > arch/arm64/boot/dts/rockchip/Makefile | 2 + > .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + > .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ > .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ > 5 files changed, 787 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi > > -- > 2.45.2 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y rockchip/rk3566-orangepi-3b-v1.1.dtb rockchip/rk3566-orangepi-3b-v2.1.dtb' for 20240626230319.1425316-1-jonas@kwiboo.se: arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-06-27 14:34 ` Rob Herring (Arm) 0 siblings, 0 replies; 22+ messages in thread From: Rob Herring (Arm) @ 2024-06-27 14:34 UTC (permalink / raw) To: Jonas Karlman Cc: linux-rockchip, Conor Dooley, Krzysztof Kozlowski, linux-arm-kernel, linux-kernel, devicetree, Heiko Stuebner On Wed, 26 Jun 2024 23:03:10 +0000, Jonas Karlman wrote: > This series adds initial support for the Xunlong Orange Pi 3B board. > > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. > > Schematic for Orange Pi 3B can be downloaded from: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html > > Changes in v2: > - Add DT for v2.1 hw revision, rename initial DT to v1.1: > - Ethernet phy io voltage: 3v3 (v1.1) / 1v8 (v2.1) > - Etherent reset gpios: GPIO3_C2 (v1.1) / GPIO4_C4 (v2.1) > - WiFi/BT: CDW-20U5622 (v1.1) / AP6256 (v2.1) > - Rename led node and move led pinctrl props > - Use regulator-.* nodename for fixed regulators > - Drop rockchip,mic-in-differential prop > - Add cap-mmc-highspeed to sdhci node > - Add no-mmc and no-sd to sdmmc1 node > > Jonas Karlman (2): > dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B > arm64: dts: rockchip: Add Xunlong Orange Pi 3B > > .../devicetree/bindings/arm/rockchip.yaml | 8 + > arch/arm64/boot/dts/rockchip/Makefile | 2 + > .../dts/rockchip/rk3566-orangepi-3b-v1.1.dts | 29 + > .../dts/rockchip/rk3566-orangepi-3b-v2.1.dts | 70 ++ > .../boot/dts/rockchip/rk3566-orangepi-3b.dtsi | 678 ++++++++++++++++++ > 5 files changed, 787 insertions(+) > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dts > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dts > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b.dtsi > > -- > 2.45.2 > > > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y rockchip/rk3566-orangepi-3b-v1.1.dtb rockchip/rk3566-orangepi-3b-v2.1.dtb' for 20240626230319.1425316-1-jonas@kwiboo.se: arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v2.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# arch/arm64/boot/dts/rockchip/rk3566-orangepi-3b-v1.1.dtb: pmic@20: '#sound-dai-cells', 'assigned-clock-parents', 'assigned-clocks', 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/mfd/rockchip,rk809.yaml# ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B 2024-06-26 23:03 ` Jonas Karlman @ 2024-07-08 22:27 ` Heiko Stuebner -1 siblings, 0 replies; 22+ messages in thread From: Heiko Stuebner @ 2024-07-08 22:27 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Jonas Karlman, Conor Dooley Cc: Heiko Stuebner, linux-arm-kernel, linux-rockchip, devicetree, linux-kernel On Wed, 26 Jun 2024 23:03:10 +0000, Jonas Karlman wrote: > This series adds initial support for the Xunlong Orange Pi 3B board. > > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. > > Schematic for Orange Pi 3B can be downloaded from: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html > > [...] Applied, thanks! [1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B commit: 6d48d5045d99a938b42ee875ae6be80b832e6d77 [2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B commit: d79d713d602e8b32cf935ddfdf61769cb74ba1dc Best regards, -- Heiko Stuebner <heiko@sntech.de> _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B @ 2024-07-08 22:27 ` Heiko Stuebner 0 siblings, 0 replies; 22+ messages in thread From: Heiko Stuebner @ 2024-07-08 22:27 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Jonas Karlman, Conor Dooley Cc: Heiko Stuebner, linux-arm-kernel, linux-rockchip, devicetree, linux-kernel On Wed, 26 Jun 2024 23:03:10 +0000, Jonas Karlman wrote: > This series adds initial support for the Xunlong Orange Pi 3B board. > > The Xunlong Orange Pi 3B is a single-board computer based on the > Rockchip RK3566 SoC. > > Schematic for Orange Pi 3B can be downloaded from: > http://www.orangepi.org/html/hardWare/computerAndMicrocontrollers/service-and-support/Orange-Pi-3B.html > > [...] Applied, thanks! [1/2] dt-bindings: arm: rockchip: Add Xunlong Orange Pi 3B commit: 6d48d5045d99a938b42ee875ae6be80b832e6d77 [2/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B commit: d79d713d602e8b32cf935ddfdf61769cb74ba1dc Best regards, -- Heiko Stuebner <heiko@sntech.de> ^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2025-03-08 19:16 UTC | newest] Thread overview: 22+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-06-26 23:03 [PATCH v2 0/2] arm64: dts: rockchip: Add Xunlong Orange Pi 3B Jonas Karlman 2024-06-26 23:03 ` Jonas Karlman 2024-06-26 23:03 ` [PATCH v2 1/2] dt-bindings: arm: " Jonas Karlman 2024-06-26 23:03 ` Jonas Karlman 2024-06-27 7:47 ` Krzysztof Kozlowski 2024-06-27 7:47 ` Krzysztof Kozlowski 2024-06-26 23:03 ` [PATCH v2 2/2] arm64: dts: " Jonas Karlman 2024-06-26 23:03 ` Jonas Karlman 2024-06-28 0:01 ` kernel test robot 2024-06-28 0:01 ` kernel test robot 2024-06-28 10:49 ` kernel test robot 2024-06-28 10:49 ` kernel test robot 2025-03-08 14:53 ` Arturas Moskvinas 2025-03-08 14:53 ` Arturas Moskvinas 2025-03-08 16:34 ` Jonas Karlman 2025-03-08 16:34 ` Jonas Karlman 2025-03-08 19:03 ` Arturas Moskvinas 2025-03-08 19:03 ` Arturas Moskvinas 2024-06-27 14:34 ` [PATCH v2 0/2] " Rob Herring (Arm) 2024-06-27 14:34 ` Rob Herring (Arm) 2024-07-08 22:27 ` Heiko Stuebner 2024-07-08 22:27 ` Heiko Stuebner
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