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From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Alistair Francis" <alistair.francis@wdc.com>,
	"Bob Eshleman" <bobbyeshleman@gmail.com>,
	"Connor Davis" <connojdavis@gmail.com>,
	"Andrew Cooper" <andrew.cooper3@citrix.com>,
	"Anthony PERARD" <anthony.perard@vates.tech>,
	"Michal Orzel" <michal.orzel@amd.com>,
	"Julien Grall" <julien@xen.org>,
	"Roger Pau Monné" <roger.pau@citrix.com>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	"Romain Caritey" <Romain.Caritey@microchip.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH v1 09/14] xen/riscv: aplic_init() implementation
Date: Fri, 18 Apr 2025 13:31:56 +0200	[thread overview]
Message-ID: <5d211530-fe1b-4f83-a8a9-cf41603e4fd3@gmail.com> (raw)
In-Reply-To: <2795e63a-fc37-4ab9-8348-ab2f609f1734@suse.com>

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On 4/17/25 5:30 PM, Jan Beulich wrote:
> On 17.04.2025 17:21, Oleksii Kurochko wrote:
>> On 4/16/25 12:30 PM, Jan Beulich wrote:
>>> On 16.04.2025 12:15, Oleksii Kurochko wrote:
>>>> On 4/14/25 12:04 PM, Jan Beulich wrote:
>>>>> On 08.04.2025 17:57, Oleksii Kurochko wrote:
>>>>>> +    rc = dt_property_read_u32(node, "msi-parent", &imsic_phandle);
>>>>>> +    if ( !rc )
>>>>>> +        panic("%s: IDC mode not supported\n", node->full_name);
>>>>>> +
>>>>>> +    imsic_node = dt_find_node_by_phandle(imsic_phandle);
>>>>>> +    if ( !imsic_node )
>>>>>> +        panic("%s: unable to find IMSIC node\n", node->full_name);
>>>>>> +
>>>>>> +    /* check imsic mode */
>>>>>> +    rc = dt_property_read_u32_array(imsic_node, "interrupts-extended",
>>>>>> +                                    irq_range, ARRAY_SIZE(irq_range));
>>>>>> +    if ( rc && (rc != -EOVERFLOW) )
>>>>>> +        panic("%s: unable to find interrupt-extended in %s node\n",
>>>>>> +               node->full_name, imsic_node->full_name);
>>>>> Why exactly is EOVERFLOW tolerable here?
>>>> QEMU generates two IMSIC device tree nodes: one for M-mode and one for S-mode.
>>>> For the hypervisor, we don’t really care about the M-mode IMSIC node — we're only
>>>> interested in the S-mode IMSIC node.
>>>>
>>>> The IMSIC node includes this information in the|"interrupts-extended"| property,
>>>> which has the following format:
>>>>      interrupt-extended = {<interrupt-controller-phandle>, <machine_mode>},...
>>>> The number of such|<phandle, mode>| pairs depends on the number of CPUs the platform has.
>>>>
>>>> For our purposes, to determine whether the IMSIC node corresponds to M-mode or not, it’s sufficient to read only the first pair and check the mode like this:
>>>>
>>>>      if ( irq_range[1] == IRQ_M_EXT )
>>>>
>>>> Thereby dt_property_read_u32_array() will return -EOVERFLOW in the case when a platfrom
>>>> has more then one CPU as we passed irq_range[2] as an argument but the amount of values
>>>> in "interrupts-extended" property will be (2 * CPUS_NUM).
>>>>
>>>> I can update the comment above dt_property_read_u32_array() for more clearness.
>>> Yet my question remains: Why would it be okay to ignore the remaining entries,
>>> and hence accept -EOVERFLOW as kind-of-success?
>> Because for other entries the IMSIC mode will be the same and the difference will be only in
>> interrupt controller's phandle
> And we can blindly take this for granted? Would you mind extending the
> comment that's there to include this aspect?

I tried to compile dtc with different modes in interrupt-extends and compilation doesn't failed, so
it's not really granted.
Just to be sure, I'll check all items of interrupts-extend not just the first one.

~ Oleksii

>> which we don't care about in this function and cares only about
>> in imisic_init(), look at usage of imsic_get_parent_hartid().

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  reply	other threads:[~2025-04-18 11:32 UTC|newest]

Thread overview: 79+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-08 15:57 [PATCH v1 00/14] riscv: introduce basic UART support and interrupts for hypervisor mode Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 01/14] xen/riscv: implement get_s_time() Oleksii Kurochko
2025-04-10 12:52   ` Jan Beulich
2025-04-14 14:50     ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 02/14] xen/riscv: introduce smp_clear_cpu_maps() Oleksii Kurochko
2025-04-10 13:10   ` Jan Beulich
2025-04-14 15:05     ` Oleksii Kurochko
2025-04-14 15:13       ` Jan Beulich
2025-04-08 15:57 ` [PATCH v1 03/14] xen/riscv: introduce ioremap() Oleksii Kurochko
2025-04-10 15:13   ` Jan Beulich
2025-04-15 10:29     ` Oleksii Kurochko
2025-04-15 11:02       ` Jan Beulich
2025-04-17 14:20         ` Oleksii Kurochko
2025-04-17 14:24           ` Jan Beulich
2025-04-17 14:37             ` Oleksii Kurochko
2025-04-17 14:49               ` Jan Beulich
2025-04-22  8:40                 ` Oleksii Kurochko
2025-04-22  9:14                   ` Jan Beulich
2025-04-24 13:30                     ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 04/14] xen/riscv: introduce init_IRQ() Oleksii Kurochko
2025-04-10 15:25   ` Jan Beulich
2025-04-15 10:36     ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 05/14] xen/riscv: introduce platform_get_irq() Oleksii Kurochko
2025-04-10 15:35   ` Jan Beulich
2025-04-15 11:11     ` Oleksii Kurochko
2025-04-15 11:23       ` Jan Beulich
2025-04-17 14:43         ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 06/14] xen/riscv: riscv_of_processor_hartid() implementation Oleksii Kurochko
2025-04-10 15:53   ` Jan Beulich
2025-04-15 13:39     ` Oleksii Kurochko
2025-04-15 13:45       ` Jan Beulich
2025-04-25 17:07         ` Oleksii Kurochko
2025-04-28  6:31           ` Jan Beulich
2025-04-28 10:43             ` Oleksii Kurochko
2025-04-28 11:09               ` Jan Beulich
2025-04-08 15:57 ` [PATCH v1 07/14] xen/riscv: Introduce intc_hw_operations abstraction Oleksii Kurochko
2025-04-10 16:02   ` Jan Beulich
2025-04-15 15:01     ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 08/14] xen/riscv: imsic_init() implementation Oleksii Kurochko
2025-04-14  9:32   ` Jan Beulich
2025-04-15 19:11     ` Oleksii Kurochko
     [not found]       ` <9a13c625-cd33-485d-a91f-9f005522b5a4@suse.com>
2025-04-23 11:44         ` Oleksii Kurochko
2025-04-29  8:24         ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 09/14] xen/riscv: aplic_init() implementation Oleksii Kurochko
2025-04-14 10:04   ` Jan Beulich
2025-04-16 10:15     ` Oleksii Kurochko
2025-04-16 10:30       ` Jan Beulich
2025-04-17 15:21         ` Oleksii Kurochko
2025-04-17 15:30           ` Jan Beulich
2025-04-18 11:31             ` Oleksii Kurochko [this message]
2025-04-08 15:57 ` [PATCH v1 10/14] xen/riscv: implementation of aplic and imsic operations Oleksii Kurochko
2025-04-15 12:46   ` Jan Beulich
2025-04-16 19:05     ` Oleksii Kurochko
2025-04-17  6:25       ` Jan Beulich
2025-04-28  8:12         ` Oleksii Kurochko
2025-04-28  8:54           ` Jan Beulich
2025-04-30 16:07             ` Oleksii Kurochko
2025-04-15 14:53   ` Jan Beulich
2025-04-18 10:43     ` Oleksii Kurochko
2025-04-22  7:02       ` Jan Beulich
2025-04-25 19:31         ` Oleksii Kurochko
2025-04-28  6:35           ` Jan Beulich
2025-04-08 15:57 ` [PATCH v1 11/14] xen/riscv: add external interrupt handling for hypervisor mode Oleksii Kurochko
2025-04-15 14:42   ` Jan Beulich
2025-04-17  8:44     ` Oleksii Kurochko
2025-04-17  9:13       ` Oleksii Kurochko
2025-04-08 15:57 ` [PATCH v1 12/14] xen/riscv: implement setup_irq() Oleksii Kurochko
2025-04-15 15:55   ` Jan Beulich
2025-04-17 10:10     ` Oleksii Kurochko
2025-04-17 11:51       ` Jan Beulich
2025-04-08 15:57 ` [PATCH v1 13/14] xen/riscv: initialize interrupt controller Oleksii Kurochko
2025-04-15 15:59   ` Jan Beulich
2025-04-17 10:11     ` Oleksii Kurochko
2025-04-30 15:34       ` Oleksii Kurochko
2025-04-30 15:39         ` Jan Beulich
2025-04-08 15:57 ` [PATCH v1 14/14] xen/riscv: add basic UART support Oleksii Kurochko
2025-04-15 16:03   ` Jan Beulich
2025-04-17 10:31     ` Oleksii Kurochko
2025-04-17 11:52       ` Jan Beulich

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