Re: [PATCH 0/5] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC

[Mario Limonciello <superm1@kernel.org>]

On 5/20/26 14:11, Shyam Sundar S K wrote:
> The series introduces the necessary device identification, refactors SMU
> mailbox register handling for better maintainability, and configures the
> SoC-specific register offsets required for SMU communication.
> 
> Patch 1 adds the ACPI and PCI device IDs for the new SoC variant.
> 
> Patch 2 refactors SMU mailbox offset initialization into a dedicated helper
> function to improve code organization as the number of supported SoCs grows.
> 
> Patch 3 extends the SMU register refactoring to store all three SMU registers
> (message, argument, response) in the device structure, replacing hardcoded
> register addresses.
> 
> Patch 4 adds the SoC-specific SMU register addresses for the 1Ah Family 80h,
> completing the register configuration needed for SMU communication.
> 
> Patch 5 enables s0i3 support for the new SoC by adding it to the OS_HINT
> and idle mask handling code paths.
> 
> This series has been tested on AMD 1Ah Family 80h hardware to verify proper
> driver binding, SMU communication, and s2idle functionality.
> 
> Shyam Sundar S K (5):
>    platform/x86/amd/pmc: Add ACPI ID AMDI000C for AMD 1Ah Family SoC
>    platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different
>      CPU families
>    platform/x86/amd/pmc: Refactor SMU register handling to be
>      device-specific
>    platform/x86/amd/pmc: Add SMU register support for 1Ah 80h SoC
>    platform/x86/amd/pmc: Add OS_HINT command for AMD Family 1Ah Model 80h
> 
>   drivers/platform/x86/amd/pmc/pmc.c | 45 +++++++++++++++++++++++++-----
>   drivers/platform/x86/amd/pmc/pmc.h | 12 ++++++++
>   2 files changed, 50 insertions(+), 7 deletions(-)
> 

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>