[PATCH 0/5] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC

[PATCH 0/5] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC

[Shyam Sundar S K]

The series introduces the necessary device identification, refactors SMU
mailbox register handling for better maintainability, and configures the
SoC-specific register offsets required for SMU communication.

Patch 1 adds the ACPI and PCI device IDs for the new SoC variant.

Patch 2 refactors SMU mailbox offset initialization into a dedicated helper
function to improve code organization as the number of supported SoCs grows.

Patch 3 extends the SMU register refactoring to store all three SMU registers
(message, argument, response) in the device structure, replacing hardcoded
register addresses.

Patch 4 adds the SoC-specific SMU register addresses for the 1Ah Family 80h,
completing the register configuration needed for SMU communication.

Patch 5 enables s0i3 support for the new SoC by adding it to the OS_HINT
and idle mask handling code paths.

This series has been tested on AMD 1Ah Family 80h hardware to verify proper
driver binding, SMU communication, and s2idle functionality.

Shyam Sundar S K (5):
  platform/x86/amd/pmc: Add ACPI ID AMDI000C for AMD 1Ah Family SoC
  platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different
    CPU families
  platform/x86/amd/pmc: Refactor SMU register handling to be
    device-specific
  platform/x86/amd/pmc: Add SMU register support for 1Ah 80h SoC
  platform/x86/amd/pmc: Add OS_HINT command for AMD Family 1Ah Model 80h

 drivers/platform/x86/amd/pmc/pmc.c | 45 +++++++++++++++++++++++++-----
 drivers/platform/x86/amd/pmc/pmc.h | 12 ++++++++
 2 files changed, 50 insertions(+), 7 deletions(-)

-- 
2.34.1

[PATCH 1/5] platform/x86/amd/pmc: Add ACPI ID AMDI000C for AMD 1Ah Family SoC

[Shyam Sundar S K]

Add support for the AMD 1Ah Family 80h SoC by adding the ACPI ID
AMDI000C and PCI Device ID 0x115b to the amd-pmc driver.

Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
 drivers/platform/x86/amd/pmc/pmc.c | 2 ++
 drivers/platform/x86/amd/pmc/pmc.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index cae3fcafd4d7..7200f19088fe 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -722,6 +722,7 @@ static const struct pci_device_id pmc_pci_ids[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_VG) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) },
 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M80H_ROOT) },
 	{ }
 };
 
@@ -825,6 +826,7 @@ static const struct acpi_device_id amd_pmc_acpi_ids[] = {
 	{"AMDI0009", 0},
 	{"AMDI000A", 0},
 	{"AMDI000B", 0},
+	{"AMDI000C", 0},
 	{"AMD0004", 0},
 	{"AMD0005", 0},
 	{ }
diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
index fe3f53eb5955..969b62162470 100644
--- a/drivers/platform/x86/amd/pmc/pmc.h
+++ b/drivers/platform/x86/amd/pmc/pmc.h
@@ -165,6 +165,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev);
 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507
 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122
 #define PCI_DEVICE_ID_AMD_MP2_STB	0x172c
+#define PCI_DEVICE_ID_AMD_1AH_M80H_ROOT	0x115b
 
 int amd_stb_s2d_init(struct amd_pmc_dev *dev);
 int amd_stb_read(struct amd_pmc_dev *dev, u32 *buf);
-- 
2.34.1

[PATCH 2/5] platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different CPU families

[Shyam Sundar S K]

Different AMD CPU families have different SMU mailbox register offsets.
Add a helper function amd_pmc_get_smu_mb() to populate the appropriate
SMU message offset based on the CPU ID during probe.

This infrastructure will help support future features that require
communication with the SMU through the correct mailbox address.

Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
 drivers/platform/x86/amd/pmc/pmc.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index 7200f19088fe..7c80fb445138 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -101,6 +101,24 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
 	iowrite32(val, dev->regbase + reg_offset);
 }
 
+static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
+{
+	switch (dev->cpu_id) {
+	case AMD_CPU_ID_PCO:
+	case AMD_CPU_ID_RN:
+	case AMD_CPU_ID_VG:
+	case AMD_CPU_ID_YC:
+	case AMD_CPU_ID_CB:
+	case AMD_CPU_ID_PS:
+		dev->smu_msg = 0x538;
+		break;
+	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
+	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
+		dev->smu_msg = 0x938;
+		break;
+	}
+}
+
 static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
 {
 	switch (dev->cpu_id) {
@@ -111,12 +129,10 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
 	case AMD_CPU_ID_CB:
 		dev->num_ips = 12;
 		dev->ips_ptr = soc15_ip_blk;
-		dev->smu_msg = 0x538;
 		break;
 	case AMD_CPU_ID_PS:
 		dev->num_ips = 21;
 		dev->ips_ptr = soc15_ip_blk;
-		dev->smu_msg = 0x538;
 		break;
 	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
 	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
@@ -127,7 +143,6 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
 			dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
 			dev->ips_ptr = soc15_ip_blk;
 		}
-		dev->smu_msg = 0x938;
 		break;
 	}
 }
@@ -782,6 +797,9 @@ static int amd_pmc_probe(struct platform_device *pdev)
 	/* Get num of IP blocks within the SoC */
 	amd_pmc_get_ip_info(dev);
 
+	/* Populate SMU msg offset */
+	amd_pmc_get_smu_mb(dev);
+
 	platform_set_drvdata(pdev, dev);
 	if (IS_ENABLED(CONFIG_SUSPEND)) {
 		err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
-- 
2.34.1

Re: [PATCH 2/5] platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different CPU families

[Ilpo Järvinen]

On Thu, 21 May 2026, Shyam Sundar S K wrote:

> Different AMD CPU families have different SMU mailbox register offsets.
> Add a helper function amd_pmc_get_smu_mb() to populate the appropriate
> SMU message offset based on the CPU ID during probe.
> 
> This infrastructure will help support future features that require
> communication with the SMU through the correct mailbox address.
> 
> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> ---
>  drivers/platform/x86/amd/pmc/pmc.c | 24 +++++++++++++++++++++---
>  1 file changed, 21 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> index 7200f19088fe..7c80fb445138 100644
> --- a/drivers/platform/x86/amd/pmc/pmc.c
> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> @@ -101,6 +101,24 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
>  	iowrite32(val, dev->regbase + reg_offset);
>  }
>  
> +static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
> +{
> +	switch (dev->cpu_id) {
> +	case AMD_CPU_ID_PCO:
> +	case AMD_CPU_ID_RN:
> +	case AMD_CPU_ID_VG:
> +	case AMD_CPU_ID_YC:
> +	case AMD_CPU_ID_CB:
> +	case AMD_CPU_ID_PS:
> +		dev->smu_msg = 0x538;
> +		break;
> +	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
> +	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> +		dev->smu_msg = 0x938;
> +		break;
> +	}
> +}
> +
>  static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>  {
>  	switch (dev->cpu_id) {
> @@ -111,12 +129,10 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>  	case AMD_CPU_ID_CB:
>  		dev->num_ips = 12;
>  		dev->ips_ptr = soc15_ip_blk;
> -		dev->smu_msg = 0x538;
>  		break;
>  	case AMD_CPU_ID_PS:
>  		dev->num_ips = 21;
>  		dev->ips_ptr = soc15_ip_blk;
> -		dev->smu_msg = 0x538;
>  		break;
>  	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
>  	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> @@ -127,7 +143,6 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>  			dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
>  			dev->ips_ptr = soc15_ip_blk;
>  		}
> -		dev->smu_msg = 0x938;
>  		break;
>  	}
>  }
> @@ -782,6 +797,9 @@ static int amd_pmc_probe(struct platform_device *pdev)
>  	/* Get num of IP blocks within the SoC */
>  	amd_pmc_get_ip_info(dev);
>  
> +	/* Populate SMU msg offset */
> +	amd_pmc_get_smu_mb(dev);
> +
>  	platform_set_drvdata(pdev, dev);
>  	if (IS_ENABLED(CONFIG_SUSPEND)) {
>  		err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);

Could these difference should be recorded into an info struct so we don't 
need to make a function for each difference?

-- 
 i.

Re: [PATCH 2/5] platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different CPU families

[Shyam Sundar S K]

On 5/22/2026 18:06, Ilpo Järvinen wrote:
> On Thu, 21 May 2026, Shyam Sundar S K wrote:
> 
>> Different AMD CPU families have different SMU mailbox register offsets.
>> Add a helper function amd_pmc_get_smu_mb() to populate the appropriate
>> SMU message offset based on the CPU ID during probe.
>>
>> This infrastructure will help support future features that require
>> communication with the SMU through the correct mailbox address.
>>
>> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
>> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
>> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
>> ---
>>  drivers/platform/x86/amd/pmc/pmc.c | 24 +++++++++++++++++++++---
>>  1 file changed, 21 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
>> index 7200f19088fe..7c80fb445138 100644
>> --- a/drivers/platform/x86/amd/pmc/pmc.c
>> +++ b/drivers/platform/x86/amd/pmc/pmc.c
>> @@ -101,6 +101,24 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
>>  	iowrite32(val, dev->regbase + reg_offset);
>>  }
>>  
>> +static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
>> +{
>> +	switch (dev->cpu_id) {
>> +	case AMD_CPU_ID_PCO:
>> +	case AMD_CPU_ID_RN:
>> +	case AMD_CPU_ID_VG:
>> +	case AMD_CPU_ID_YC:
>> +	case AMD_CPU_ID_CB:
>> +	case AMD_CPU_ID_PS:
>> +		dev->smu_msg = 0x538;
>> +		break;
>> +	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
>> +	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
>> +		dev->smu_msg = 0x938;
>> +		break;
>> +	}
>> +}
>> +
>>  static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>>  {
>>  	switch (dev->cpu_id) {
>> @@ -111,12 +129,10 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>>  	case AMD_CPU_ID_CB:
>>  		dev->num_ips = 12;
>>  		dev->ips_ptr = soc15_ip_blk;
>> -		dev->smu_msg = 0x538;
>>  		break;
>>  	case AMD_CPU_ID_PS:
>>  		dev->num_ips = 21;
>>  		dev->ips_ptr = soc15_ip_blk;
>> -		dev->smu_msg = 0x538;
>>  		break;
>>  	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
>>  	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
>> @@ -127,7 +143,6 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
>>  			dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
>>  			dev->ips_ptr = soc15_ip_blk;
>>  		}
>> -		dev->smu_msg = 0x938;
>>  		break;
>>  	}
>>  }
>> @@ -782,6 +797,9 @@ static int amd_pmc_probe(struct platform_device *pdev)
>>  	/* Get num of IP blocks within the SoC */
>>  	amd_pmc_get_ip_info(dev);
>>  
>> +	/* Populate SMU msg offset */
>> +	amd_pmc_get_smu_mb(dev);
>> +
>>  	platform_set_drvdata(pdev, dev);
>>  	if (IS_ENABLED(CONFIG_SUSPEND)) {
>>  		err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
> 
> Could these difference should be recorded into an info struct so we don't 
> need to make a function for each difference?
> 

I could not understand your comment here, can you please elaborate
what do you mean by info struct?

Is it something like this?

+static const struct amd_pmc_cpu_info amd_1ah_cpu_info = {
+	.smu_msg	= 0x938,
+	.num_ips	= ARRAY_SIZE(soc15_ip_blk),
+	.ips_ptr	= soc15_ip_blk,
+};

+

+static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = {
+	.smu_msg	= 0x938,
+	.num_ips	= ARRAY_SIZE(soc15_ip_blk_v2),
+	.ips_ptr	= soc15_ip_blk_v2,
+};


+static void amd_pmc_get_cpu_info(struct amd_pmc_dev *dev)
{
...

+	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
+	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
+		if (boot_cpu_data.x86_model == 0x70)
+			info = &amd_1ah_m70_cpu_info;
+		else
+			info = &amd_1ah_cpu_info;
+		break;
+	default:
+		return;
+	}
+
+	dev->smu_msg = info->smu_msg;
+	dev->num_ips = info->num_ips;
+	dev->ips_ptr = info->ips_ptr;

...
}

static int amd_pmc_probe(struct platform_device *pdev)
{

...

-	amd_pmc_get_ip_info(dev);

+	amd_pmc_get_cpu_info(dev);


...
}


Thanks,
Shyam

Re: [PATCH 2/5] platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different CPU families

[Ilpo Järvinen]

[-- Attachment #1: Type: text/plain, Size: 4809 bytes --]

On Wed, 27 May 2026, Shyam Sundar S K wrote:
> On 5/22/2026 18:06, Ilpo Järvinen wrote:
> > On Thu, 21 May 2026, Shyam Sundar S K wrote:
> > 
> >> Different AMD CPU families have different SMU mailbox register offsets.
> >> Add a helper function amd_pmc_get_smu_mb() to populate the appropriate
> >> SMU message offset based on the CPU ID during probe.
> >>
> >> This infrastructure will help support future features that require
> >> communication with the SMU through the correct mailbox address.
> >>
> >> Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
> >> Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
> >> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
> >> ---
> >>  drivers/platform/x86/amd/pmc/pmc.c | 24 +++++++++++++++++++++---
> >>  1 file changed, 21 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
> >> index 7200f19088fe..7c80fb445138 100644
> >> --- a/drivers/platform/x86/amd/pmc/pmc.c
> >> +++ b/drivers/platform/x86/amd/pmc/pmc.c
> >> @@ -101,6 +101,24 @@ static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u3
> >>  	iowrite32(val, dev->regbase + reg_offset);
> >>  }
> >>  
> >> +static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
> >> +{
> >> +	switch (dev->cpu_id) {
> >> +	case AMD_CPU_ID_PCO:
> >> +	case AMD_CPU_ID_RN:
> >> +	case AMD_CPU_ID_VG:
> >> +	case AMD_CPU_ID_YC:
> >> +	case AMD_CPU_ID_CB:
> >> +	case AMD_CPU_ID_PS:
> >> +		dev->smu_msg = 0x538;
> >> +		break;
> >> +	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
> >> +	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> >> +		dev->smu_msg = 0x938;
> >> +		break;
> >> +	}
> >> +}
> >> +
> >>  static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> >>  {
> >>  	switch (dev->cpu_id) {
> >> @@ -111,12 +129,10 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> >>  	case AMD_CPU_ID_CB:
> >>  		dev->num_ips = 12;
> >>  		dev->ips_ptr = soc15_ip_blk;
> >> -		dev->smu_msg = 0x538;
> >>  		break;
> >>  	case AMD_CPU_ID_PS:
> >>  		dev->num_ips = 21;
> >>  		dev->ips_ptr = soc15_ip_blk;
> >> -		dev->smu_msg = 0x538;
> >>  		break;
> >>  	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
> >>  	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> >> @@ -127,7 +143,6 @@ static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> >>  			dev->num_ips = ARRAY_SIZE(soc15_ip_blk);
> >>  			dev->ips_ptr = soc15_ip_blk;
> >>  		}
> >> -		dev->smu_msg = 0x938;
> >>  		break;
> >>  	}
> >>  }
> >> @@ -782,6 +797,9 @@ static int amd_pmc_probe(struct platform_device *pdev)
> >>  	/* Get num of IP blocks within the SoC */
> >>  	amd_pmc_get_ip_info(dev);
> >>  
> >> +	/* Populate SMU msg offset */
> >> +	amd_pmc_get_smu_mb(dev);
> >> +
> >>  	platform_set_drvdata(pdev, dev);
> >>  	if (IS_ENABLED(CONFIG_SUSPEND)) {
> >>  		err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
> > 
> > Could these difference should be recorded into an info struct so we don't 
> > need to make a function for each difference?
> > 
> 
> I could not understand your comment here, can you please elaborate
> what do you mean by info struct?
> 
> Is it something like this?
> 
> +static const struct amd_pmc_cpu_info amd_1ah_cpu_info = {
> +	.smu_msg	= 0x938,
> +	.num_ips	= ARRAY_SIZE(soc15_ip_blk),
> +	.ips_ptr	= soc15_ip_blk,
> +};
> 
> +
> 
> +static const struct amd_pmc_cpu_info amd_1ah_m70_cpu_info = {
> +	.smu_msg	= 0x938,
> +	.num_ips	= ARRAY_SIZE(soc15_ip_blk_v2),
> +	.ips_ptr	= soc15_ip_blk_v2,
> +};
>
> +static void amd_pmc_get_cpu_info(struct amd_pmc_dev *dev)
> {
> ...
> 
> +	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
> +	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
> +		if (boot_cpu_data.x86_model == 0x70)
> +			info = &amd_1ah_m70_cpu_info;
> +		else
> +			info = &amd_1ah_cpu_info;
> +		break;
> +	default:
> +		return;
> +	}
> +
> +	dev->smu_msg = info->smu_msg;
> +	dev->num_ips = info->num_ips;
> +	dev->ips_ptr = info->ips_ptr;


Something alone the lines of above but you could also change PCI_DEVICE() 
-> PCI_DEVICE_DATA(..., &xx_info) and get the struct from there per each 
ID. The variations related to boot_cpu_data.x86_model == 0x70 is a bit 
problematic though so you'll need to handle that case separately from 
getting rest directly from the id table.

There's also amd_pmc_get_os_hint() which could be covered using this 
approach, I think.

If store the info pointer into dev, you don't need to have those fields 
copied to dev anymore.

> 
> ...
> }
> 
> static int amd_pmc_probe(struct platform_device *pdev)
> {
> 
> ...
> 
> -	amd_pmc_get_ip_info(dev);
> 
> +	amd_pmc_get_cpu_info(dev);
> 
> 
> ...
> }
> 
> 
> Thanks,
> Shyam
> 

-- 
 i.

[PATCH 3/5] platform/x86/amd/pmc: Refactor SMU register handling to be device-specific

[Shyam Sundar S K]

Currently, the driver uses hardcoded register addresses for SMU
communication (argument and response registers) and a mix of hardcoded
values and device-specific storage for the message register.

Refactor the code to store all three SMU communication registers
(message, argument and response) in the device structure. This approach
provides better consistency and flexibility for supporting SoCs with
different register layouts.

Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
 drivers/platform/x86/amd/pmc/pmc.c | 16 ++++++++++------
 drivers/platform/x86/amd/pmc/pmc.h |  6 ++++++
 2 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index 7c80fb445138..55dc88c93614 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -110,11 +110,15 @@ static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
 	case AMD_CPU_ID_YC:
 	case AMD_CPU_ID_CB:
 	case AMD_CPU_ID_PS:
-		dev->smu_msg = 0x538;
+		dev->smu_msg = AMD_PMC_REGISTER_MESSAGE;
+		dev->smu_arg = AMD_PMC_REGISTER_ARGUMENT;
+		dev->smu_rsp = AMD_PMC_REGISTER_RESPONSE;
 		break;
 	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
 	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
-		dev->smu_msg = 0x938;
+		dev->smu_msg = AMD_PMC_REGISTER_MSG_1AH_20H;
+		dev->smu_arg = AMD_PMC_REGISTER_ARGUMENT;
+		dev->smu_rsp = AMD_PMC_REGISTER_RESPONSE;
 		break;
 	}
 }
@@ -441,8 +445,8 @@ static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
 		response = dev->stb_arg.resp;
 	} else {
 		message = dev->smu_msg;
-		argument = AMD_PMC_REGISTER_ARGUMENT;
-		response = AMD_PMC_REGISTER_RESPONSE;
+		argument = dev->smu_arg;
+		response = dev->smu_rsp;
 	}
 
 	value = amd_pmc_reg_read(dev, response);
@@ -468,8 +472,8 @@ int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool r
 		response = dev->stb_arg.resp;
 	} else {
 		message = dev->smu_msg;
-		argument = AMD_PMC_REGISTER_ARGUMENT;
-		response = AMD_PMC_REGISTER_RESPONSE;
+		argument = dev->smu_arg;
+		response = dev->smu_rsp;
 	}
 
 	/* Wait until we get a valid response */
diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
index 969b62162470..0c3c31f73fdf 100644
--- a/drivers/platform/x86/amd/pmc/pmc.h
+++ b/drivers/platform/x86/amd/pmc/pmc.h
@@ -17,6 +17,10 @@
 /* SMU communication registers */
 #define AMD_PMC_REGISTER_RESPONSE	0x980
 #define AMD_PMC_REGISTER_ARGUMENT	0x9BC
+#define AMD_PMC_REGISTER_MESSAGE	0x538
+
+/* SMU communication registers for 1Ah 20h SoC */
+#define AMD_PMC_REGISTER_MSG_1AH_20H	0x938
 
 /* PMC Scratch Registers */
 #define AMD_PMC_SCRATCH_REG_CZN		0x94
@@ -102,6 +106,8 @@ struct amd_pmc_dev {
 	const struct amd_pmc_bit_map *ips_ptr;
 	u32 num_ips;
 	u32 smu_msg;
+	u32 smu_arg;
+	u32 smu_rsp;
 /* SMU version information */
 	u8 smu_program;
 	u8 major;
-- 
2.34.1

[PATCH 4/5] platform/x86/amd/pmc: Add SMU register support for 1Ah 80h SoC

[Shyam Sundar S K]

The AMD 1Ah 80h SoC uses different set of SMU communication registers
compared to earlier AMD SoCs. Add support for these SoC-specific
register addresses.

Update amd_pmc_get_smu_mb() to initialize the device structure with
these registers when PCI_DEVICE_ID_AMD_1AH_M80H_ROOT is detected.

Co-developed-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Sanket Goswami <Sanket.Goswami@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
 drivers/platform/x86/amd/pmc/pmc.c | 5 +++++
 drivers/platform/x86/amd/pmc/pmc.h | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index 55dc88c93614..9620b7cbd371 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -120,6 +120,11 @@ static void amd_pmc_get_smu_mb(struct amd_pmc_dev *dev)
 		dev->smu_arg = AMD_PMC_REGISTER_ARGUMENT;
 		dev->smu_rsp = AMD_PMC_REGISTER_RESPONSE;
 		break;
+	case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
+		dev->smu_msg = AMD_PMC_REGISTER_MSG_1AH_80H;
+		dev->smu_arg = AMD_PMC_REGISTER_ARG_1AH_80H;
+		dev->smu_rsp = AMD_PMC_REGISTER_RSP_1AH_80H;
+		break;
 	}
 }
 
diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h
index 0c3c31f73fdf..425ceac3ad72 100644
--- a/drivers/platform/x86/amd/pmc/pmc.h
+++ b/drivers/platform/x86/amd/pmc/pmc.h
@@ -22,6 +22,11 @@
 /* SMU communication registers for 1Ah 20h SoC */
 #define AMD_PMC_REGISTER_MSG_1AH_20H	0x938
 
+/* SMU communication registers for 1Ah 80h SoC */
+#define AMD_PMC_REGISTER_MSG_1AH_80H	0xA10
+#define AMD_PMC_REGISTER_ARG_1AH_80H	0xA18
+#define AMD_PMC_REGISTER_RSP_1AH_80H	0xA14
+
 /* PMC Scratch Registers */
 #define AMD_PMC_SCRATCH_REG_CZN		0x94
 #define AMD_PMC_SCRATCH_REG_YC		0xD14
-- 
2.34.1

[PATCH 5/5] platform/x86/amd/pmc: Add OS_HINT command for AMD Family 1Ah Model 80h

[Shyam Sundar S K]

Add PCI_DEVICE_ID_AMD_1AH_M80H_ROOT to the AMD PMC driver to enable
s0i3 support for AMD Family 1Ah Model 80h SoC.

This includes:
  - Adding the device ID to amd_pmc_idlemask_read() for reading the
    idle mask from the appropriate scratch register.
  - Adding the device ID to amd_pmc_get_os_hint() to get the
    correct OS hint message.

Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
---
 drivers/platform/x86/amd/pmc/pmc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c
index 9620b7cbd371..eff1afbee223 100644
--- a/drivers/platform/x86/amd/pmc/pmc.c
+++ b/drivers/platform/x86/amd/pmc/pmc.c
@@ -391,6 +391,7 @@ static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
 		break;
 	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
 	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
+	case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
 		val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH);
 		break;
 	default:
@@ -548,6 +549,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
 	case AMD_CPU_ID_PS:
 	case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT:
 	case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT:
+	case PCI_DEVICE_ID_AMD_1AH_M80H_ROOT:
 		return MSG_OS_HINT_RN;
 	}
 	return -EINVAL;
-- 
2.34.1

Re: [PATCH 0/5] platform/x86/amd/pmc: Add support for AMD 1Ah Family 80h SoC

[Mario Limonciello]

On 5/20/26 14:11, Shyam Sundar S K wrote:
> The series introduces the necessary device identification, refactors SMU
> mailbox register handling for better maintainability, and configures the
> SoC-specific register offsets required for SMU communication.
> 
> Patch 1 adds the ACPI and PCI device IDs for the new SoC variant.
> 
> Patch 2 refactors SMU mailbox offset initialization into a dedicated helper
> function to improve code organization as the number of supported SoCs grows.
> 
> Patch 3 extends the SMU register refactoring to store all three SMU registers
> (message, argument, response) in the device structure, replacing hardcoded
> register addresses.
> 
> Patch 4 adds the SoC-specific SMU register addresses for the 1Ah Family 80h,
> completing the register configuration needed for SMU communication.
> 
> Patch 5 enables s0i3 support for the new SoC by adding it to the OS_HINT
> and idle mask handling code paths.
> 
> This series has been tested on AMD 1Ah Family 80h hardware to verify proper
> driver binding, SMU communication, and s2idle functionality.
> 
> Shyam Sundar S K (5):
>    platform/x86/amd/pmc: Add ACPI ID AMDI000C for AMD 1Ah Family SoC
>    platform/x86/amd/pmc: Add SMU mailbox offset retrieval for different
>      CPU families
>    platform/x86/amd/pmc: Refactor SMU register handling to be
>      device-specific
>    platform/x86/amd/pmc: Add SMU register support for 1Ah 80h SoC
>    platform/x86/amd/pmc: Add OS_HINT command for AMD Family 1Ah Model 80h
> 
>   drivers/platform/x86/amd/pmc/pmc.c | 45 +++++++++++++++++++++++++-----
>   drivers/platform/x86/amd/pmc/pmc.h | 12 ++++++++
>   2 files changed, 50 insertions(+), 7 deletions(-)
> 

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>