* [PATCH 1/3] MIPS: Make DIEI support as a config option
@ 2020-01-13 10:14 Jiaxun Yang
2020-01-13 10:15 ` [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2 Jiaxun Yang
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jiaxun Yang @ 2020-01-13 10:14 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, paul.burton, linux-kernel, Jiaxun Yang
DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by
MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as
Loongson-3A1000. Thus we make it as a config option to allow disable it at
compile time with CPU_MIPSR2 selected.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 9 +++++++++
arch/mips/include/asm/irqflags.h | 6 +++---
arch/mips/lib/mips-atomic.c | 4 ++--
3 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4b83507499f4..c3103f4eeafa 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2111,12 +2111,14 @@ config CPU_MIPSR2
bool
default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
select CPU_HAS_RIXI
+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select MIPS_SPRAM
config CPU_MIPSR6
bool
default y if CPU_MIPS32_R6 || CPU_MIPS64_R6
select CPU_HAS_RIXI
+ select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
select HAVE_ARCH_BITREVERSE
select MIPS_ASID_BITS_VARIABLE
select MIPS_CRC_SUPPORT
@@ -2579,6 +2581,13 @@ config XKS01
config CPU_HAS_RIXI
bool
+config CPU_HAS_DIEI
+ depends on !CPU_DIEI_BROKEN
+ bool
+
+config CPU_DIEI_BROKEN
+ bool
+
config CPU_HAS_LOAD_STORE_LR
bool
help
diff --git a/arch/mips/include/asm/irqflags.h b/arch/mips/include/asm/irqflags.h
index c4728bbdf15b..47a8ffc0b413 100644
--- a/arch/mips/include/asm/irqflags.h
+++ b/arch/mips/include/asm/irqflags.h
@@ -18,7 +18,7 @@
#include <asm/compiler.h>
#include <asm/hazards.h>
-#if defined(CONFIG_CPU_MIPSR2) || defined (CONFIG_CPU_MIPSR6)
+#if defined(CONFIG_CPU_HAS_DIEI)
static inline void arch_local_irq_disable(void)
{
@@ -94,7 +94,7 @@ static inline void arch_local_irq_restore(unsigned long flags)
void arch_local_irq_disable(void);
unsigned long arch_local_irq_save(void);
void arch_local_irq_restore(unsigned long flags);
-#endif /* CONFIG_CPU_MIPSR2 || CONFIG_CPU_MIPSR6 */
+#endif /* CONFIG_CPU_HAS_DIEI */
static inline void arch_local_irq_enable(void)
{
@@ -102,7 +102,7 @@ static inline void arch_local_irq_enable(void)
" .set push \n"
" .set reorder \n"
" .set noat \n"
-#if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)
+#if defined(CONFIG_CPU_HAS_DIEI)
" ei \n"
#else
" mfc0 $1,$12 \n"
diff --git a/arch/mips/lib/mips-atomic.c b/arch/mips/lib/mips-atomic.c
index 5530070e0d05..de03838b343b 100644
--- a/arch/mips/lib/mips-atomic.c
+++ b/arch/mips/lib/mips-atomic.c
@@ -15,7 +15,7 @@
#include <linux/export.h>
#include <linux/stringify.h>
-#if !defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_MIPSR6)
+#if !defined(CONFIG_CPU_HAS_DIEI)
/*
* For cli() we have to insert nops to make sure that the new value
@@ -110,4 +110,4 @@ notrace void arch_local_irq_restore(unsigned long flags)
}
EXPORT_SYMBOL(arch_local_irq_restore);
-#endif /* !CONFIG_CPU_MIPSR2 && !CONFIG_CPU_MIPSR6 */
+#endif /* !CONFIG_CPU_HAS_DIEI */
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2
2020-01-13 10:14 [PATCH 1/3] MIPS: Make DIEI support as a config option Jiaxun Yang
@ 2020-01-13 10:15 ` Jiaxun Yang
2020-01-13 10:15 ` [PATCH 3/3] MIPS: Loongson64: Disable exec hazard Jiaxun Yang
2020-01-23 19:44 ` [PATCH 1/3] MIPS: Make DIEI support as a config option Paul Burton
2 siblings, 0 replies; 4+ messages in thread
From: Jiaxun Yang @ 2020-01-13 10:15 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, paul.burton, linux-kernel, Jiaxun Yang
Despite early sample of Loongson-3A1000, the whole Loongson64 family have
implemented all the features required by MIPS64 Release2. Thus we decide to
bump the ISA option to R2.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 6 ++++--
arch/mips/include/asm/hazards.h | 4 ++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c3103f4eeafa..d0b727daddb3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1443,11 +1443,15 @@ config CPU_LOONGSON64
bool "Loongson 64-bit CPU"
depends on SYS_HAS_CPU_LOONGSON64
select ARCH_HAS_PHYS_TO_DMA
+ select CPU_MIPSR2
+ select CPU_HAS_PREFETCH
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select CPU_SUPPORTS_MSA
select CPU_HAS_LOAD_STORE_LR
+ select CPU_DIEI_BROKEN if !LOONGSON3_ENHANCEMENT
+ select CPU_MIPSR2_IRQ_VI
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_ASID_BITS_VARIABLE
@@ -1465,8 +1469,6 @@ config CPU_LOONGSON64
config LOONGSON3_ENHANCEMENT
bool "New Loongson-3 CPU Enhancements"
default n
- select CPU_MIPSR2
- select CPU_HAS_PREFETCH
depends on CPU_LOONGSON64
help
New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index a4f48b0f5541..a0b92205f933 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -23,7 +23,7 @@
* TLB hazards
*/
#if (defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6)) && \
- !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_LOONGSON3_ENHANCEMENT)
+ !defined(CONFIG_CPU_CAVIUM_OCTEON) && !defined(CONFIG_CPU_LOONGSON64)
/*
* MIPSR2 defines ehb for hazard avoidance
@@ -158,7 +158,7 @@ do { \
} while (0)
#elif defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \
- defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_LOONGSON3_ENHANCEMENT) || \
+ defined(CONFIG_CPU_LOONGSON2EF) || defined(CONFIG_CPU_LOONGSON64) || \
defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_XLR)
/*
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 3/3] MIPS: Loongson64: Disable exec hazard
2020-01-13 10:14 [PATCH 1/3] MIPS: Make DIEI support as a config option Jiaxun Yang
2020-01-13 10:15 ` [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2 Jiaxun Yang
@ 2020-01-13 10:15 ` Jiaxun Yang
2020-01-23 19:44 ` [PATCH 1/3] MIPS: Make DIEI support as a config option Paul Burton
2 siblings, 0 replies; 4+ messages in thread
From: Jiaxun Yang @ 2020-01-13 10:15 UTC (permalink / raw)
To: linux-mips; +Cc: chenhc, paul.burton, linux-kernel, Jiaxun Yang
Loongson64 has hardware mechanism to prevent hazard issue,
so we can simply disable exec hazard in cpu-features.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
index 7dc8d75445a9..23aa8ed7cb9e 100644
--- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h
@@ -46,5 +46,6 @@
#define cpu_has_wsbh 1
#define cpu_has_ic_fills_f_dc 1
#define cpu_hwrena_impl_bits 0xc0000000
+#define cpu_has_mips_r2_exec_hazard 0
#endif /* __ASM_MACH_LOONGSON64_CPU_FEATURE_OVERRIDES_H */
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] MIPS: Make DIEI support as a config option
2020-01-13 10:14 [PATCH 1/3] MIPS: Make DIEI support as a config option Jiaxun Yang
2020-01-13 10:15 ` [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2 Jiaxun Yang
2020-01-13 10:15 ` [PATCH 3/3] MIPS: Loongson64: Disable exec hazard Jiaxun Yang
@ 2020-01-23 19:44 ` Paul Burton
2 siblings, 0 replies; 4+ messages in thread
From: Paul Burton @ 2020-01-23 19:44 UTC (permalink / raw)
To: Jiaxun Yang
Cc: linux-mips, chenhc, paul.burton, linux-kernel, Jiaxun Yang,
linux-mips
Hello,
Jiaxun Yang wrote:
> DI(Disable Interrupt) and EI(Enable Interrupt) instructions is required by
> MIPSR2/MIPSR6, however, it appears to be buggy on some processors such as
> Loongson-3A1000. Thus we make it as a config option to allow disable it at
> compile time with CPU_MIPSR2 selected.
Series applied to mips-next.
> MIPS: Make DIEI support as a config option
> commit ba9196d2e005
> https://git.kernel.org/mips/c/ba9196d2e005
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> MIPS: Loongson64: Bump ISA level to MIPSR2
> commit 51522217f65f
> https://git.kernel.org/mips/c/51522217f65f
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> MIPS: Loongson64: Disable exec hazard
> commit 1306cc0a3091
> https://git.kernel.org/mips/c/1306cc0a3091
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paulburton@kernel.org to report it. ]
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-01-23 19:44 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-01-13 10:14 [PATCH 1/3] MIPS: Make DIEI support as a config option Jiaxun Yang
2020-01-13 10:15 ` [PATCH 2/3] MIPS: Loongson64: Bump ISA level to MIPSR2 Jiaxun Yang
2020-01-13 10:15 ` [PATCH 3/3] MIPS: Loongson64: Disable exec hazard Jiaxun Yang
2020-01-23 19:44 ` [PATCH 1/3] MIPS: Make DIEI support as a config option Paul Burton
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.