* [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements
@ 2020-01-22 10:58 Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 1/5] MIPS: don't explicitly select LIBFDT in Kconfig Alexander Lobakin
` (5 more replies)
0 siblings, 6 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
This patchset aims mainly at MIPS and Generic MIPS Kconfig optimizations
except for the last patch that removes redundant BASE_BAUD override for
Generic MIPS. If it should go out of this series, please let me know.
All changes were fully tested on Generic MIPS32R2 board, but I admit
there potentionally might be any non-critical issues on other systems
(unlikely though).
Alexander Lobakin (5):
MIPS: don't explicitly select LIBFDT in Kconfig
MIPS: generic: don't unconditionally select PINCTRL
MIPS: make CPU_HAS_LOAD_STORE_LR opt-out
MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically
(again)
Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic
kernel"
arch/mips/Kconfig | 60 ++++++-------------
arch/mips/configs/generic/board-ocelot.config | 1 +
arch/mips/include/asm/Kbuild | 1 +
arch/mips/include/asm/serial.h | 18 ------
arch/mips/kernel/unaligned.c | 36 +++++------
arch/mips/lib/memcpy.S | 14 ++---
arch/mips/lib/memset.S | 16 ++---
7 files changed, 52 insertions(+), 94 deletions(-)
delete mode 100644 arch/mips/include/asm/serial.h
--
2.25.0
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH mips-next 1/5] MIPS: don't explicitly select LIBFDT in Kconfig
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
@ 2020-01-22 10:58 ` Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 2/5] MIPS: generic: don't unconditionally select PINCTRL Alexander Lobakin
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
It gets selected anyway through USE_OF -> OF_EARLY_FLATTREE ->
OF_FLATTREE -> LIBFDT, no need to double-check.
Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
---
arch/mips/Kconfig | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 4b83507499f4..b937a883b029 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -111,7 +111,6 @@ config MIPS_GENERIC
select DMA_PERDEV_COHERENT
select HAVE_PCI
select IRQ_MIPS_CPU
- select LIBFDT
select MIPS_AUTO_PFN_OFFSET
select MIPS_CPU_SCACHE
select MIPS_GIC
@@ -404,7 +403,6 @@ config MACH_INGENIC
select GENERIC_IRQ_CHIP
select BUILTIN_DTB if MIPS_NO_APPENDED_DTB
select USE_OF
- select LIBFDT
config LANTIQ
bool "Lantiq based platforms"
@@ -511,7 +509,6 @@ config MACH_PISTACHIO
select DMA_NONCOHERENT
select GPIOLIB
select IRQ_MIPS_CPU
- select LIBFDT
select MFD_SYSCON
select MIPS_CPU_SCACHE
select MIPS_GIC
@@ -549,7 +546,6 @@ config MIPS_MALTA
select I8253
select I8259
select IRQ_MIPS_CPU
- select LIBFDT
select MIPS_BONITO64
select MIPS_CPU_SCACHE
select MIPS_GIC
@@ -981,7 +977,6 @@ config CAVIUM_OCTEON_SOC
select ZONE_DMA32
select HOLES_IN_ZONE
select GPIOLIB
- select LIBFDT
select USE_OF
select ARCH_SPARSEMEM_ENABLE
select SYS_SUPPORTS_SMP
--
2.25.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH mips-next 2/5] MIPS: generic: don't unconditionally select PINCTRL
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 1/5] MIPS: don't explicitly select LIBFDT in Kconfig Alexander Lobakin
@ 2020-01-22 10:58 ` Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 3/5] MIPS: make CPU_HAS_LOAD_STORE_LR opt-out Alexander Lobakin
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
CONFIG_PINCTRL was converted from hidden selectable to a visible option
with commit d219b924611a ("pinctrl: change Kconfig PINCTRL variable to
a menuconfig"). Remove unconditional select and enable this symbol in
Ocelot config, which currently is the only user among generic boards.
Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
---
arch/mips/Kconfig | 1 -
arch/mips/configs/generic/board-ocelot.config | 1 +
2 files changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b937a883b029..c5498146bd3b 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -117,7 +117,6 @@ config MIPS_GENERIC
select MIPS_L1_CACHE_SHIFT_7
select NO_EXCEPT_FILL
select PCI_DRIVERS_GENERIC
- select PINCTRL
select SMP_UP if SMP
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
index 1134fbb99fc2..7626f2a75b03 100644
--- a/arch/mips/configs/generic/board-ocelot.config
+++ b/arch/mips/configs/generic/board-ocelot.config
@@ -41,6 +41,7 @@ CONFIG_SPI_DESIGNWARE=y
CONFIG_SPI_DW_MMIO=y
CONFIG_SPI_SPIDEV=y
+CONFIG_PINCTRL=y
CONFIG_PINCTRL_OCELOT=y
CONFIG_GPIO_SYSFS=y
--
2.25.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH mips-next 3/5] MIPS: make CPU_HAS_LOAD_STORE_LR opt-out
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 1/5] MIPS: don't explicitly select LIBFDT in Kconfig Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 2/5] MIPS: generic: don't unconditionally select PINCTRL Alexander Lobakin
@ 2020-01-22 10:58 ` Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 4/5] MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically (again) Alexander Lobakin
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
CPU_HAS_LOAD_STORE_LR was introduced in 932afdeec18b ("MIPS: Add Kconfig
variable for CPUs with unaligned load/store instructions") to make code
in kernel/unaligned.c and lib/mem{cpy,set}.S more intuitive and give a
possibility to easily add new CPUs without these instruction sets in
future.
Hovewer, this variant is not optimal for mainly two reasons:
* For now, we have 20+ CPUs with such instructions and only two (MIPS R6)
without. It will obviously be more effective and straightforward to
have an option for these two rather than for the rest.
* You can easily miss the fact that you need to select this option when
adding a new CPU, while all processors lacking these sets are
well-known, so the probability of missing something is way much lower.
We can address both points by turning CPU_HAS_LOAD_STORE_LR into opt-out
CPU_NO_LOAD_STORE_LR. This also makes MIPS root Kconfig more clear and
understandable.
Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
---
arch/mips/Kconfig | 34 +++++++---------------------------
arch/mips/kernel/unaligned.c | 36 ++++++++++++++++++------------------
arch/mips/lib/memcpy.S | 14 +++++++-------
arch/mips/lib/memset.S | 16 ++++++++--------
4 files changed, 40 insertions(+), 60 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c5498146bd3b..8ff846ef2345 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1218,8 +1218,7 @@ config NO_IOPORT_MAP
def_bool n
config GENERIC_CSUM
- bool
- default y if !CPU_HAS_LOAD_STORE_LR
+ def_bool CPU_NO_LOAD_STORE_LR
config GENERIC_ISA_DMA
bool
@@ -1441,7 +1440,6 @@ config CPU_LOONGSON64
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select CPU_SUPPORTS_MSA
- select CPU_HAS_LOAD_STORE_LR
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select MIPS_ASID_BITS_VARIABLE
@@ -1537,7 +1535,6 @@ config CPU_MIPS32_R1
bool "MIPS32 Release 1"
depends on SYS_HAS_CPU_MIPS32_R1
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
help
@@ -1555,7 +1552,6 @@ config CPU_MIPS32_R2
bool "MIPS32 Release 2"
depends on SYS_HAS_CPU_MIPS32_R2
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_MSA
@@ -1571,6 +1567,7 @@ config CPU_MIPS32_R6
bool "MIPS32 Release 6"
depends on SYS_HAS_CPU_MIPS32_R6
select CPU_HAS_PREFETCH
+ select CPU_NO_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_MSA
@@ -1586,7 +1583,6 @@ config CPU_MIPS64_R1
bool "MIPS64 Release 1"
depends on SYS_HAS_CPU_MIPS64_R1
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1606,7 +1602,6 @@ config CPU_MIPS64_R2
bool "MIPS64 Release 2"
depends on SYS_HAS_CPU_MIPS64_R2
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1624,6 +1619,7 @@ config CPU_MIPS64_R6
bool "MIPS64 Release 6"
depends on SYS_HAS_CPU_MIPS64_R6
select CPU_HAS_PREFETCH
+ select CPU_NO_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1641,7 +1637,6 @@ config CPU_R3000
bool "R3000"
depends on SYS_HAS_CPU_R3000
select CPU_HAS_WB
- select CPU_HAS_LOAD_STORE_LR
select CPU_R3K_TLB
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1657,7 +1652,6 @@ config CPU_TX39XX
bool "R39XX"
depends on SYS_HAS_CPU_TX39XX
select CPU_SUPPORTS_32BIT_KERNEL
- select CPU_HAS_LOAD_STORE_LR
select CPU_R3K_TLB
config CPU_VR41XX
@@ -1665,7 +1659,6 @@ config CPU_VR41XX
depends on SYS_HAS_CPU_VR41XX
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
- select CPU_HAS_LOAD_STORE_LR
help
The options selects support for the NEC VR4100 series of processors.
Only choose this option if you have one of these processors as a
@@ -1678,7 +1671,6 @@ config CPU_R4X00
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
- select CPU_HAS_LOAD_STORE_LR
help
MIPS Technologies R4000-series processors other than 4300, including
the R4000, R4400, R4600, and 4700.
@@ -1687,7 +1679,6 @@ config CPU_TX49XX
bool "R49XX"
depends on SYS_HAS_CPU_TX49XX
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
@@ -1698,7 +1689,6 @@ config CPU_R5000
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
- select CPU_HAS_LOAD_STORE_LR
help
MIPS Technologies R5000-series processors other than the Nevada.
@@ -1708,7 +1698,6 @@ config CPU_R5500
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
- select CPU_HAS_LOAD_STORE_LR
help
NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
instruction set.
@@ -1719,7 +1708,6 @@ config CPU_NEVADA
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HUGEPAGES
- select CPU_HAS_LOAD_STORE_LR
help
QED / PMC-Sierra RM52xx-series ("Nevada") processors.
@@ -1727,7 +1715,6 @@ config CPU_R10000
bool "R10000"
depends on SYS_HAS_CPU_R10000
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1739,7 +1726,6 @@ config CPU_RM7000
bool "RM7000"
depends on SYS_HAS_CPU_RM7000
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1748,7 +1734,6 @@ config CPU_RM7000
config CPU_SB1
bool "SB1"
depends on SYS_HAS_CPU_SB1
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1759,7 +1744,6 @@ config CPU_CAVIUM_OCTEON
bool "Cavium Octeon processor"
depends on SYS_HAS_CPU_CAVIUM_OCTEON
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_64BIT_KERNEL
select WEAK_ORDERING
select CPU_SUPPORTS_HIGHMEM
@@ -1789,7 +1773,6 @@ config CPU_BMIPS
select WEAK_ORDERING
select CPU_SUPPORTS_HIGHMEM
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_CPUFREQ
select MIPS_EXTERNAL_TIMER
help
@@ -1798,7 +1781,6 @@ config CPU_BMIPS
config CPU_XLR
bool "Netlogic XLR SoC"
depends on SYS_HAS_CPU_XLR
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
@@ -1817,7 +1799,6 @@ config CPU_XLP
select WEAK_ORDERING
select WEAK_REORDERING_BEYOND_LLSC
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_MIPSR2
select CPU_SUPPORTS_HUGEPAGES
select MIPS_ASID_BITS_VARIABLE
@@ -1923,14 +1904,12 @@ config CPU_LOONGSON2EF
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select ARCH_HAS_PHYS_TO_DMA
- select CPU_HAS_LOAD_STORE_LR
config CPU_LOONGSON32
bool
select CPU_MIPS32
select CPU_MIPSR2
select CPU_HAS_PREFETCH
- select CPU_HAS_LOAD_STORE_LR
select CPU_SUPPORTS_32BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_CPUFREQ
@@ -2573,12 +2552,13 @@ config XKS01
config CPU_HAS_RIXI
bool
-config CPU_HAS_LOAD_STORE_LR
+config CPU_NO_LOAD_STORE_LR
bool
help
- CPU has support for unaligned load and store instructions:
+ CPU lacks support for unaligned load and store instructions:
LWL, LWR, SWL, SWR (Load/store word left/right).
- LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit systems).
+ LDL, LDR, SDL, SDR (Load/store doubleword left/right, for 64bit
+ systems).
#
# Vectored interrupt mode is an R2 feature
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 92bd2b0f0548..ca6fc4762d97 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -131,7 +131,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -152,7 +152,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl instruction */
#define _LoadW(addr, value, res, type) \
do { \
@@ -187,7 +187,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _LoadHWU(addr, value, res, type) \
do { \
@@ -213,7 +213,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -256,7 +256,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl and ldl instructions */
#define _LoadWU(addr, value, res, type) \
do { \
@@ -340,7 +340,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreHW(addr, value, res, type) \
@@ -366,7 +366,7 @@ do { \
: "r" (value), "r" (addr), "i" (-EFAULT));\
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -407,7 +407,7 @@ do { \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -483,7 +483,7 @@ do { \
: "memory"); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#else /* __BIG_ENDIAN */
@@ -509,7 +509,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -530,7 +530,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl instruction */
#define _LoadW(addr, value, res, type) \
do { \
@@ -565,7 +565,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _LoadHWU(addr, value, res, type) \
@@ -592,7 +592,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _LoadWU(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -635,7 +635,7 @@ do { \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without lwl and ldl instructions */
#define _LoadWU(addr, value, res, type) \
do { \
@@ -718,7 +718,7 @@ do { \
: "=&r" (value), "=r" (res) \
: "r" (addr), "i" (-EFAULT)); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define _StoreHW(addr, value, res, type) \
do { \
@@ -743,7 +743,7 @@ do { \
: "r" (value), "r" (addr), "i" (-EFAULT));\
} while(0)
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
#define _StoreW(addr, value, res, type) \
do { \
__asm__ __volatile__ ( \
@@ -784,7 +784,7 @@ do { \
: "r" (value), "r" (addr), "i" (-EFAULT)); \
} while(0)
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
/* For CPUs without swl and sdl instructions */
#define _StoreW(addr, value, res, type) \
do { \
@@ -861,7 +861,7 @@ do { \
: "memory"); \
} while(0)
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
#endif
#define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel)
diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index cdd19d8561e8..f7994d936505 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -301,14 +301,14 @@
and t0, src, ADDRMASK
PREFS( 0, 2*32(src) )
PREFD( 1, 2*32(dst) )
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
bnez t1, .Ldst_unaligned\@
nop
bnez t0, .Lsrc_unaligned_dst_aligned\@
-#else
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
or t0, t0, t1
bnez t0, .Lcopy_unaligned_bytes\@
-#endif
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
/*
* use delay slot for fall-through
* src and dst are aligned; need to compute rem
@@ -389,7 +389,7 @@
bne rem, len, 1b
.set noreorder
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
/*
* src and dst are aligned, need to copy rem bytes (rem < NBYTES)
* A loop would do only a byte at a time with possible branch
@@ -491,7 +491,7 @@
bne len, rem, 1b
.set noreorder
-#endif /* CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* !CONFIG_CPU_NO_LOAD_STORE_LR */
.Lcopy_bytes_checklen\@:
beqz len, .Ldone\@
nop
@@ -520,7 +520,7 @@
jr ra
nop
-#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifdef CONFIG_CPU_NO_LOAD_STORE_LR
.Lcopy_unaligned_bytes\@:
1:
COPY_BYTE(0)
@@ -534,7 +534,7 @@
ADD src, src, 8
b 1b
ADD dst, dst, 8
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
.if __memcpy == 1
END(memcpy)
.set __memcpy, 0
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 418611ef13cf..d5449e8a3dfc 100644
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -115,7 +115,7 @@
#endif
.set reorder
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
R10KCBARRIER(0(ra))
#ifdef __MIPSEB__
EX(LONG_S_L, a1, (a0), .Lfirst_fixup\@) /* make word/dword aligned */
@@ -125,7 +125,7 @@
PTR_SUBU a0, t0 /* long align ptr */
PTR_ADDU a2, t0 /* correct size */
-#else /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
#define STORE_BYTE(N) \
EX(sb, a1, N(a0), .Lbyte_fixup\@); \
.set noreorder; \
@@ -150,7 +150,7 @@
ori a0, STORMASK
xori a0, STORMASK
PTR_ADDIU a0, STORSIZE
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
1: ori t1, a2, 0x3f /* # of full blocks */
xori t1, 0x3f
andi t0, a2, 0x40-STORSIZE
@@ -185,7 +185,7 @@
.set noreorder
beqz a2, 1f
-#ifdef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifndef CONFIG_CPU_NO_LOAD_STORE_LR
PTR_ADDU a0, a2 /* What's left */
.set reorder
R10KCBARRIER(0(ra))
@@ -194,7 +194,7 @@
#else
EX(LONG_S_L, a1, -1(a0), .Llast_fixup\@)
#endif
-#else
+#else /* CONFIG_CPU_NO_LOAD_STORE_LR */
PTR_SUBU t0, $0, a2
.set reorder
move a2, zero /* No remaining longs */
@@ -211,7 +211,7 @@
EX(sb, a1, 6(a0), .Lbyte_fixup\@)
#endif
0:
-#endif
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
1: move a2, zero
jr ra
@@ -234,7 +234,7 @@
.hidden __memset
.endif
-#ifndef CONFIG_CPU_HAS_LOAD_STORE_LR
+#ifdef CONFIG_CPU_NO_LOAD_STORE_LR
.Lbyte_fixup\@:
/*
* unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1
@@ -243,7 +243,7 @@
PTR_SUBU a2, t0
PTR_ADDIU a2, 1
jr ra
-#endif /* !CONFIG_CPU_HAS_LOAD_STORE_LR */
+#endif /* CONFIG_CPU_NO_LOAD_STORE_LR */
.Lfirst_fixup\@:
/* unset_bytes already in a2 */
--
2.25.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH mips-next 4/5] MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically (again)
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
` (2 preceding siblings ...)
2020-01-22 10:58 ` [PATCH mips-next 3/5] MIPS: make CPU_HAS_LOAD_STORE_LR opt-out Alexander Lobakin
@ 2020-01-22 10:58 ` Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 5/5] Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic kernel" Alexander Lobakin
2020-01-23 19:44 ` [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Paul Burton
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
Cycles "sort selects alphabetically -> add new options at the end or at
random place -> repeat" go on and on.
Please double-check when adding new options and make sure that they
don't break the existing order to prevent dumb commits like this one
from appearing.
Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
---
arch/mips/Kconfig | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 8ff846ef2345..488ce71cce73 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -5,9 +5,11 @@ config MIPS
select ARCH_32BIT_OFF_T if !64BIT
select ARCH_BINFMT_ELF_STATE if MIPS_FP_SUPPORT
select ARCH_CLOCKSOURCE_DATA
+ select ARCH_HAS_FORTIFY_SOURCE
+ select ARCH_HAS_KCOV
+ select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
select ARCH_HAS_UBSAN_SANITIZE_ALL
- select ARCH_HAS_FORTIFY_SOURCE
select ARCH_SUPPORTS_UPROBES
select ARCH_USE_BUILTIN_BSWAP
select ARCH_USE_CMPXCHG_LOCKREF if 64BIT
@@ -48,7 +50,6 @@ config MIPS
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if CPU_SUPPORTS_HUGEPAGES
select HAVE_ASM_MODVERSIONS
select HAVE_CBPF_JIT if !64BIT && !CPU_MICROMIPS
- select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
select HAVE_CONTEXT_TRACKING
select HAVE_COPY_THREAD_TLS
select HAVE_C_RECORDMCOUNT
@@ -56,11 +57,14 @@ config MIPS
select HAVE_DEBUG_STACKOVERFLOW
select HAVE_DMA_CONTIGUOUS
select HAVE_DYNAMIC_FTRACE
+ select HAVE_EBPF_JIT if 64BIT && !CPU_MICROMIPS && TARGET_ISA_REV >= 2
select HAVE_EXIT_THREAD
select HAVE_FAST_GUP
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACER
+ select HAVE_GCC_PLUGINS
+ select HAVE_GENERIC_VDSO
select HAVE_IDE
select HAVE_IOREMAP_PROT
select HAVE_IRQ_EXIT_ON_IRQ_STACK
@@ -79,18 +83,14 @@ config MIPS
select HAVE_STACKPROTECTOR
select HAVE_SYSCALL_TRACEPOINTS
select HAVE_VIRT_CPU_ACCOUNTING_GEN if 64BIT || !SMP
- select HAVE_GENERIC_VDSO
select IRQ_FORCED_THREADING
select ISA if EISA
- select MODULES_USE_ELF_RELA if MODULES && 64BIT
select MODULES_USE_ELF_REL if MODULES
+ select MODULES_USE_ELF_RELA if MODULES && 64BIT
select PERF_USE_VMALLOC
select RTC_LIB
select SYSCTL_EXCEPTION_TRACE
select VIRT_TO_BUS
- select ARCH_HAS_PTE_SPECIAL if !(32BIT && CPU_HAS_RIXI)
- select ARCH_HAS_KCOV
- select HAVE_GCC_PLUGINS
menu "Machine selection"
@@ -105,8 +105,8 @@ config MIPS_GENERIC
select CEVT_R4K
select CLKSRC_MIPS_GIC
select COMMON_CLK
- select CPU_MIPSR2_IRQ_VI
select CPU_MIPSR2_IRQ_EI
+ select CPU_MIPSR2_IRQ_VI
select CSRC_R4K
select DMA_PERDEV_COHERENT
select HAVE_PCI
@@ -131,11 +131,12 @@ config MIPS_GENERIC
select SYS_SUPPORTS_HIGHMEM
select SYS_SUPPORTS_LITTLE_ENDIAN
select SYS_SUPPORTS_MICROMIPS
- select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MIPS16
+ select SYS_SUPPORTS_MIPS_CPS
select SYS_SUPPORTS_MULTITHREADING
select SYS_SUPPORTS_RELOCATABLE
select SYS_SUPPORTS_SMARTMIPS
+ select UHI_BOOT
select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
@@ -143,7 +144,6 @@ config MIPS_GENERIC
select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN
select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
select USE_OF
- select UHI_BOOT
help
Select this to build a kernel which aims to support multiple boards,
generally using a flattened device tree passed from the bootloader
--
2.25.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH mips-next 5/5] Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic kernel"
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
` (3 preceding siblings ...)
2020-01-22 10:58 ` [PATCH mips-next 4/5] MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically (again) Alexander Lobakin
@ 2020-01-22 10:58 ` Alexander Lobakin
2020-01-23 19:44 ` [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Paul Burton
5 siblings, 0 replies; 7+ messages in thread
From: Alexander Lobakin @ 2020-01-22 10:58 UTC (permalink / raw)
To: Paul Burton
Cc: Ralf Baechle, Alexandre Belloni, Microchip Linux Driver Support,
Will Deacon, Greg Kroah-Hartman, Masahiro Yamada, Paul Walmsley,
Alexander Lobakin, Michal Simek, Allison Randal, Thomas Gleixner,
Eric W. Biederman, linux-mips, linux-kernel
This reverts commit c8ec2041f549e7f2dee0c34d25381be6f7805f99.
There's no more need to set BASE_BAUD to 0 to make earlycon work
properly on DTS-based boards since such cases were handled in commit
182ead3e418a ("earlycon: Remove hardcoded port->uartclk initialization
in of_setup_earlycon"). earlycon no longer initializes port->uartclk
with a value of BASE_BAUD * 16 when starting from FDT/OF.
Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
---
arch/mips/include/asm/Kbuild | 1 +
arch/mips/include/asm/serial.h | 18 ------------------
2 files changed, 1 insertion(+), 18 deletions(-)
delete mode 100644 arch/mips/include/asm/serial.h
diff --git a/arch/mips/include/asm/Kbuild b/arch/mips/include/asm/Kbuild
index 61b0fc2026e6..16d1eb4c8fe6 100644
--- a/arch/mips/include/asm/Kbuild
+++ b/arch/mips/include/asm/Kbuild
@@ -19,6 +19,7 @@ generic-y += preempt.h
generic-y += qrwlock.h
generic-y += qspinlock.h
generic-y += sections.h
+generic-y += serial.h
generic-y += trace_clock.h
generic-y += unaligned.h
generic-y += user.h
diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h
deleted file mode 100644
index 2777148dbfc5..000000000000
--- a/arch/mips/include/asm/serial.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2017 MIPS Tech, LLC
- */
-#ifndef __ASM__SERIAL_H
-#define __ASM__SERIAL_H
-
-#ifdef CONFIG_MIPS_GENERIC
-/*
- * Generic kernels cannot know a correct value for all platforms at
- * compile time. Set it to 0 to prevent 8250_early using it
- */
-#define BASE_BAUD 0
-#else
-#include <asm-generic/serial.h>
-#endif
-
-#endif /* __ASM__SERIAL_H */
--
2.25.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
` (4 preceding siblings ...)
2020-01-22 10:58 ` [PATCH mips-next 5/5] Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic kernel" Alexander Lobakin
@ 2020-01-23 19:44 ` Paul Burton
5 siblings, 0 replies; 7+ messages in thread
From: Paul Burton @ 2020-01-23 19:44 UTC (permalink / raw)
To: Alexander Lobakin
Cc: Paul Burton, Ralf Baechle, Alexandre Belloni,
Microchip Linux Driver Support, Will Deacon, Greg Kroah-Hartman,
Masahiro Yamada, Paul Walmsley, Alexander Lobakin, Michal Simek,
Allison Randal, Thomas Gleixner, Eric W. Biederman, linux-mips,
linux-kernel, linux-mips
Hello,
Alexander Lobakin wrote:
> This patchset aims mainly at MIPS and Generic MIPS Kconfig optimizations
> except for the last patch that removes redundant BASE_BAUD override for
> Generic MIPS. If it should go out of this series, please let me know.
> All changes were fully tested on Generic MIPS32R2 board, but I admit
> there potentionally might be any non-critical issues on other systems
> (unlikely though).
>
> Alexander Lobakin (5):
> MIPS: don't explicitly select LIBFDT in Kconfig
> MIPS: generic: don't unconditionally select PINCTRL
> MIPS: make CPU_HAS_LOAD_STORE_LR opt-out
> MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically
> (again)
> Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic
> kernel"
Series applied to mips-next.
> MIPS: don't explicitly select LIBFDT in Kconfig
> commit 7c8f13790958
> https://git.kernel.org/mips/c/7c8f13790958
>
> Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> MIPS: generic: don't unconditionally select PINCTRL
> commit 7de86604bbe4
> https://git.kernel.org/mips/c/7de86604bbe4
>
> Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> MIPS: make CPU_HAS_LOAD_STORE_LR opt-out
> commit 18d84e2e55b6
> https://git.kernel.org/mips/c/18d84e2e55b6
>
> Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically (again)
> commit 34c01e41b247
> https://git.kernel.org/mips/c/34c01e41b247
>
> Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
>
> Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic kernel"
> commit 0a3d5b577784
> https://git.kernel.org/mips/c/0a3d5b577784
>
> Signed-off-by: Alexander Lobakin <alobakin@dlink.ru>
> Signed-off-by: Paul Burton <paulburton@kernel.org>
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paulburton@kernel.org to report it. ]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2020-01-23 19:44 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-01-22 10:58 [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 1/5] MIPS: don't explicitly select LIBFDT in Kconfig Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 2/5] MIPS: generic: don't unconditionally select PINCTRL Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 3/5] MIPS: make CPU_HAS_LOAD_STORE_LR opt-out Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 4/5] MIPS: sort MIPS and MIPS_GENERIC Kconfig selects alphabetically (again) Alexander Lobakin
2020-01-22 10:58 ` [PATCH mips-next 5/5] Revert "MIPS: Add custom serial.h with BASE_BAUD override for generic kernel" Alexander Lobakin
2020-01-23 19:44 ` [PATCH mips-next 0/5] MIPS: a set of misc Kconfig/Kbuild improvements Paul Burton
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.