From: "Falcon, Thomas" <thomas.falcon@intel.com>
To: "alexander.shishkin@linux.intel.com"
<alexander.shishkin@linux.intel.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"peterz@infradead.org" <peterz@infradead.org>,
"acme@kernel.org" <acme@kernel.org>,
"dapeng1.mi@linux.intel.com" <dapeng1.mi@linux.intel.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"Hunter, Adrian" <adrian.hunter@intel.com>,
"namhyung@kernel.org" <namhyung@kernel.org>,
"Rogers, Ian" <irogers@google.com>,
"Eranian, Stephane" <eranian@google.com>
Cc: "stable@vger.kernel.org" <stable@vger.kernel.org>,
"Chen, Zide" <zide.chen@intel.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-perf-users@vger.kernel.org"
<linux-perf-users@vger.kernel.org>,
"Mi, Dapeng1" <dapeng1.mi@intel.com>,
"Hao, Xudong" <xudong.hao@intel.com>
Subject: Re: [PATCH 4/8] perf/x86/intel: Fix redundant branch type check in intel_pmu_lbr_filter()
Date: Fri, 5 Jun 2026 18:28:22 +0000 [thread overview]
Message-ID: <5f1cedec93b2ea87cb89f259b0eaeddba69093bf.camel@intel.com> (raw)
In-Reply-To: <20260605011136.2043393-5-dapeng1.mi@linux.intel.com>
On Fri, 2026-06-05 at 09:11 +0800, Dapeng Mi wrote:
> In intel_pmu_lbr_filter(), the 'type' variable is bitwise ORed with
> 'to_plm' (which contains X86_BR_USER and/or X86_BR_KERNEL bits). Because
> of this, 'type' can never equal X86_BR_NONE (0) after the assignment.
>
> As a result, the subsequent check 'if (type == X86_BR_NONE)' is dead code
> and the entries with X86_BR_NONE type would not be skipped eventually.
>
> Correct this by masking out the X86_BR_KERNEL and X86_BR_USER bits
> before performing the X86_BR_NONE comparison.
>
> Cc: stable@vger.kernel.org
> Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> ---
>
> Original patch link:
> https://lore.kernel.org/all/20260414021440.928068-1-dapeng1.mi@linux.intel.com/
>
> arch/x86/events/intel/lbr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
> index 72f2adcda7c6..16977e4c6f8a 100644
> --- a/arch/x86/events/intel/lbr.c
> +++ b/arch/x86/events/intel/lbr.c
> @@ -1245,7 +1245,7 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
> }
>
> /* if type does not correspond, then discard */
> - if (type == X86_BR_NONE || (br_sel & type) != type) {
> + if ((type & ~X86_BR_PLM) == X86_BR_NONE || (br_sel & type) != type) {
Looking at intel_pmu_lbr_filter...
if (static_cpu_has(X86_FEATURE_ARCH_LBR) &&
type <= ARCH_LBR_BR_TYPE_KNOWN_MAX) {
to_plm = kernel_ip(to) ? X86_BR_KERNEL : X86_BR_USER;
type = arch_lbr_br_type_map[type] | to_plm;
} else
type = branch_type(from, to, cpuc->lbr_entries[i].abort);
In the else case, it does look (branch_type -> get_branch_type) can return X86_BR_NONE without OR'ing it with X86_BR_KERNEL or X86_BR_USER, so the condition checking the type for X86_BR_NONE is not exactly "dead code."
One example:
static int get_branch_type(unsigned long from, unsigned long to, int abort,
bool fused, int *offset)
{
...
* maybe zero if lbr did not fill up after a reset by the time
* we get a PMU interrupt
*/
if (from == 0 || to == 0)
return X86_BR_NONE;
...
Though in those cases, it doesn't seem like this change would make a difference. I guess it isn't clear to me what issue this change is fixing.
Thanks,
Tom
> cpuc->lbr_entries[i].from = 0;
> compress = true;
> }
next prev parent reply other threads:[~2026-06-05 18:28 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-05 1:11 [PATCH 0/8] perf/x86: Miscellaneous PMU bug fixes Dapeng Mi
2026-06-05 1:11 ` [PATCH 1/8] perf/x86/intel: Remove anythread_deprecated bit from perf_capabilities Dapeng Mi
2026-06-05 17:04 ` Falcon, Thomas
2026-06-08 1:37 ` Mi, Dapeng
2026-06-05 1:11 ` [PATCH 2/8] perf/x86: Introduce is_x86_pmu() helper Dapeng Mi
2026-06-05 17:08 ` Falcon, Thomas
2026-06-05 1:11 ` [PATCH 3/8] perf/x86: Update cap_user_rdpmc base on rdpmc user disable state Dapeng Mi
2026-06-05 17:15 ` Falcon, Thomas
2026-06-05 1:11 ` [PATCH 4/8] perf/x86/intel: Fix redundant branch type check in intel_pmu_lbr_filter() Dapeng Mi
2026-06-05 18:28 ` Falcon, Thomas [this message]
2026-06-08 1:56 ` Mi, Dapeng
2026-06-08 6:15 ` Mi, Dapeng
2026-06-05 1:11 ` [PATCH 5/8] perf/x86/intel: Fix kernel address leakages in LBR stack Dapeng Mi
2026-06-05 1:33 ` sashiko-bot
2026-06-05 3:20 ` Mi, Dapeng
2026-06-05 1:11 ` [PATCH 6/8] perf/x86/intel: Validate return value of intel_pmu_init_hybrid() Dapeng Mi
2026-06-05 1:36 ` sashiko-bot
2026-06-05 3:29 ` Mi, Dapeng
2026-06-05 16:17 ` Chen, Zide
2026-06-08 2:48 ` Mi, Dapeng
2026-06-05 18:47 ` Falcon, Thomas
2026-06-05 1:11 ` [PATCH 7/8] perf/x86/intel: Drop fixed-counter PEBS constraints for baseline PEBS Dapeng Mi
2026-06-05 20:32 ` Chen, Zide
2026-06-08 2:46 ` Mi, Dapeng
2026-06-08 15:46 ` Chen, Zide
2026-06-09 0:36 ` Mi, Dapeng
2026-06-05 1:11 ` [PATCH 8/8] perf/core: Fix kernel register info leak via hardware skid Dapeng Mi
2026-06-05 1:38 ` sashiko-bot
2026-06-05 3:42 ` Mi, Dapeng
2026-06-05 19:08 ` Falcon, Thomas
2026-06-08 2:47 ` Mi, Dapeng
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