Re: [PATCH v1 2/3] x86/cpu: Set low performance CRC32C flag on some Zhaoxin CPUs

[Dave Hansen <dave.hansen@intel.com>]

On 1/6/21 10:19 PM, Tony W Wang-oc wrote:
> +	/*
> +	 * These CPUs declare support SSE4.2 instruction sets but
> +	 * having low performance CRC32C instruction implementation.
> +	 */
> +	if (c->x86 == 0x6 || (c->x86 == 0x7 && c->x86_model <= 0x3b))
> +		set_cpu_cap(c, X86_FEATURE_CRC32C);
>  }

On the Intel side, we've tried to move away from open-coded model
numbers.  Say another CPU is released that has a microarchitecture close
to 0x3b, but has a model of 0x3c.  It's a *LOT* easier to grep for
INTEL_FAM6_NEHALEM (or whatever) than 0x3c.  See:

	arch/x86/include/asm/intel-family.h

for examples.