From: Marc Zyngier <maz@kernel.org>
To: Alexandre Torgue <alexandre.torgue@st.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Linus Walleij <linus.walleij@linaro.org>,
marex@denx.de, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/2] irqchip/stm32: Add irq retrigger support
Date: Wed, 19 Feb 2020 11:43:11 +0000 [thread overview]
Message-ID: <608d9c84813323ee3839f6ac21aa8f4e@kernel.org> (raw)
In-Reply-To: <16d27f75-8157-7a92-ae61-b5b3ab05bdd9@st.com>
On 2020-02-19 11:33, Alexandre Torgue wrote:
> Fix Marc email address
>
> On 2/18/20 2:12 PM, Alexandre Torgue wrote:
>> This commit introduces retrigger support for stm32_ext_h chip.
>> It consists to rise the GIC interrupt mapped to an EXTI line.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>>
>> diff --git a/drivers/irqchip/irq-stm32-exti.c
>> b/drivers/irqchip/irq-stm32-exti.c
>> index e00f2fa27f00..c971d115edb4 100644
>> --- a/drivers/irqchip/irq-stm32-exti.c
>> +++ b/drivers/irqchip/irq-stm32-exti.c
>> @@ -604,12 +604,24 @@ static void stm32_exti_h_syscore_deinit(void)
>> unregister_syscore_ops(&stm32_exti_h_syscore_ops);
>> }
>> +static int stm32_exti_h_retrigger(struct irq_data *d)
>> +{
>> + struct stm32_exti_chip_data *chip_data =
>> irq_data_get_irq_chip_data(d);
>> + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
>> + void __iomem *base = chip_data->host_data->base;
>> + u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
>> +
>> + writel_relaxed(mask, base + stm32_bank->swier_ofst);
>> +
>> + return irq_chip_retrigger_hierarchy(d);
Calling irq_chip_retrigger_hierarchy here is really odd. If the write
above has the effect of making the interrupt pending again, why do you
need to force the retrigger any further?
M.
--
Jazz is not dead. It just smells funny...
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Alexandre Torgue <alexandre.torgue@st.com>
Cc: marex@denx.de, Jason Cooper <jason@lakedaemon.net>,
Linus Walleij <linus.walleij@linaro.org>,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 1/2] irqchip/stm32: Add irq retrigger support
Date: Wed, 19 Feb 2020 11:43:11 +0000 [thread overview]
Message-ID: <608d9c84813323ee3839f6ac21aa8f4e@kernel.org> (raw)
In-Reply-To: <16d27f75-8157-7a92-ae61-b5b3ab05bdd9@st.com>
On 2020-02-19 11:33, Alexandre Torgue wrote:
> Fix Marc email address
>
> On 2/18/20 2:12 PM, Alexandre Torgue wrote:
>> This commit introduces retrigger support for stm32_ext_h chip.
>> It consists to rise the GIC interrupt mapped to an EXTI line.
>>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
>>
>> diff --git a/drivers/irqchip/irq-stm32-exti.c
>> b/drivers/irqchip/irq-stm32-exti.c
>> index e00f2fa27f00..c971d115edb4 100644
>> --- a/drivers/irqchip/irq-stm32-exti.c
>> +++ b/drivers/irqchip/irq-stm32-exti.c
>> @@ -604,12 +604,24 @@ static void stm32_exti_h_syscore_deinit(void)
>> unregister_syscore_ops(&stm32_exti_h_syscore_ops);
>> }
>> +static int stm32_exti_h_retrigger(struct irq_data *d)
>> +{
>> + struct stm32_exti_chip_data *chip_data =
>> irq_data_get_irq_chip_data(d);
>> + const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
>> + void __iomem *base = chip_data->host_data->base;
>> + u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
>> +
>> + writel_relaxed(mask, base + stm32_bank->swier_ofst);
>> +
>> + return irq_chip_retrigger_hierarchy(d);
Calling irq_chip_retrigger_hierarchy here is really odd. If the write
above has the effect of making the interrupt pending again, why do you
need to force the retrigger any further?
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2020-02-19 11:43 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-18 13:12 [PATCH v2 0/2] Add GPIO level-sensitive interrupt support Alexandre Torgue
2020-02-18 13:12 ` Alexandre Torgue
2020-02-18 13:12 ` [PATCH v2 1/2] irqchip/stm32: Add irq retrigger support Alexandre Torgue
2020-02-18 13:12 ` Alexandre Torgue
2020-02-18 17:51 ` Marek Vasut
2020-02-18 17:51 ` Marek Vasut
2020-02-19 11:33 ` Alexandre Torgue
2020-02-19 11:33 ` Alexandre Torgue
2020-02-19 11:43 ` Marc Zyngier [this message]
2020-02-19 11:43 ` Marc Zyngier
2020-02-19 13:07 ` Alexandre Torgue
2020-02-19 13:07 ` Alexandre Torgue
2020-02-19 13:13 ` Marc Zyngier
2020-02-19 13:13 ` Marc Zyngier
2020-02-19 13:17 ` Alexandre Torgue
2020-02-19 13:17 ` Alexandre Torgue
2020-02-18 13:12 ` [PATCH v2 2/2] pinctrl: stm32: Add level interrupt support to gpio irq chip Alexandre Torgue
2020-02-18 13:12 ` Alexandre Torgue
2020-02-18 17:51 ` Marek Vasut
2020-02-18 17:51 ` Marek Vasut
2020-02-19 11:34 ` Alexandre Torgue
2020-02-19 11:34 ` Alexandre Torgue
2020-02-19 12:07 ` Marc Zyngier
2020-02-19 12:07 ` Marc Zyngier
2020-02-19 12:59 ` Alexandre Torgue
2020-02-19 12:59 ` Alexandre Torgue
2020-02-18 16:25 ` [PATCH v2 0/2] Add GPIO level-sensitive interrupt support Marek Vasut
2020-02-18 16:25 ` Marek Vasut
2020-02-18 18:10 ` Alexandre Torgue
2020-02-18 18:10 ` Alexandre Torgue
2020-02-18 18:13 ` Marek Vasut
2020-02-18 18:13 ` Marek Vasut
2020-02-19 9:20 ` Alexandre Torgue
2020-02-19 9:20 ` Alexandre Torgue
2020-02-19 17:24 ` Marek Vasut
2020-02-19 17:24 ` Marek Vasut
2020-02-20 13:09 ` Alexandre Torgue
2020-02-20 13:09 ` Alexandre Torgue
2020-02-21 16:41 ` Marek Vasut
2020-02-21 16:41 ` Marek Vasut
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