From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Dave Jiang <dave.jiang@intel.com>,
Alison Schofield <alison.schofield@intel.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Tue, 1 Sep 2026 19:30:45 -0700 [thread overview]
Message-ID: <6353b16d-36a0-4fa1-9b9e-8a3448b6e07e@nvidia.com> (raw)
In-Reply-To: <1c648e0d-eb07-4006-91ec-9f092fd7c8ec@intel.com>
On 8/21/26 4:33 PM, Dave Jiang wrote:
>> +}
>> +
>> +static int cxl_pci_hdm_capable(struct pci_dev *pdev)
> Function should return a bool.
>
> cxl_pci_mem_capable() would be clearer on what this function is checking. Although do you want to check the hdm_count as well? That would make the original function name make sense.
>
> Also a helper that returns the DVSEC offset and the cap word can be shared with cxl_dvsec_rr_decode() and cxl_reset_dvsec().
>
>
>> +{
>> + u16 cap;
>> + int dvsec;
>> + int rc;
>> +
>> + dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
>> + PCI_DVSEC_CXL_DEVICE);
>> + if (!dvsec)
>> + return -ENOTTY;
>> +
>> + rc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_CAP, &cap);
>> + if (rc)
>> + return pcibios_err_to_errno(rc);
>> +
>> + if (!(cap & PCI_DVSEC_CXL_MEM_CAPABLE))
>> + return -ENOTTY;
>> +
>> + return 0;
>> +}
>> +
>> +static int cxl_pci_hdm_read_info(struct pci_dev *pdev,
>> + struct cxl_register_map *map,
>> + struct cxl_hdm_info *info)
>> +{
>> + struct cxl_decoder_settings *settings;
>> + void __iomem *hdm;
>> + int decoder_count;
>> + int rc;
>> +
>> + rc = cxl_setup_regs(map);
>> + if (rc)
>> + return rc;
>> +
>> + if (!map->component_map.hdm_decoder.valid)
>> + return -ENODEV;
>> +
>> + hdm = cxl_pci_hdm_map(pdev, map, info);
> I think you can setup a custom __free() for the hdm so you don't need to have the gotos.
>
>> + if (IS_ERR(hdm))
>> + return PTR_ERR(hdm);
>> +
>> + decoder_count = cxl_hdm_decoder_count(readl(hdm +
>> + CXL_HDM_DECODER_CAP_OFFSET));
>> + if (decoder_count < 0) {
>> + rc = decoder_count;
>> + goto out_unmap;
>> + }
>> +
>> + if (decoder_count > CXL_HDM_DECODER_MAX_COUNT) {
> There's no need to check this. The register cannot decoder larger than a value of 32. So this scenario would never happen. Maybe
> if (decoder_count > ARRAY_SIZE(info->settings))
>
> DJ
Ack. I've addressed this in v11. The helper now returns bool, and I
retained the cxl_pci_hdm_capable() name because it checks both CXL.mem
capability and HDM decoder count.
I also added a shared helper for retrieving the CXL Device DVSEC
offset and capability word, added a custom __free() cleanup for the HDM
mapping, and replaced the fixed decoder-count limit with an ARRAY_SIZE()
check.
--
Regards,
Srirangan
next prev parent reply other threads:[~2026-09-02 2:30 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-04 19:29 [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-08-04 19:46 ` sashiko-bot
2026-08-05 2:13 ` Alison Schofield
2026-09-02 0:52 ` Srirangan Madhavan
2026-08-20 21:13 ` Dave Jiang
2026-08-24 7:11 ` Li Ming
2026-08-24 7:19 ` Li Ming
2026-09-02 1:18 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 02/12] cxl: Pass decoder settings to HDM commit helpers Srirangan Madhavan
2026-08-04 19:49 ` sashiko-bot
2026-08-20 22:21 ` Dave Jiang
2026-09-02 1:51 ` Srirangan Madhavan
2026-08-24 7:33 ` Li Ming
2026-09-02 1:53 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-08-04 19:45 ` sashiko-bot
2026-08-20 23:25 ` Dave Jiang
2026-09-02 1:58 ` Srirangan Madhavan
2026-09-02 2:06 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-08-04 19:40 ` sashiko-bot
2026-08-21 22:12 ` Dave Jiang
2026-09-02 2:12 ` Srirangan Madhavan
2026-08-24 7:53 ` Li Ming
2026-09-02 2:13 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-08-04 19:51 ` sashiko-bot
2026-08-05 2:28 ` Alison Schofield
2026-09-02 2:14 ` Srirangan Madhavan
2026-08-17 5:30 ` Richard Cheng
2026-09-02 2:23 ` Srirangan Madhavan
2026-08-21 23:33 ` Dave Jiang
2026-09-02 2:30 ` Srirangan Madhavan [this message]
2026-08-25 6:58 ` Li Ming
2026-09-02 2:48 ` Srirangan Madhavan
2026-08-26 18:30 ` Lucero Palau, Alejandro
2026-09-02 3:22 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-08-04 19:42 ` sashiko-bot
2026-08-24 22:24 ` Dave Jiang
2026-08-26 18:09 ` Lucero Palau, Alejandro
2026-09-02 3:52 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-08-04 19:38 ` sashiko-bot
2026-08-25 20:30 ` Dave Jiang
2026-09-02 4:39 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 08/12] cxl: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-08-04 19:40 ` sashiko-bot
2026-08-25 20:32 ` Dave Jiang
2026-08-26 18:47 ` Lucero Palau, Alejandro
2026-09-02 4:52 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 09/12] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-08-04 19:44 ` sashiko-bot
2026-08-17 7:12 ` Richard Cheng
2026-09-02 5:17 ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-08-04 20:00 ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-08-04 19:41 ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-08-04 19:59 ` sashiko-bot
2026-08-13 9:35 ` [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Alejandro Lucero Palau
2026-08-25 21:13 ` Dave Jiang
2026-09-02 5:11 ` Srirangan Madhavan
2026-09-02 15:37 ` Dave Jiang
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