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From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Alex Williamson <alex.williamson@redhat.com>,
	vsethi@nvidia.com, alwilliamson@nvidia.com,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration
Date: Tue, 1 Sep 2026 19:14:08 -0700	[thread overview]
Message-ID: <d064eedb-91be-4aa1-8212-c9b8faa27b72@nvidia.com> (raw)
In-Reply-To: <anKfz_QxEaTVNm1R@aschofie-mobl2.lan>

On 8/4/26 7:28 PM, Alison Schofield wrote:
> snip
>> diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c
> snip
>> +void pci_cxl_hdm_init(struct pci_dev *pdev)
>> +{
>> +     int rc;
>> +
>> +     rc = __pci_cxl_hdm_init(pdev);
>> +     if (rc && rc != -ENOTTY && rc != -ENODEV)
>> +             pci_dbg(pdev, "CXL HDM cache init failed: %d\n", rc);
>> +}
> Needs: EXPORT_SYMBOL_FOR_MODULES(pci_cxl_hdm_init, "cxl_core");
> 
> Without that the modular build fails, CONFIG_CXL_BUS=m
>          ERROR: modpost: "pci_cxl_hdm_init" [drivers/cxl/core/cxl_core.ko] undefined!
> 
> To catch this: build with CONFIG_CXL_BUS=m, not =y.
> With =y, hdm.o and resource.o both land in vmlinux so the reference
> resolves at link time and the missing export is invisible.
> 
> This failure masked the first one because modpost aborts before
> Module.symvers is written, reads a stale Module.symvers and
> make some erroneous complaints.
> 
> And, FWIW, with this and the mock Kbuild fixup in Patch 1, the
> series passes the CXL unit tests.
> 
> -- Alison

Thank you. Fixed this in v11 by exporting pci_cxl_hdm_init() for 
cxl_core. I also tested with CONFIG_CXL_BUS=m and verified both make 
vmlinux modules and make M=tools/testing/cxl/ pass.

-- 
Regards,
Srirangan

  reply	other threads:[~2026-09-02  2:14 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 19:29 [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 01/12] cxl: Move HDM decoder programming helpers Srirangan Madhavan
2026-08-04 19:46   ` sashiko-bot
2026-08-05  2:13   ` Alison Schofield
2026-09-02  0:52     ` Srirangan Madhavan
2026-08-20 21:13   ` Dave Jiang
2026-08-24  7:11   ` Li Ming
2026-08-24  7:19     ` Li Ming
2026-09-02  1:18       ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 02/12] cxl: Pass decoder settings to HDM commit helpers Srirangan Madhavan
2026-08-04 19:49   ` sashiko-bot
2026-08-20 22:21   ` Dave Jiang
2026-09-02  1:51     ` Srirangan Madhavan
2026-08-24  7:33   ` Li Ming
2026-09-02  1:53     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 03/12] cxl: Share HDM decoder decode logic Srirangan Madhavan
2026-08-04 19:45   ` sashiko-bot
2026-08-20 23:25   ` Dave Jiang
2026-09-02  1:58     ` Srirangan Madhavan
2026-09-02  2:06     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 04/12] cxl: Cache decoder settings on PCI devices Srirangan Madhavan
2026-08-04 19:40   ` sashiko-bot
2026-08-21 22:12   ` Dave Jiang
2026-09-02  2:12     ` Srirangan Madhavan
2026-08-24  7:53   ` Li Ming
2026-09-02  2:13     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Srirangan Madhavan
2026-08-04 19:51   ` sashiko-bot
2026-08-05  2:28   ` Alison Schofield
2026-09-02  2:14     ` Srirangan Madhavan [this message]
2026-08-17  5:30   ` Richard Cheng
2026-09-02  2:23     ` Srirangan Madhavan
2026-08-21 23:33   ` Dave Jiang
2026-09-02  2:30     ` Srirangan Madhavan
2026-08-25  6:58   ` Li Ming
2026-09-02  2:48     ` Srirangan Madhavan
2026-08-26 18:30   ` Lucero Palau, Alejandro
2026-09-02  3:22     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 06/12] cxl: Add CXL Device Reset helper Srirangan Madhavan
2026-08-04 19:42   ` sashiko-bot
2026-08-24 22:24   ` Dave Jiang
2026-08-26 18:09   ` Lucero Palau, Alejandro
2026-09-02  3:52     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 07/12] cxl: Validate HDM ranges before CXL reset Srirangan Madhavan
2026-08-04 19:38   ` sashiko-bot
2026-08-25 20:30   ` Dave Jiang
2026-09-02  4:39     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 08/12] cxl: Reject CXL Reset on multifunction devices Srirangan Madhavan
2026-08-04 19:40   ` sashiko-bot
2026-08-25 20:32   ` Dave Jiang
2026-08-26 18:47   ` Lucero Palau, Alejandro
2026-09-02  4:52     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 09/12] cxl: Restore CXL HDM state after PCI reset Srirangan Madhavan
2026-08-04 19:44   ` sashiko-bot
2026-08-17  7:12   ` Richard Cheng
2026-09-02  5:17     ` Srirangan Madhavan
2026-08-04 19:29 ` [PATCH v10 10/12] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-08-04 20:00   ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 11/12] Documentation/ABI: Document CXL Reset " Srirangan Madhavan
2026-08-04 19:41   ` sashiko-bot
2026-08-04 19:29 ` [PATCH v10 12/12] PCI/CXL: Restore HDM state after CXL bus reset Srirangan Madhavan
2026-08-04 19:59   ` sashiko-bot
2026-08-13  9:35 ` [PATCH v10 00/12] PCI/CXL: Add CXL reset support for Type 2 devices Alejandro Lucero Palau
2026-08-25 21:13 ` Dave Jiang
2026-09-02  5:11   ` Srirangan Madhavan
2026-09-02 15:37     ` Dave Jiang

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