Re: [PATCH] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled

["Liu Kimriver/刘金河" <kimriver.liu@siengine.com>]

Hi,
 I am sorry for not replying to questions in time, when I left the office early on Friday.
 I sincerely apologize to you again.

-----邮件原件-----
发件人: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 
发送时间: 2024年9月6日 19:48
收件人: Liu Kimriver/刘金河 <kimriver.liu@siengine.com>
抄送: jarkko.nikula@linux.intel.com; mika.westerberg@linux.intel.com; jsd@semihalf.com; andi.shyti@kernel.org; linux-i2c@vger.kernel.org; linux-kernel@vger.kernel.org
主题: Re: [PATCH] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled

On Fri, Sep 06, 2024 at 01:42:50PM +0800, Kimriver Liu wrote:
> It was observed issuing ABORT bit(IC_ENABLE[1]) will not work when 
> IC_ENABLE is already disabled.
> 
> Check if ENABLE bit(IC_ENABLE[0]) is disabled when the master is 
> holding SCL low. If ENABLE bit is disabled, the software need enable 
> it before trying to issue ABORT bit. otherwise, the controller ignores 
> any write to ABORT bit
> 
> Signed-off-by: Kimriver Liu <kimriver.liu@siengine.com>
> 
> ---

> V3->V4:

>Nice, but the Subject (which is most important part) still has no versioning :-(

 Thanks or your guidance.
 ON Monday , I will update the Subject versioning and resend V7 patch:  
 [PATCH V7] i2c: designware: fix master is holding SCL low while ENABLE bit is disabled

>       1. update commit messages and add patch version and changelog
>       2. move print the error message in i2c_dw_xfer
> V2->V3: change (!enable) to (!(enable & DW_IC_ENABLE_ENABLE))
> V1->V2: used standard words in function names and addressed review 
> V1->comments

...

> +			/*
> +			 * Wait two ic_clk delay when enabling the i2c to ensure ENABLE bit
> +			 * is already set by the driver (for 400KHz this is 25us)
> +			 * as described in the DesignWare I2C databook.
> +			 */
> +			fsleep(25);

>And if we use 100kHz?
>Please, calculate this delay based on the actual speed in use (or about to be in use).

Yes, I will change fsleep(25) to usleep_range(25, 250), for next V7 version.
Wait 10 times the signaling period of the highest I2C transfer supported
by the driver (for 400KHz this is* 25us)

> +		}

---------------
Kimriver Liu