[PATCH v2 0/2] RK3588 PCIe3 support

[PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

Hi,

This adds PCIe v3 support for RK3588. The series depends on the PCIe
v2 series [0], since the the same binding is used. It has been tested
on Rockchip EVB1 and Radxa Rock 5B.

Note, that the PCIe3 PHY driver is currently missing bifurcation
support for RK3588. Thus after this series only PCIe3x4 is usable
(in aggregated x4 mode) without adding support for the PHY's
"rockchip,pcie30-phymode" DT property, which allows configuring
how the lanes are distributed. Aggregated 3x4 mode seems to be the
most common configuration. Both EVB1 and Rock 5B use it, so I
cannot test anything else anyways.

[0] https://lore.kernel.org/all/20230717172651.64324-1-sebastian.reichel@collabora.com/

Changes since v1:
 * https://lore.kernel.org/all/20230714175331.112923-1-sebastian.reichel@collabora.com/
 * Collected Acked-by from Conor Dooley
 * Dropped deprecated and useless num-ib-windows/num-ob-windows/num-viewport
   properties from DT (Serge Semin)

-- Sebastian

Sebastian Reichel (2):
  dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
  arm64: dts: rockchip: rk3588: add PCIe3 support

 .../bindings/phy/rockchip,pcie3-phy.yaml      |  33 ++++-
 arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 120 ++++++++++++++++++
 2 files changed, 148 insertions(+), 5 deletions(-)

-- 
2.40.1


-- 
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[PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

Hi,

This adds PCIe v3 support for RK3588. The series depends on the PCIe
v2 series [0], since the the same binding is used. It has been tested
on Rockchip EVB1 and Radxa Rock 5B.

Note, that the PCIe3 PHY driver is currently missing bifurcation
support for RK3588. Thus after this series only PCIe3x4 is usable
(in aggregated x4 mode) without adding support for the PHY's
"rockchip,pcie30-phymode" DT property, which allows configuring
how the lanes are distributed. Aggregated 3x4 mode seems to be the
most common configuration. Both EVB1 and Rock 5B use it, so I
cannot test anything else anyways.

[0] https://lore.kernel.org/all/20230717172651.64324-1-sebastian.reichel@collabora.com/

Changes since v1:
 * https://lore.kernel.org/all/20230714175331.112923-1-sebastian.reichel@collabora.com/
 * Collected Acked-by from Conor Dooley
 * Dropped deprecated and useless num-ib-windows/num-ob-windows/num-viewport
   properties from DT (Serge Semin)

-- Sebastian

Sebastian Reichel (2):
  dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
  arm64: dts: rockchip: rk3588: add PCIe3 support

 .../bindings/phy/rockchip,pcie3-phy.yaml      |  33 ++++-
 arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 120 ++++++++++++++++++
 2 files changed, 148 insertions(+), 5 deletions(-)

-- 
2.40.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

Hi,

This adds PCIe v3 support for RK3588. The series depends on the PCIe
v2 series [0], since the the same binding is used. It has been tested
on Rockchip EVB1 and Radxa Rock 5B.

Note, that the PCIe3 PHY driver is currently missing bifurcation
support for RK3588. Thus after this series only PCIe3x4 is usable
(in aggregated x4 mode) without adding support for the PHY's
"rockchip,pcie30-phymode" DT property, which allows configuring
how the lanes are distributed. Aggregated 3x4 mode seems to be the
most common configuration. Both EVB1 and Rock 5B use it, so I
cannot test anything else anyways.

[0] https://lore.kernel.org/all/20230717172651.64324-1-sebastian.reichel@collabora.com/

Changes since v1:
 * https://lore.kernel.org/all/20230714175331.112923-1-sebastian.reichel@collabora.com/
 * Collected Acked-by from Conor Dooley
 * Dropped deprecated and useless num-ib-windows/num-ob-windows/num-viewport
   properties from DT (Serge Semin)

-- Sebastian

Sebastian Reichel (2):
  dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
  arm64: dts: rockchip: rk3588: add PCIe3 support

 .../bindings/phy/rockchip,pcie3-phy.yaml      |  33 ++++-
 arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 120 ++++++++++++++++++
 2 files changed, 148 insertions(+), 5 deletions(-)

-- 
2.40.1


_______________________________________________
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Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

Hi,

This adds PCIe v3 support for RK3588. The series depends on the PCIe
v2 series [0], since the the same binding is used. It has been tested
on Rockchip EVB1 and Radxa Rock 5B.

Note, that the PCIe3 PHY driver is currently missing bifurcation
support for RK3588. Thus after this series only PCIe3x4 is usable
(in aggregated x4 mode) without adding support for the PHY's
"rockchip,pcie30-phymode" DT property, which allows configuring
how the lanes are distributed. Aggregated 3x4 mode seems to be the
most common configuration. Both EVB1 and Rock 5B use it, so I
cannot test anything else anyways.

[0] https://lore.kernel.org/all/20230717172651.64324-1-sebastian.reichel@collabora.com/

Changes since v1:
 * https://lore.kernel.org/all/20230714175331.112923-1-sebastian.reichel@collabora.com/
 * Collected Acked-by from Conor Dooley
 * Dropped deprecated and useless num-ib-windows/num-ob-windows/num-viewport
   properties from DT (Serge Semin)

-- Sebastian

Sebastian Reichel (2):
  dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
  arm64: dts: rockchip: rk3588: add PCIe3 support

 .../bindings/phy/rockchip,pcie3-phy.yaml      |  33 ++++-
 arch/arm64/boot/dts/rockchip/rk3588.dtsi      | 120 ++++++++++++++++++
 2 files changed, 148 insertions(+), 5 deletions(-)

-- 
2.40.1

[PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy

[Sebastian Reichel]

When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../bindings/phy/rockchip,pcie3-phy.yaml      | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index 9f2d8d2cc7a5..c4fbffcde6e4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -13,19 +13,18 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-pcie3-phy
+      - rockchip,rk3588-pcie3-phy
 
   reg:
     maxItems: 1
 
   clocks:
-    minItems: 3
+    minItems: 1
     maxItems: 3
 
   clock-names:
-    items:
-      - const: refclk_m
-      - const: refclk_n
-      - const: pclk
+    minItems: 1
+    maxItems: 3
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -61,6 +60,30 @@ required:
   - rockchip,phy-grf
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - rockchip,rk3588-pcie3-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: pclk
+    else:
+      properties:
+        clocks:
+          minItems: 3
+
+        clock-names:
+          items:
+            - const: refclk_m
+            - const: refclk_n
+            - const: pclk
+
 additionalProperties: false
 
 examples:
-- 
2.40.1


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[PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy

[Sebastian Reichel]

When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../bindings/phy/rockchip,pcie3-phy.yaml      | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index 9f2d8d2cc7a5..c4fbffcde6e4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -13,19 +13,18 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-pcie3-phy
+      - rockchip,rk3588-pcie3-phy
 
   reg:
     maxItems: 1
 
   clocks:
-    minItems: 3
+    minItems: 1
     maxItems: 3
 
   clock-names:
-    items:
-      - const: refclk_m
-      - const: refclk_n
-      - const: pclk
+    minItems: 1
+    maxItems: 3
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -61,6 +60,30 @@ required:
   - rockchip,phy-grf
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - rockchip,rk3588-pcie3-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: pclk
+    else:
+      properties:
+        clocks:
+          minItems: 3
+
+        clock-names:
+          items:
+            - const: refclk_m
+            - const: refclk_n
+            - const: pclk
+
 additionalProperties: false
 
 examples:
-- 
2.40.1


_______________________________________________
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[PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy

[Sebastian Reichel]

When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../bindings/phy/rockchip,pcie3-phy.yaml      | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index 9f2d8d2cc7a5..c4fbffcde6e4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -13,19 +13,18 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-pcie3-phy
+      - rockchip,rk3588-pcie3-phy
 
   reg:
     maxItems: 1
 
   clocks:
-    minItems: 3
+    minItems: 1
     maxItems: 3
 
   clock-names:
-    items:
-      - const: refclk_m
-      - const: refclk_n
-      - const: pclk
+    minItems: 1
+    maxItems: 3
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -61,6 +60,30 @@ required:
   - rockchip,phy-grf
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - rockchip,rk3588-pcie3-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: pclk
+    else:
+      properties:
+        clocks:
+          minItems: 3
+
+        clock-names:
+          items:
+            - const: refclk_m
+            - const: refclk_n
+            - const: pclk
+
 additionalProperties: false
 
 examples:
-- 
2.40.1


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy

[Sebastian Reichel]

When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
support was included, but the DT binding does not reflect this.
This adds the missing bits.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 .../bindings/phy/rockchip,pcie3-phy.yaml      | 33 ++++++++++++++++---
 1 file changed, 28 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
index 9f2d8d2cc7a5..c4fbffcde6e4 100644
--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -13,19 +13,18 @@ properties:
   compatible:
     enum:
       - rockchip,rk3568-pcie3-phy
+      - rockchip,rk3588-pcie3-phy
 
   reg:
     maxItems: 1
 
   clocks:
-    minItems: 3
+    minItems: 1
     maxItems: 3
 
   clock-names:
-    items:
-      - const: refclk_m
-      - const: refclk_n
-      - const: pclk
+    minItems: 1
+    maxItems: 3
 
   data-lanes:
     description: which lanes (by position) should be mapped to which
@@ -61,6 +60,30 @@ required:
   - rockchip,phy-grf
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - rockchip,rk3588-pcie3-phy
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+        clock-names:
+          items:
+            - const: pclk
+    else:
+      properties:
+        clocks:
+          minItems: 3
+
+        clock-names:
+          items:
+            - const: refclk_m
+            - const: refclk_n
+            - const: pclk
+
 additionalProperties: false
 
 examples:
-- 
2.40.1

[PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

Add both PCIe3 controllers together with the shared PHY.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 88d702575db2..8f210f002fac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	pcie30_phy_grf: syscon@fd5b8000 {
+		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+		reg = <0x0 0xfd5b8000 0x0 0x10000>;
+	};
+
 	pipe_phy1_grf: syscon@fd5c0000 {
 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
 		status = "disabled";
 	};
 
+	pcie3x4: pcie@fe150000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x00 0x0f>;
+		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+				<0 0 0 2 &pcie3x4_intc 1>,
+				<0 0 0 3 &pcie3x4_intc 2>,
+				<0 0 0 4 &pcie3x4_intc 3>;
+		linux,pci-domain = <0>;
+		max-link-speed = <3>;
+		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		num-lanes = <4>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+		reg = <0xa 0x40000000 0x0 0x00400000>,
+		      <0x0 0xfe150000 0x0 0x00010000>,
+		      <0x0 0xf0000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x4_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
+	pcie3x2: pcie@fe160000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x10 0x1f>;
+		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+				<0 0 0 2 &pcie3x2_intc 1>,
+				<0 0 0 3 &pcie3x2_intc 2>,
+				<0 0 0 4 &pcie3x2_intc 3>;
+		linux,pci-domain = <1>;
+		max-link-speed = <3>;
+		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		num-lanes = <2>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+		reg = <0xa 0x40400000 0x0 0x00400000>,
+		      <0x0 0xfe160000 0x0 0x00010000>,
+		      <0x0 0xf1000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x2_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
 	pcie2x1l0: pcie@fe170000 {
 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 		#address-cells = <3>;
@@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
 		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
 		status = "disabled";
 	};
+
+	pcie30phy: phy@fee80000 {
+		compatible = "rockchip,rk3588-pcie3-phy";
+		reg = <0x0 0xfee80000 0x0 0x20000>;
+		#phy-cells = <0>;
+		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_PCIE30_PHY>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <&php_grf>;
+		rockchip,phy-grf = <&pcie30_phy_grf>;
+		status = "disabled";
+	};
 };
-- 
2.40.1


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[PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

Add both PCIe3 controllers together with the shared PHY.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 88d702575db2..8f210f002fac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	pcie30_phy_grf: syscon@fd5b8000 {
+		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+		reg = <0x0 0xfd5b8000 0x0 0x10000>;
+	};
+
 	pipe_phy1_grf: syscon@fd5c0000 {
 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
 		status = "disabled";
 	};
 
+	pcie3x4: pcie@fe150000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x00 0x0f>;
+		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+				<0 0 0 2 &pcie3x4_intc 1>,
+				<0 0 0 3 &pcie3x4_intc 2>,
+				<0 0 0 4 &pcie3x4_intc 3>;
+		linux,pci-domain = <0>;
+		max-link-speed = <3>;
+		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		num-lanes = <4>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+		reg = <0xa 0x40000000 0x0 0x00400000>,
+		      <0x0 0xfe150000 0x0 0x00010000>,
+		      <0x0 0xf0000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x4_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
+	pcie3x2: pcie@fe160000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x10 0x1f>;
+		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+				<0 0 0 2 &pcie3x2_intc 1>,
+				<0 0 0 3 &pcie3x2_intc 2>,
+				<0 0 0 4 &pcie3x2_intc 3>;
+		linux,pci-domain = <1>;
+		max-link-speed = <3>;
+		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		num-lanes = <2>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+		reg = <0xa 0x40400000 0x0 0x00400000>,
+		      <0x0 0xfe160000 0x0 0x00010000>,
+		      <0x0 0xf1000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x2_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
 	pcie2x1l0: pcie@fe170000 {
 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 		#address-cells = <3>;
@@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
 		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
 		status = "disabled";
 	};
+
+	pcie30phy: phy@fee80000 {
+		compatible = "rockchip,rk3588-pcie3-phy";
+		reg = <0x0 0xfee80000 0x0 0x20000>;
+		#phy-cells = <0>;
+		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_PCIE30_PHY>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <&php_grf>;
+		rockchip,phy-grf = <&pcie30_phy_grf>;
+		status = "disabled";
+	};
 };
-- 
2.40.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

Add both PCIe3 controllers together with the shared PHY.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 88d702575db2..8f210f002fac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	pcie30_phy_grf: syscon@fd5b8000 {
+		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+		reg = <0x0 0xfd5b8000 0x0 0x10000>;
+	};
+
 	pipe_phy1_grf: syscon@fd5c0000 {
 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
 		status = "disabled";
 	};
 
+	pcie3x4: pcie@fe150000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x00 0x0f>;
+		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+				<0 0 0 2 &pcie3x4_intc 1>,
+				<0 0 0 3 &pcie3x4_intc 2>,
+				<0 0 0 4 &pcie3x4_intc 3>;
+		linux,pci-domain = <0>;
+		max-link-speed = <3>;
+		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		num-lanes = <4>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+		reg = <0xa 0x40000000 0x0 0x00400000>,
+		      <0x0 0xfe150000 0x0 0x00010000>,
+		      <0x0 0xf0000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x4_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
+	pcie3x2: pcie@fe160000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x10 0x1f>;
+		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+				<0 0 0 2 &pcie3x2_intc 1>,
+				<0 0 0 3 &pcie3x2_intc 2>,
+				<0 0 0 4 &pcie3x2_intc 3>;
+		linux,pci-domain = <1>;
+		max-link-speed = <3>;
+		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		num-lanes = <2>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+		reg = <0xa 0x40400000 0x0 0x00400000>,
+		      <0x0 0xfe160000 0x0 0x00010000>,
+		      <0x0 0xf1000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x2_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
 	pcie2x1l0: pcie@fe170000 {
 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 		#address-cells = <3>;
@@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
 		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
 		status = "disabled";
 	};
+
+	pcie30phy: phy@fee80000 {
+		compatible = "rockchip,rk3588-pcie3-phy";
+		reg = <0x0 0xfee80000 0x0 0x20000>;
+		#phy-cells = <0>;
+		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_PCIE30_PHY>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <&php_grf>;
+		rockchip,phy-grf = <&pcie30_phy_grf>;
+		status = "disabled";
+	};
 };
-- 
2.40.1


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

Add both PCIe3 controllers together with the shared PHY.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
 1 file changed, 120 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
index 88d702575db2..8f210f002fac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
@@ -7,6 +7,11 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+	pcie30_phy_grf: syscon@fd5b8000 {
+		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
+		reg = <0x0 0xfd5b8000 0x0 0x10000>;
+	};
+
 	pipe_phy1_grf: syscon@fd5c0000 {
 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
 		reg = <0x0 0xfd5c0000 0x0 0x100>;
@@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
 		status = "disabled";
 	};
 
+	pcie3x4: pcie@fe150000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x00 0x0f>;
+		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
+			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
+			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+				<0 0 0 2 &pcie3x4_intc 1>,
+				<0 0 0 3 &pcie3x4_intc 2>,
+				<0 0 0 4 &pcie3x4_intc 3>;
+		linux,pci-domain = <0>;
+		max-link-speed = <3>;
+		msi-map = <0x0000 &its1 0x0000 0x1000>;
+		num-lanes = <4>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+		reg = <0xa 0x40000000 0x0 0x00400000>,
+		      <0x0 0xfe150000 0x0 0x00010000>,
+		      <0x0 0xf0000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x4_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
+	pcie3x2: pcie@fe160000 {
+		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x10 0x1f>;
+		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
+			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
+			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
+		clock-names = "aclk_mst", "aclk_slv",
+			      "aclk_dbi", "pclk",
+			      "aux", "pipe";
+		device_type = "pci";
+		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
+			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
+		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+		#interrupt-cells = <1>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
+				<0 0 0 2 &pcie3x2_intc 1>,
+				<0 0 0 3 &pcie3x2_intc 2>,
+				<0 0 0 4 &pcie3x2_intc 3>;
+		linux,pci-domain = <1>;
+		max-link-speed = <3>;
+		msi-map = <0x1000 &its1 0x1000 0x1000>;
+		num-lanes = <2>;
+		phys = <&pcie30phy>;
+		phy-names = "pcie-phy";
+		power-domains = <&power RK3588_PD_PCIE>;
+		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+		reg = <0xa 0x40400000 0x0 0x00400000>,
+		      <0x0 0xfe160000 0x0 0x00010000>,
+		      <0x0 0xf1000000 0x0 0x00100000>;
+		reg-names = "dbi", "apb", "config";
+		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+		reset-names = "pwr", "pipe";
+		status = "disabled";
+
+		pcie3x2_intc: legacy-interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
+		};
+	};
+
 	pcie2x1l0: pcie@fe170000 {
 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
 		#address-cells = <3>;
@@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
 		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
 		status = "disabled";
 	};
+
+	pcie30phy: phy@fee80000 {
+		compatible = "rockchip,rk3588-pcie3-phy";
+		reg = <0x0 0xfee80000 0x0 0x20000>;
+		#phy-cells = <0>;
+		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
+		clock-names = "pclk";
+		resets = <&cru SRST_PCIE30_PHY>;
+		reset-names = "phy";
+		rockchip,pipe-grf = <&php_grf>;
+		rockchip,phy-grf = <&pcie30_phy_grf>;
+		status = "disabled";
+	};
 };
-- 
2.40.1

Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> Add both PCIe3 controllers together with the shared PHY.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
>  1 file changed, 120 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 88d702575db2..8f210f002fac 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,11 @@
>  #include "rk3588-pinctrl.dtsi"
>  
>  / {
> +	pcie30_phy_grf: syscon@fd5b8000 {
> +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> +	};
> +
>  	pipe_phy1_grf: syscon@fd5c0000 {
>  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
>  		reg = <0x0 0xfd5c0000 0x0 0x100>;

Hi Sebastian,

What tree is based this on? Even after applying your PCIe2 series I don't have the above
node so the patch doesn't apply to mainline.

Best regards,
Liviu


> @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
>  		status = "disabled";
>  	};
>  
> +	pcie3x4: pcie@fe150000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x00 0x0f>;
> +		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
> +				<0 0 0 2 &pcie3x4_intc 1>,
> +				<0 0 0 3 &pcie3x4_intc 2>,
> +				<0 0 0 4 &pcie3x4_intc 3>;
> +		linux,pci-domain = <0>;
> +		max-link-speed = <3>;
> +		msi-map = <0x0000 &its1 0x0000 0x1000>;
> +		num-lanes = <4>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> +		reg = <0xa 0x40000000 0x0 0x00400000>,
> +		      <0x0 0xfe150000 0x0 0x00010000>,
> +		      <0x0 0xf0000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x4_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
> +	pcie3x2: pcie@fe160000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x10 0x1f>;
> +		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> +			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> +			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> +				<0 0 0 2 &pcie3x2_intc 1>,
> +				<0 0 0 3 &pcie3x2_intc 2>,
> +				<0 0 0 4 &pcie3x2_intc 3>;
> +		linux,pci-domain = <1>;
> +		max-link-speed = <3>;
> +		msi-map = <0x1000 &its1 0x1000 0x1000>;
> +		num-lanes = <2>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> +		reg = <0xa 0x40400000 0x0 0x00400000>,
> +		      <0x0 0xfe160000 0x0 0x00010000>,
> +		      <0x0 0xf1000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x2_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
>  	pcie2x1l0: pcie@fe170000 {
>  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
>  		#address-cells = <3>;
> @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
>  		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
>  		status = "disabled";
>  	};
> +
> +	pcie30phy: phy@fee80000 {
> +		compatible = "rockchip,rk3588-pcie3-phy";
> +		reg = <0x0 0xfee80000 0x0 0x20000>;
> +		#phy-cells = <0>;
> +		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
> +		clock-names = "pclk";
> +		resets = <&cru SRST_PCIE30_PHY>;
> +		reset-names = "phy";
> +		rockchip,pipe-grf = <&php_grf>;
> +		rockchip,phy-grf = <&pcie30_phy_grf>;
> +		status = "disabled";
> +	};
>  };
> -- 
> 2.40.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

-- 
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> Add both PCIe3 controllers together with the shared PHY.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
>  1 file changed, 120 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 88d702575db2..8f210f002fac 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,11 @@
>  #include "rk3588-pinctrl.dtsi"
>  
>  / {
> +	pcie30_phy_grf: syscon@fd5b8000 {
> +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> +	};
> +
>  	pipe_phy1_grf: syscon@fd5c0000 {
>  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
>  		reg = <0x0 0xfd5c0000 0x0 0x100>;

Hi Sebastian,

What tree is based this on? Even after applying your PCIe2 series I don't have the above
node so the patch doesn't apply to mainline.

Best regards,
Liviu


> @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
>  		status = "disabled";
>  	};
>  
> +	pcie3x4: pcie@fe150000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x00 0x0f>;
> +		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
> +				<0 0 0 2 &pcie3x4_intc 1>,
> +				<0 0 0 3 &pcie3x4_intc 2>,
> +				<0 0 0 4 &pcie3x4_intc 3>;
> +		linux,pci-domain = <0>;
> +		max-link-speed = <3>;
> +		msi-map = <0x0000 &its1 0x0000 0x1000>;
> +		num-lanes = <4>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> +		reg = <0xa 0x40000000 0x0 0x00400000>,
> +		      <0x0 0xfe150000 0x0 0x00010000>,
> +		      <0x0 0xf0000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x4_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
> +	pcie3x2: pcie@fe160000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x10 0x1f>;
> +		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> +			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> +			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> +				<0 0 0 2 &pcie3x2_intc 1>,
> +				<0 0 0 3 &pcie3x2_intc 2>,
> +				<0 0 0 4 &pcie3x2_intc 3>;
> +		linux,pci-domain = <1>;
> +		max-link-speed = <3>;
> +		msi-map = <0x1000 &its1 0x1000 0x1000>;
> +		num-lanes = <2>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> +		reg = <0xa 0x40400000 0x0 0x00400000>,
> +		      <0x0 0xfe160000 0x0 0x00010000>,
> +		      <0x0 0xf1000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x2_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
>  	pcie2x1l0: pcie@fe170000 {
>  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
>  		#address-cells = <3>;
> @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
>  		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
>  		status = "disabled";
>  	};
> +
> +	pcie30phy: phy@fee80000 {
> +		compatible = "rockchip,rk3588-pcie3-phy";
> +		reg = <0x0 0xfee80000 0x0 0x20000>;
> +		#phy-cells = <0>;
> +		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
> +		clock-names = "pclk";
> +		resets = <&cru SRST_PCIE30_PHY>;
> +		reset-names = "phy";
> +		rockchip,pipe-grf = <&php_grf>;
> +		rockchip,phy-grf = <&pcie30_phy_grf>;
> +		status = "disabled";
> +	};
>  };
> -- 
> 2.40.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> Add both PCIe3 controllers together with the shared PHY.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
>  1 file changed, 120 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 88d702575db2..8f210f002fac 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,11 @@
>  #include "rk3588-pinctrl.dtsi"
>  
>  / {
> +	pcie30_phy_grf: syscon@fd5b8000 {
> +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> +	};
> +
>  	pipe_phy1_grf: syscon@fd5c0000 {
>  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
>  		reg = <0x0 0xfd5c0000 0x0 0x100>;

Hi Sebastian,

What tree is based this on? Even after applying your PCIe2 series I don't have the above
node so the patch doesn't apply to mainline.

Best regards,
Liviu


> @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
>  		status = "disabled";
>  	};
>  
> +	pcie3x4: pcie@fe150000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x00 0x0f>;
> +		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
> +				<0 0 0 2 &pcie3x4_intc 1>,
> +				<0 0 0 3 &pcie3x4_intc 2>,
> +				<0 0 0 4 &pcie3x4_intc 3>;
> +		linux,pci-domain = <0>;
> +		max-link-speed = <3>;
> +		msi-map = <0x0000 &its1 0x0000 0x1000>;
> +		num-lanes = <4>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> +		reg = <0xa 0x40000000 0x0 0x00400000>,
> +		      <0x0 0xfe150000 0x0 0x00010000>,
> +		      <0x0 0xf0000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x4_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
> +	pcie3x2: pcie@fe160000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x10 0x1f>;
> +		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> +			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> +			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> +				<0 0 0 2 &pcie3x2_intc 1>,
> +				<0 0 0 3 &pcie3x2_intc 2>,
> +				<0 0 0 4 &pcie3x2_intc 3>;
> +		linux,pci-domain = <1>;
> +		max-link-speed = <3>;
> +		msi-map = <0x1000 &its1 0x1000 0x1000>;
> +		num-lanes = <2>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> +		reg = <0xa 0x40400000 0x0 0x00400000>,
> +		      <0x0 0xfe160000 0x0 0x00010000>,
> +		      <0x0 0xf1000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x2_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
>  	pcie2x1l0: pcie@fe170000 {
>  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
>  		#address-cells = <3>;
> @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
>  		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
>  		status = "disabled";
>  	};
> +
> +	pcie30phy: phy@fee80000 {
> +		compatible = "rockchip,rk3588-pcie3-phy";
> +		reg = <0x0 0xfee80000 0x0 0x20000>;
> +		#phy-cells = <0>;
> +		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
> +		clock-names = "pclk";
> +		resets = <&cru SRST_PCIE30_PHY>;
> +		reset-names = "phy";
> +		rockchip,pipe-grf = <&php_grf>;
> +		rockchip,phy-grf = <&pcie30_phy_grf>;
> +		status = "disabled";
> +	};
>  };
> -- 
> 2.40.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> Add both PCIe3 controllers together with the shared PHY.
> 
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
>  1 file changed, 120 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> index 88d702575db2..8f210f002fac 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> @@ -7,6 +7,11 @@
>  #include "rk3588-pinctrl.dtsi"
>  
>  / {
> +	pcie30_phy_grf: syscon@fd5b8000 {
> +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> +	};
> +
>  	pipe_phy1_grf: syscon@fd5c0000 {
>  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
>  		reg = <0x0 0xfd5c0000 0x0 0x100>;

Hi Sebastian,

What tree is based this on? Even after applying your PCIe2 series I don't have the above
node so the patch doesn't apply to mainline.

Best regards,
Liviu


> @@ -80,6 +85,108 @@ i2s10_8ch: i2s@fde00000 {
>  		status = "disabled";
>  	};
>  
> +	pcie3x4: pcie@fe150000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x00 0x0f>;
> +		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
> +			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
> +			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
> +				<0 0 0 2 &pcie3x4_intc 1>,
> +				<0 0 0 3 &pcie3x4_intc 2>,
> +				<0 0 0 4 &pcie3x4_intc 3>;
> +		linux,pci-domain = <0>;
> +		max-link-speed = <3>;
> +		msi-map = <0x0000 &its1 0x0000 0x1000>;
> +		num-lanes = <4>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
> +		reg = <0xa 0x40000000 0x0 0x00400000>,
> +		      <0x0 0xfe150000 0x0 0x00010000>,
> +		      <0x0 0xf0000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x4_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
> +	pcie3x2: pcie@fe160000 {
> +		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x10 0x1f>;
> +		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
> +			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
> +			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
> +		clock-names = "aclk_mst", "aclk_slv",
> +			      "aclk_dbi", "pclk",
> +			      "aux", "pipe";
> +		device_type = "pci";
> +		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
> +			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
> +		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> +		#interrupt-cells = <1>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
> +				<0 0 0 2 &pcie3x2_intc 1>,
> +				<0 0 0 3 &pcie3x2_intc 2>,
> +				<0 0 0 4 &pcie3x2_intc 3>;
> +		linux,pci-domain = <1>;
> +		max-link-speed = <3>;
> +		msi-map = <0x1000 &its1 0x1000 0x1000>;
> +		num-lanes = <2>;
> +		phys = <&pcie30phy>;
> +		phy-names = "pcie-phy";
> +		power-domains = <&power RK3588_PD_PCIE>;
> +		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
> +			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
> +			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
> +		reg = <0xa 0x40400000 0x0 0x00400000>,
> +		      <0x0 0xfe160000 0x0 0x00010000>,
> +		      <0x0 0xf1000000 0x0 0x00100000>;
> +		reg-names = "dbi", "apb", "config";
> +		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
> +		reset-names = "pwr", "pipe";
> +		status = "disabled";
> +
> +		pcie3x2_intc: legacy-interrupt-controller {
> +			interrupt-controller;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-parent = <&gic>;
> +			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
> +		};
> +	};
> +
>  	pcie2x1l0: pcie@fe170000 {
>  		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
>  		#address-cells = <3>;
> @@ -218,4 +325,17 @@ combphy1_ps: phy@fee10000 {
>  		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
>  		status = "disabled";
>  	};
> +
> +	pcie30phy: phy@fee80000 {
> +		compatible = "rockchip,rk3588-pcie3-phy";
> +		reg = <0x0 0xfee80000 0x0 0x20000>;
> +		#phy-cells = <0>;
> +		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
> +		clock-names = "pclk";
> +		resets = <&cru SRST_PCIE30_PHY>;
> +		reset-names = "phy";
> +		rockchip,pipe-grf = <&php_grf>;
> +		rockchip,phy-grf = <&pcie30_phy_grf>;
> +		status = "disabled";
> +	};
>  };
> -- 
> 2.40.1
> 
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip

-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1406 bytes --]

Hi Liviu,

On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > Add both PCIe3 controllers together with the shared PHY.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> >  1 file changed, 120 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 88d702575db2..8f210f002fac 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,11 @@
> >  #include "rk3588-pinctrl.dtsi"
> >  
> >  / {
> > +	pcie30_phy_grf: syscon@fd5b8000 {
> > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > +	};
> > +
> >  	pipe_phy1_grf: syscon@fd5c0000 {
> >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> 
> What tree is based this on? Even after applying your PCIe2 series I don't have the above
> node so the patch doesn't apply to mainline.

You are missing naneng-combphy support:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

-- Sebastian

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[-- Attachment #2: Type: text/plain, Size: 112 bytes --]

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1406 bytes --]

Hi Liviu,

On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > Add both PCIe3 controllers together with the shared PHY.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> >  1 file changed, 120 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 88d702575db2..8f210f002fac 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,11 @@
> >  #include "rk3588-pinctrl.dtsi"
> >  
> >  / {
> > +	pcie30_phy_grf: syscon@fd5b8000 {
> > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > +	};
> > +
> >  	pipe_phy1_grf: syscon@fd5c0000 {
> >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> 
> What tree is based this on? Even after applying your PCIe2 series I don't have the above
> node so the patch doesn't apply to mainline.

You are missing naneng-combphy support:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

-- Sebastian

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1406 bytes --]

Hi Liviu,

On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > Add both PCIe3 controllers together with the shared PHY.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> >  1 file changed, 120 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 88d702575db2..8f210f002fac 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,11 @@
> >  #include "rk3588-pinctrl.dtsi"
> >  
> >  / {
> > +	pcie30_phy_grf: syscon@fd5b8000 {
> > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > +	};
> > +
> >  	pipe_phy1_grf: syscon@fd5c0000 {
> >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> 
> What tree is based this on? Even after applying your PCIe2 series I don't have the above
> node so the patch doesn't apply to mainline.

You are missing naneng-combphy support:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

-- Sebastian

[-- Attachment #1.2: signature.asc --]
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1406 bytes --]

Hi Liviu,

On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > Add both PCIe3 controllers together with the shared PHY.
> > 
> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > ---
> >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> >  1 file changed, 120 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > index 88d702575db2..8f210f002fac 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > @@ -7,6 +7,11 @@
> >  #include "rk3588-pinctrl.dtsi"
> >  
> >  / {
> > +	pcie30_phy_grf: syscon@fd5b8000 {
> > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > +	};
> > +
> >  	pipe_phy1_grf: syscon@fd5c0000 {
> >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> 
> What tree is based this on? Even after applying your PCIe2 series I don't have the above
> node so the patch doesn't apply to mainline.

You are missing naneng-combphy support:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

-- Sebastian

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> Hi Liviu,
> 
> On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > Add both PCIe3 controllers together with the shared PHY.
> > > 
> > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> > >  1 file changed, 120 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > index 88d702575db2..8f210f002fac 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > @@ -7,6 +7,11 @@
> > >  #include "rk3588-pinctrl.dtsi"
> > >  
> > >  / {
> > > +	pcie30_phy_grf: syscon@fd5b8000 {
> > > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > +	};
> > > +
> > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > 
> > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > node so the patch doesn't apply to mainline.
> 
> You are missing naneng-combphy support:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
use, otherwise the DTS fail to compile.

Best regards,
Liviu

> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> Hi Liviu,
> 
> On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > Add both PCIe3 controllers together with the shared PHY.
> > > 
> > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> > >  1 file changed, 120 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > index 88d702575db2..8f210f002fac 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > @@ -7,6 +7,11 @@
> > >  #include "rk3588-pinctrl.dtsi"
> > >  
> > >  / {
> > > +	pcie30_phy_grf: syscon@fd5b8000 {
> > > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > +	};
> > > +
> > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > 
> > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > node so the patch doesn't apply to mainline.
> 
> You are missing naneng-combphy support:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
use, otherwise the DTS fail to compile.

Best regards,
Liviu

> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> Hi Liviu,
> 
> On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > Add both PCIe3 controllers together with the shared PHY.
> > > 
> > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> > >  1 file changed, 120 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > index 88d702575db2..8f210f002fac 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > @@ -7,6 +7,11 @@
> > >  #include "rk3588-pinctrl.dtsi"
> > >  
> > >  / {
> > > +	pcie30_phy_grf: syscon@fd5b8000 {
> > > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > +	};
> > > +
> > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > 
> > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > node so the patch doesn't apply to mainline.
> 
> You are missing naneng-combphy support:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
use, otherwise the DTS fail to compile.

Best regards,
Liviu

> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> Hi Liviu,
> 
> On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > Add both PCIe3 controllers together with the shared PHY.
> > > 
> > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> > > ---
> > >  arch/arm64/boot/dts/rockchip/rk3588.dtsi | 120 +++++++++++++++++++++++
> > >  1 file changed, 120 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588.dtsi b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > index 88d702575db2..8f210f002fac 100644
> > > --- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
> > > @@ -7,6 +7,11 @@
> > >  #include "rk3588-pinctrl.dtsi"
> > >  
> > >  / {
> > > +	pcie30_phy_grf: syscon@fd5b8000 {
> > > +		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
> > > +		reg = <0x0 0xfd5b8000 0x0 0x10000>;
> > > +	};
> > > +
> > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > 
> > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > node so the patch doesn't apply to mainline.
> 
> You are missing naneng-combphy support:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708

Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
use, otherwise the DTS fail to compile.

Best regards,
Liviu

> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1228 bytes --]

Hi,

On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > 
> > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > node so the patch doesn't apply to mainline.
> > 
> > You are missing naneng-combphy support:
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> 
> Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> use, otherwise the DTS fail to compile.

Yes, that's also already in linux-next:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

Greetings,

-- Sebastian

[-- Attachment #1.2: signature.asc --]
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1228 bytes --]

Hi,

On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > 
> > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > node so the patch doesn't apply to mainline.
> > 
> > You are missing naneng-combphy support:
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> 
> Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> use, otherwise the DTS fail to compile.

Yes, that's also already in linux-next:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

Greetings,

-- Sebastian

[-- Attachment #1.2: signature.asc --]
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1228 bytes --]

Hi,

On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > 
> > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > node so the patch doesn't apply to mainline.
> > 
> > You are missing naneng-combphy support:
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> 
> Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> use, otherwise the DTS fail to compile.

Yes, that's also already in linux-next:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

Greetings,

-- Sebastian

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1228 bytes --]

Hi,

On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > 
> > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > node so the patch doesn't apply to mainline.
> > 
> > You are missing naneng-combphy support:
> > 
> > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> 
> Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> use, otherwise the DTS fail to compile.

Yes, that's also already in linux-next:

https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

Greetings,

-- Sebastian

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

Hi Sebastian,

On Tue, Jul 18, 2023 at 11:06:01PM +0200, Sebastian Reichel wrote:
> Hi,
> 
> On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > > 
> > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > > node so the patch doesn't apply to mainline.
> > > 
> > > You are missing naneng-combphy support:
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> > 
> > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> > use, otherwise the DTS fail to compile.
> 
> Yes, that's also already in linux-next:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

I'm reading that as: "relevant patch that this series depends on has already
been added to the tree that's going to pull this PCIe2 series so all will be
good". Otherwise I think there should be some mention in the cover letter
about dependencies, so that people like me don't report issues just because
they are not using the linux-rockchip tree by default.

Many thanks for the quick answers and the links to fix my tree.

Best regards,
Liviu

> 
> Greetings,
> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

Hi Sebastian,

On Tue, Jul 18, 2023 at 11:06:01PM +0200, Sebastian Reichel wrote:
> Hi,
> 
> On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > > 
> > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > > node so the patch doesn't apply to mainline.
> > > 
> > > You are missing naneng-combphy support:
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> > 
> > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> > use, otherwise the DTS fail to compile.
> 
> Yes, that's also already in linux-next:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

I'm reading that as: "relevant patch that this series depends on has already
been added to the tree that's going to pull this PCIe2 series so all will be
good". Otherwise I think there should be some mention in the cover letter
about dependencies, so that people like me don't report issues just because
they are not using the linux-rockchip tree by default.

Many thanks for the quick answers and the links to fix my tree.

Best regards,
Liviu

> 
> Greetings,
> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

Hi Sebastian,

On Tue, Jul 18, 2023 at 11:06:01PM +0200, Sebastian Reichel wrote:
> Hi,
> 
> On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > > 
> > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > > node so the patch doesn't apply to mainline.
> > > 
> > > You are missing naneng-combphy support:
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> > 
> > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> > use, otherwise the DTS fail to compile.
> 
> Yes, that's also already in linux-next:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

I'm reading that as: "relevant patch that this series depends on has already
been added to the tree that's going to pull this PCIe2 series so all will be
good". Otherwise I think there should be some mention in the cover letter
about dependencies, so that people like me don't report issues just because
they are not using the linux-rockchip tree by default.

Many thanks for the quick answers and the links to fix my tree.

Best regards,
Liviu

> 
> Greetings,
> 
> -- Sebastian



-- 
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Re: [PATCH v2 2/2] arm64: dts: rockchip: rk3588: add PCIe3 support

[Liviu Dudau]

Hi Sebastian,

On Tue, Jul 18, 2023 at 11:06:01PM +0200, Sebastian Reichel wrote:
> Hi,
> 
> On Tue, Jul 18, 2023 at 08:38:36PM +0100, Liviu Dudau wrote:
> > On Tue, Jul 18, 2023 at 06:01:37PM +0200, Sebastian Reichel wrote:
> > > On Tue, Jul 18, 2023 at 04:09:53PM +0100, Liviu Dudau wrote:
> > > > On Mon, Jul 17, 2023 at 07:35:12PM +0200, Sebastian Reichel wrote:
> > > > >  	pipe_phy1_grf: syscon@fd5c0000 {
> > > > >  		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
> > > > >  		reg = <0x0 0xfd5c0000 0x0 0x100>;
> > > > 
> > > > What tree is based this on? Even after applying your PCIe2 series I don't have the above
> > > > node so the patch doesn't apply to mainline.
> > > 
> > > You are missing naneng-combphy support:
> > > 
> > > https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=6ebd55b3bba383e0523b0c014f17c97f3ce80708
> > 
> > Thanks! It looks like the PCIe2 commit that adds support to rk3588(s).dtsi
> > files is also missing an #include <dt-bindings/phy/phy.h> for the PHY_TYPE_PCIE
> > use, otherwise the DTS fail to compile.
> 
> Yes, that's also already in linux-next:
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=v6.6-armsoc/dts64&id=34d6c15d8e86256ef2456c604b1c8d8242720871

I'm reading that as: "relevant patch that this series depends on has already
been added to the tree that's going to pull this PCIe2 series so all will be
good". Otherwise I think there should be some mention in the cover letter
about dependencies, so that people like me don't report issues just because
they are not using the linux-rockchip tree by default.

Many thanks for the quick answers and the links to fix my tree.

Best regards,
Liviu

> 
> Greetings,
> 
> -- Sebastian



-- 
Everyone who uses computers frequently has had, from time to time,
a mad desire to attack the precocious abacus with an axe.
       	   	      	     	  -- John D. Clark, Ignition!

Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Vinod Koul]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
      commit: f66782cff479807ad7e98f0cf6a0c0babfe0159b

Best regards,
-- 
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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Vinod Koul]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
      commit: f66782cff479807ad7e98f0cf6a0c0babfe0159b

Best regards,
-- 
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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Vinod Koul]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
      commit: f66782cff479807ad7e98f0cf6a0c0babfe0159b

Best regards,
-- 
~Vinod



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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Vinod Koul]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[1/2] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
      commit: f66782cff479807ad7e98f0cf6a0c0babfe0159b

Best regards,
-- 
~Vinod

Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
      commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
      commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> This adds PCIe v3 support for RK3588. The series depends on the PCIe
> v2 series [0], since the the same binding is used. It has been tested
> on Rockchip EVB1 and Radxa Rock 5B.
> 
> Note, that the PCIe3 PHY driver is currently missing bifurcation
> support for RK3588. Thus after this series only PCIe3x4 is usable
> (in aggregated x4 mode) without adding support for the PHY's
> "rockchip,pcie30-phymode" DT property, which allows configuring
> how the lanes are distributed. Aggregated 3x4 mode seems to be the
> most common configuration. Both EVB1 and Rock 5B use it, so I
> cannot test anything else anyways.
> 
> [...]

Applied, thanks!

[2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
      commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>

Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1191 bytes --]

Hi Heiko,

On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > v2 series [0], since the the same binding is used. It has been tested
> > on Rockchip EVB1 and Radxa Rock 5B.
> > 
> > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > support for RK3588. Thus after this series only PCIe3x4 is usable
> > (in aggregated x4 mode) without adding support for the PHY's
> > "rockchip,pcie30-phymode" DT property, which allows configuring
> > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > most common configuration. Both EVB1 and Rock 5B use it, so I
> > cannot test anything else anyways.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
>       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Applying this without the PCIe 2 series being applied introduces
warnings for the RK3588 dtbs_check, as mentioned in the second
setence of the text you quoted :)

(FWIW RK356x already has the same warnings, though)

-- Sebastian

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[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 112 bytes --]

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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

[-- Attachment #1.1: Type: text/plain, Size: 1191 bytes --]

Hi Heiko,

On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > v2 series [0], since the the same binding is used. It has been tested
> > on Rockchip EVB1 and Radxa Rock 5B.
> > 
> > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > support for RK3588. Thus after this series only PCIe3x4 is usable
> > (in aggregated x4 mode) without adding support for the PHY's
> > "rockchip,pcie30-phymode" DT property, which allows configuring
> > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > most common configuration. Both EVB1 and Rock 5B use it, so I
> > cannot test anything else anyways.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
>       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Applying this without the PCIe 2 series being applied introduces
warnings for the RK3588 dtbs_check, as mentioned in the second
setence of the text you quoted :)

(FWIW RK356x already has the same warnings, though)

-- Sebastian

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 170 bytes --]

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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Sebastian Reichel]

[-- Attachment #1: Type: text/plain, Size: 1191 bytes --]

Hi Heiko,

On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > v2 series [0], since the the same binding is used. It has been tested
> > on Rockchip EVB1 and Radxa Rock 5B.
> > 
> > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > support for RK3588. Thus after this series only PCIe3x4 is usable
> > (in aggregated x4 mode) without adding support for the PHY's
> > "rockchip,pcie30-phymode" DT property, which allows configuring
> > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > most common configuration. Both EVB1 and Rock 5B use it, so I
> > cannot test anything else anyways.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
>       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e

Applying this without the PCIe 2 series being applied introduces
warnings for the RK3588 dtbs_check, as mentioned in the second
setence of the text you quoted :)

(FWIW RK356x already has the same warnings, though)

-- Sebastian

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

Am Montag, 24. Juli 2023, 21:22:23 CEST schrieb Sebastian Reichel:
> Hi Heiko,
> 
> On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> > On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > > v2 series [0], since the the same binding is used. It has been tested
> > > on Rockchip EVB1 and Radxa Rock 5B.
> > > 
> > > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > > support for RK3588. Thus after this series only PCIe3x4 is usable
> > > (in aggregated x4 mode) without adding support for the PHY's
> > > "rockchip,pcie30-phymode" DT property, which allows configuring
> > > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > > most common configuration. Both EVB1 and Rock 5B use it, so I
> > > cannot test anything else anyways.
> > > 
> > > [...]
> > 
> > Applied, thanks!
> > 
> > [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
> >       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e
> 
> Applying this without the PCIe 2 series being applied introduces
> warnings for the RK3588 dtbs_check, as mentioned in the second
> setence of the text you quoted :)
> 
> (FWIW RK356x already has the same warnings, though)

darn, I didn't do a full binding check, only a "compiles" check
after applying. We're at rc3 now, so I would hope that the pcie2
binding changes get applied soon'ish so I can then also pick up the
dts change from there.


Heiko



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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

Am Montag, 24. Juli 2023, 21:22:23 CEST schrieb Sebastian Reichel:
> Hi Heiko,
> 
> On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> > On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > > v2 series [0], since the the same binding is used. It has been tested
> > > on Rockchip EVB1 and Radxa Rock 5B.
> > > 
> > > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > > support for RK3588. Thus after this series only PCIe3x4 is usable
> > > (in aggregated x4 mode) without adding support for the PHY's
> > > "rockchip,pcie30-phymode" DT property, which allows configuring
> > > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > > most common configuration. Both EVB1 and Rock 5B use it, so I
> > > cannot test anything else anyways.
> > > 
> > > [...]
> > 
> > Applied, thanks!
> > 
> > [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
> >       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e
> 
> Applying this without the PCIe 2 series being applied introduces
> warnings for the RK3588 dtbs_check, as mentioned in the second
> setence of the text you quoted :)
> 
> (FWIW RK356x already has the same warnings, though)

darn, I didn't do a full binding check, only a "compiles" check
after applying. We're at rc3 now, so I would hope that the pcie2
binding changes get applied soon'ish so I can then also pick up the
dts change from there.


Heiko



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Re: (subset) [PATCH v2 0/2] RK3588 PCIe3 support

[Heiko Stuebner]

Am Montag, 24. Juli 2023, 21:22:23 CEST schrieb Sebastian Reichel:
> Hi Heiko,
> 
> On Mon, Jul 24, 2023 at 09:12:35PM +0200, Heiko Stuebner wrote:
> > On Mon, 17 Jul 2023 19:35:10 +0200, Sebastian Reichel wrote:
> > > This adds PCIe v3 support for RK3588. The series depends on the PCIe
> > > v2 series [0], since the the same binding is used. It has been tested
> > > on Rockchip EVB1 and Radxa Rock 5B.
> > > 
> > > Note, that the PCIe3 PHY driver is currently missing bifurcation
> > > support for RK3588. Thus after this series only PCIe3x4 is usable
> > > (in aggregated x4 mode) without adding support for the PHY's
> > > "rockchip,pcie30-phymode" DT property, which allows configuring
> > > how the lanes are distributed. Aggregated 3x4 mode seems to be the
> > > most common configuration. Both EVB1 and Rock 5B use it, so I
> > > cannot test anything else anyways.
> > > 
> > > [...]
> > 
> > Applied, thanks!
> > 
> > [2/2] arm64: dts: rockchip: rk3588: add PCIe3 support
> >       commit: 0acf4fa7f187cd7e3dad93f1ee14e9509687621e
> 
> Applying this without the PCIe 2 series being applied introduces
> warnings for the RK3588 dtbs_check, as mentioned in the second
> setence of the text you quoted :)
> 
> (FWIW RK356x already has the same warnings, though)

darn, I didn't do a full binding check, only a "compiles" check
after applying. We're at rc3 now, so I would hope that the pcie2
binding changes get applied soon'ish so I can then also pick up the
dts change from there.


Heiko