Re: [PATCH v10 05/28] x86/cea: Use array indexing to simplify exception stack access

[Binbin Wu <binbin.wu@linux.intel.com>]

On 9/12/2026 5:36 AM, Sohil Mehta wrote:
> From: "Xin Li (Intel)" <xin@zytor.com>
> 
> Refactor struct cea_exception_stacks to leverage array indexing for
> exception stack access, improving code clarity and eliminating the
> need for the ESTACKS_MEMBERS() macro.
> 
> Convert __this_cpu_ist_{bottom,top}_va() from macros to functions,
> allowing removal of the now-obsolete CEA_ESTACK_BOT and CEA_ESTACK_TOP
> macros.
> 
> Also drop CEA_ESTACK_SIZE, which just duplicated EXCEPTION_STKSZ.
> 
> Signed-off-by: Xin Li (Intel) <xin@zytor.com>
> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
> Acked-by: Dave Hansen <dave.hansen@linux.intel.com>

Reviewed-by: Binbin Wu <binbin.wu@linux.intel.com>

One nit below.

[...]>  
> +/*
> + * The exception stack ordering in [cea_]exception_stacks
> + */
> +enum exception_stack_ordering {
> +	ESTACK_DF,
> +	ESTACK_NMI,
> +	ESTACK_DB,
> +	ESTACK_MCE,
> +	ESTACK_VC,
> +	ESTACK_VC2,
> +	N_EXCEPTION_STACKS
> +};
> +
>  /* Macro to enforce the same ordering and stack sizes */

Nit:
Is this still hold ? ...

>  #define ESTACKS_MEMBERS(guardsize, optional_stack_size)		\
>  	char	ESTACK_DF_stack_guard[guardsize];		\
> @@ -39,37 +52,22 @@ struct exception_stacks {
>  
>  /* The effective cpu entry area mapping with guard pages. */
>  struct cea_exception_stacks {
> -	ESTACKS_MEMBERS(PAGE_SIZE, EXCEPTION_STKSZ)
> +	struct {
> +		char stack_guard[PAGE_SIZE];
> +		char stack[EXCEPTION_STKSZ];
> +	} event_stacks[N_EXCEPTION_STACKS];
> +	char IST_top_guard[PAGE_SIZE];

... Before this change, ESTACKS_MEMBERS() is used both in exception_stacks and
cea_exception_stacks, so ESTACKS_MEMBERS() can enforce the order and stack
sizes.

After the change, ESTACKS_MEMBERS() only used in one place, so it doesn't have
the capability to enforce them.

The order consistency depends on the consistency b/t ESTACKS_MEMBERS and
enum exception_stack_ordering now.

>  };

[...]