From: Christian Marangi <ansuelsmth@gmail.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Vladimir Oltean <olteanv@gmail.com>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiner Kallweit <hkallweit1@gmail.com>,
Russell King <linux@armlinux.org.uk>,
Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, netdev@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [net-next RFC PATCH v2 3/3] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
Date: Fri, 25 Oct 2024 13:01:31 +0200 [thread overview]
Message-ID: <671b7a8f.050a0220.5b160.446a@mx.google.com> (raw)
In-Reply-To: <67192d40.5d0a0220.33f6c1.23bc@mx.google.com>
On Wed, Oct 23, 2024 at 07:07:08PM +0200, Christian Marangi wrote:
> On Wed, Oct 23, 2024 at 07:00:22PM +0200, Andrew Lunn wrote:
> > > +static int an8855_config_init(struct phy_device *phydev)
> > > +{
> > > + struct air_an8855_priv *priv = phydev->priv;
> > > + int ret;
> > > +
> > > + /* Enable HW auto downshift */
> > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_EXT_PAGE);
> > > + if (ret)
> > > + return ret;
> > > + ret = phy_set_bits(phydev, AN8855_PHY_EXT_REG_14,
> > > + AN8855_PHY_EN_DOWN_SHFIT);
> > > + if (ret)
> > > + return ret;
> > > + ret = phy_write(phydev, AN8855_PHY_PAGE_CTRL, AN8855_PHY_NORMAL_PAGE);
> > > + if (ret)
> > > + return ret;
> >
> > There are locking issues here, which is why we have the helpers
> > phy_select_page() and phy_restore_page(). The air_en8811h.c gets this
> > right.
>
> Ugh didn't think about it... The switch address is shared with the PHY
> so yes this is a problem.
>
> Consider that this page thing comes from my speculation... Not really
> use if 1f select page...
> From what I observed
> 0x0 PHY page
> 0x1 this strange EXT
> 0x4 acess switch register (every PHY can access the switch)
>
Just to followup on this... I checked air_en8811h registers again and
they match MII access to the switch so yes my speculation is correct.
Also extra happy since I now know what those magic values means at least
for MII.
> >
> > Is there anything in common with the en8811h? Does it also support
> > downshift? Can its LED code be used here?
> >
>
> For some reason part of the LED are controlled by the switch and some
> are by the PHY. I still have to investigate that (not giving priority to
> it... just on my todo)
>
> For downshift as you notice it's a single bit with no count...
> From their comments in the original driver it's said "Enable HW
> autodownshift"
>
> Trying to reach them but currently it's all very obscure.
>
> --
> Ansuel
--
Ansuel
prev parent reply other threads:[~2024-10-25 11:20 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-23 16:19 [net-next RFC PATCH v2 0/3] net: dsa: Add Airoha AN8855 support Christian Marangi
2024-10-23 16:19 ` [net-next RFC PATCH v2 1/3] dt-bindings: net: dsa: Add Airoha AN8855 Gigabit Switch documentation Christian Marangi
2024-10-23 17:08 ` Andrew Lunn
2024-10-23 17:14 ` Christian Marangi
2024-10-23 17:39 ` Andrew Lunn
2024-10-23 17:45 ` Christian Marangi
2024-10-24 15:23 ` Rob Herring
2024-10-23 16:19 ` [net-next RFC PATCH v2 2/3] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
2024-10-27 3:14 ` kernel test robot
2024-10-27 3:45 ` kernel test robot
2024-10-23 16:19 ` [net-next RFC PATCH v2 3/3] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
2024-10-23 16:53 ` Andrew Lunn
2024-10-25 10:59 ` Christian Marangi
2024-10-25 12:56 ` Andrew Lunn
2024-10-23 17:00 ` Andrew Lunn
2024-10-23 17:07 ` Christian Marangi
2024-10-25 11:01 ` Christian Marangi [this message]
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