From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
To: Andrew Jones <ajones@ventanamicro.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, alistair.francis@wdc.com, bmeng.cn@gmail.com
Subject: Re: [PATCH] target/riscv/kvm: Fix leak of reg list
Date: Mon, 4 Nov 2024 14:43:57 -0300 [thread overview]
Message-ID: <682ad778-e714-46f8-ba44-e0afdf6f69b4@ventanamicro.com> (raw)
In-Reply-To: <20241104173551.125069-2-ajones@ventanamicro.com>
On 11/4/24 2:35 PM, Andrew Jones wrote:
> Free the temporary register list.
>
> Fixes: 608bdebb6075 ("target/riscv/kvm: support KVM_GET_REG_LIST")
> Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
> ---
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> target/riscv/kvm/kvm-cpu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
> index cbda4596da73..effd8fed815d 100644
> --- a/target/riscv/kvm/kvm-cpu.c
> +++ b/target/riscv/kvm/kvm-cpu.c
> @@ -1170,6 +1170,8 @@ static void kvm_riscv_init_multiext_cfg(RISCVCPU *cpu, KVMScratchCPU *kvmcpu)
> }
>
> kvm_riscv_check_sbi_dbcn_support(cpu, kvmcpu, reglist);
> +
> + g_free(reglist);
> }
>
> static void riscv_init_kvm_registers(Object *cpu_obj)
next prev parent reply other threads:[~2024-11-04 17:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-04 17:35 [PATCH] target/riscv/kvm: Fix leak of reg list Andrew Jones
2024-11-04 17:43 ` Daniel Henrique Barboza [this message]
2024-11-04 22:59 ` Alistair Francis
2024-11-04 23:03 ` Alistair Francis
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